Abstract: A circuit includes a first memory cell and a data control circuit configured to provide first data and second data. The first memory cell has a first port and a second port. The first data is written from the first port to the first memory cell. The second data is based on information of the first data. The second port is configured to write the second data to the first memory cell based on a detection of a write disturb caused by the second port to the first port.

Abstract: A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.

Abstract: Disclosed is an in-memory computing device including a memory array with non-volatile memory cells arranged in rows and columns; a multiple row decoder to activate at least two cells in a column of the memory array at the same time to generate a parametric change in a bit line connected to at least one cell in the column; and circuitry to write data associated with the parametric change into the memory array. Additionally disclosed is a method of computing inside a memory array including non-volatile memory cells arranged in rows and columns, the method includes activating at least two cells in a column of the memory array at the same time to generate a parametric change in a bit line connected to at least one cell in the column; and writing data associated with the parametric change into the memory array.

Abstract: A memory device includes a memory array, an array gap, a voltage provider, and a voltage divider. The voltage provider is disposed in the array gap and coupled to a column of memory cells of the memory array for providing a first voltage to the column of memory cells when a memory cell of the column is selected at a write cycle. The voltage provider is coupled to the voltage provider and the column of memory cells for providing a second voltage lower than the first voltage to the column of memory cells when the memory of the column is half selected at the write cycle.

Abstract: An integrated circuit includes one or more bit cells, a word line coupled to the one or more bit cells, and a dummy word line arranged with the word line to have a capacitance therebetween. The capacitance provides a voltage boost or reduction of the word line to assist read and write operations.

Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.

Abstract: A semiconductor memory device includes a memory cell array having memory cells coupled to a plurality of word lines and a peripheral circuit group configured to supply a pass voltage to unselected word lines among the plurality of word lines, wherein the peripheral circuit group stepwise raises the pass voltage supplied to the unselected word lines to a target level.

Abstract: A bias voltage generator and generating method for a reference cell are provided. The bias voltage generator includes a data read detector, a cut-off signal generator and an output stage circuit. The data read detector generates a detection signal according to transition points of a sense amplifier enable signal and a sense amplifier latch signal. The cut-off signal generator delays the detection signal a delay time to generate a cut-off signal, wherein a start-up time of the cut-off signal is decided by the detection signal and the delay time. The output stage circuit starts or stops to provide a bias-voltage providing signal according to the cut-off signal.

Abstract: A data input/output (I/O) device includes a plurality of data units and an I/O assembly. The plurality of data units is coupled to a global I/O (GIO) line through corresponding local I/O (LIO) lines and configured to receive or transmit a plurality of data groups through the corresponding LIO lines. At least one of the plurality of data units have a different operation speed. The I/O assembly performs serial/parallel conversion operations on the plurality of data groups including a high-speed data group and outputs results of the serial/parallel conversion operations. The high-speed data group is output from the at least one of the plurality of data units having the different operation speed.

Abstract: A memory system includes a first, second and third storing area included in a volatile semiconductor memory, and a controller that allocates the storage area of the nonvolatile semiconductor memory to the second storing area and the third storing area in a logical block unit associated with one or more blocks. First and second management units respectively manage the second and third storing areas. The second management unit has a size larger than that of the first management unit. When flushing data from the first to the second or third storing areas, the controller collects, from at least one of the first, second and third storing areas, data other than the data to be flushed and controls the flushing of the data such that a total of the data is a natural number times as large as the block unit as much as possible.

Abstract: According to one embodiment, a non-volatile semiconductor storage device includes a memory cell array, a row decoder, a potential generating circuit, first plural potential selection circuits, a second potential selection circuit, a first discharge circuit, and a second discharge circuit. The first plural potential selection circuits select one of output potentials of the potential generating circuit by receiving a first control signal and apply the selected output potential to a first signal line. The second potential selection circuit applies a potential of the first signal line to a second signal line connected to the row decoder by receiving a second control signal. The first discharge circuit is arranged in the first potential selection circuit. The second discharge circuit is arranged in the second potential selection circuit.

Abstract: A memory system including a non-volatile memory device and a memory controller is provided. When a read operation on a first data initially output from the non-volatile memory device during a first read operation is successful, the memory controller may change a read voltage for reading a second data stored in the non-volatile memory device during a second read operation.

Abstract: Decoding and decoder circuits in memory devices are disclosed. Array lines are biased or floated as memory device operations are performed in the memory device. In at least one embodiment, a decoder circuit includes complementary devices to bias array lines or float array lines in a memory device while particular memory device operations are performed.

Abstract: According to some embodiments, an electronic circuit comprises a digital output which is held to a logic one after the power supply was removed, for a time duration in a narrow range. The electronic circuit comprises a first array of elements comprising capacitors and discharging devices (diodes or transistors). A time constant detector detects which elements has the discharging time closest to the target. A second array of elements also comprises capacitors and discharging devices, with discharging durations proportional to the discharging durations of the first array. A decoder charges the appropriate element from the second array. After the power is removed, this charged element starts to discharge. During the discharge duration, a comparator outputs a logic one, and a logic zero after the discharge is completed.

Abstract: A method includes determining a plurality of first current values of a first current to be sunk by a tracking cell of a tracking circuit in response to a plurality of first voltage values of a first voltage applied to the tracking cell. Each first current value of the plurality of first current values thereby corresponds to a first voltage value of the plurality of first voltage values. A second current value of a second current is determined. The second current value corresponds to a second voltage value of a second voltage of a memory cell of a plurality of memory cells. A third voltage value is selected based on the second current value, a first current value of the plurality of first current values, and a first voltage value corresponding to the first current value.

Abstract: A method of operating a semiconductor memory device includes checking an erase-program cycling number, setting a target erase level to be maintained when the erase-program cycling number is less than a predetermined critical number, and setting the target erase level to be increased when the erase-program cycling number is greater than or equal to the predetermined critical number, and performing an erase operation so that threshold voltages of selected memory cells are less than the set target erase level.

Abstract: Apparatus and method for managing data in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a soft erasure is performed on a block of memory cells by toggling an erasure status value without otherwise affecting a written state of the cells in the block. The memory cells are subsequently overwritten with a set of data using a write polarity direction determined responsive to the toggled erasure status value.

Abstract: A semiconductor memory apparatus includes a first data storage region configured to be supplied with a driving voltage via a first voltage line, a second data storage region configured to be supplied with a driving voltage via a second voltage line and a switch configured to one of electrically couple the first voltage line with the second voltage line and decouple the first voltage line from the second voltage line in response to a switching control signal.

Abstract: Operating ReRAM memory is disclosed herein. The memory cells may be trained prior to initially programming them. The training may help to establish a percolation path. In some aspects, a transistor limits current of the memory cell when training and programming. A higher current limit is used during training, which conditions the memory cell for better programming. The non-memory may be operated in unipolar mode. The memory cells can store multiple bits per memory cell. A memory cell can be SET directly from its present state to one at least two data states away. A memory cell can be RESET directly to the state having the next highest resistance. Program conditions, such as pulse width and/or magnitude, may depend on the state to which the memory cell is being SET. A higher energy can be used for programming higher current states.

Abstract: Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular embodiments can include biased sections coupled between a high power supply voltage and a low power supply voltage, each having biasable transistors. One or more generation circuits can generate multiple bias voltages. A bias control section can couple one of the different bias voltages to screening regions of biasable transistors to provide a minimum speed and lowest current leakage for such a minimum speed.

Abstract: Methods and devices for charging unselected bit lines are disclosed. The rate at which inhibited (or unselected) bit lines are charged may depend on a program condition. The program condition may be completion of a program loop. As another example, the program condition may be a certain program state completing or nearly completing programming. As one example, the bit lines may be charged at a faster rate prior to the program condition occurring than after the program condition. As another example, the bit lines may be charged at a slower rate prior to the program condition than after the program condition. Charging the unselected bit lines at a slower rate may reduce current consumption. Charging the unselected bit lines at a faster rate may allow for faster programming.

Abstract: The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window.

Abstract: An operating method of a multi-bit-per-cell nonvolatile memory device, e.g., first and second variable resistance memory cells connected to one of word lines. The operating method may include receiving first to fourth data sequentially, providing a first program current to the first variable resistance memory cell to program the first and second data to the first variable resistance memory cell, and providing a second program current to the second variable resistance memory cell to program the third and fourth data to the second variable resistance memory cell after verifying whether an actual resistance of the programmed first variable resistance memory cell is within an intended resistance distribution.

Abstract: A memory device is provided comprising an array of memory cells. During a read operation, voltage on a read bit line will transition towards a second voltage level if a data value stored in that activated memory cell has a first value, and sense amplifier circuitry will then detect this situation. If that situation is not detected, the sense amplifier circuitry determines that the activated memory cell stores a second value. Bit line keeper circuitry is coupled to each read bit line and is responsive to an asserted keeper pulse signal to pull the voltage on each read bit line towards the first voltage level. Keeper pulse signal generation circuitry asserts the keeper pulse signal at a selected time. The selected time is such that the voltage on the associated read bit line will have transitioned to the trip voltage level before the keeper pulse signal is asserted.

Abstract: Memories and methods for providing and receiving non-data signals at a signal node are disclosed. One such memory includes first and second signal nodes, and first and second signal buffer. The first signal buffer is configured to be operative responsive to a first data strobe signal and further configured to be operative responsive to a non-data signal. The second signal buffer is configured to be operative responsive to a second data strobe signal. An example first data strobe signal is a read data strobe signal provided by the memory. In another example, the first data strobe signal is a write data strobe signal received by the memory. Examples of non-data signals include a data mask signal, data valid signal, error correction signal, as well as other signals.

Abstract: Writing data to a thermally sensitive memory device, including: receiving a physical layout of the thermally sensitive memory device; receiving the direction of airflow across the thermally sensitive memory device; selecting an address for writing data to the thermally sensitive memory device in dependence upon the physical layout of the thermally sensitive memory device and the direction of airflow across the thermally sensitive memory device; and writing data to the selected address of the thermally sensitive memory device.

Abstract: A low voltage ring oscillator circuit can have a frequency variation that depends on process variations of insulated gate field effect transistors (IGFETs) of a first conductivity type without substantially being affected by process variations to IGFETs of a second conductivity type. A ring oscillator stage may include an inverter including only IGFETs of the first conductivity type. The inverter may be coupled to a boot circuit that boosts the gate potential of a first IGFET of the first conductivity type with a timing such that IGFETs of the second conductivity type in the boot circuit do not affect the frequency variations of the ring oscillator circuit.

Abstract: A novel semiconductor memory device whose power consumption is low is provided. A source of a writing transistor WTr_n_m, a gate of a reading transistor RTr_n_m, and one electrode of a capacitor CS_n_m are connected to each other. A gate and a drain of the writing transistor WTr_n_m are connected to a writing word line WWL_n and a writing bit line WBL_m, respectively. The other electrode of the capacitor CS_n_m is connected to a reading word line RWL_n. A drain of the reading transistor RTr_n_m is connected to a reading bit line RBL_m. Here, the potential of the reading bit line RBL_m is input to an inverting amplifier circuit such as a flip-flop circuit FF_m to be inverted by the inverting amplifier circuit. This inverted potential is output to the writing bit line WBL_m.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array including cell strings coupled between bit lines and a common source line, each of the cell strings comprising a plurality of memory cells stacked above a substrate. The semiconductor memory device also includes a peripheral circuit configured to supply a negative voltage to one or more word lines coupled to the cell strings and supply a positive voltage to the common source line, wherein the peripheral circuit supplies the positive voltage and the negative voltage before a program operation is performed.

Abstract: A memory device comprises a nonvolatile memory device and a controller. The nonvolatile memory comprises a first memory area comprising single-bit memory cells and a second memory area comprising multi-bit memory cells. The controller is configured to receive a first unit of write data, determine a type of the first unit of write data, and based on the type, temporarily store the first unit of write data in the first memory area and subsequently migrate the temporarily stored first unit of write data to the second memory area or to directly store the first unit of write data in the second memory area, and is further configured to migrate a second unit of write data temporarily stored in the first memory area to the second memory area where the first unit of write data is directly stored in the second memory area.

Abstract: A system comprises a plurality of first memory macros and a first tracking circuit to be shared by the plurality of first memory macros. The first tracking circuit includes at least one of a first tracking circuit associated with a row of memory cells of a first memory macro of the plurality of first memory macros, a first tracking circuit associated with a column of memory cells of the first memory macro of the plurality of first memory macros, a first decoder tracking circuit associated with decoding circuitries of the first memory macro of the plurality of first memory macros, and a first input-output tracking circuit associated with input-output circuitries of the first memory macro of the plurality of first memory macros.

Abstract: Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide independent access to its associated SRAM bank.

Abstract: A memory device can include a plurality of memory elements programmable between different impedance states; and circuits configured to apply first electrical conditions to one group of memory elements and second electrical conditions, different from the first electrical conditions, to another group of memory elements to vary a speed of an access operation to the different groups of memory elements.

Abstract: A method includes initiating a read process for a memory array of an electronic memory device to make data available at an I/O buffer of the electronic memory device for access by a controller. A method includes signaling completion of a read process prior to completion of one or more stages of the read process at a memory array.

Abstract: A method includes coupling, by using a switching circuit, a first node to a bulk node of an input/output (IO) circuit of a memory circuit when the IO circuit operates in an active mode. The first node is configured to carry a first voltage level sufficient to cause a set of transistors of the IO circuit to have a first threshold voltage. A second node is coupled to the bulk node by using the switching circuit when the IO circuit operates in an inactive mode. The second node is configured to carry a second voltage level sufficient to cause the set of transistors of the IO circuit to have a second threshold voltage, and an absolute value of the second threshold voltage is greater than an absolute value of the first threshold voltage.

Abstract: A memory device comprising a plurality of memory tiles, each tile comprising a local common source line (CSL) plate, a plurality of bitlines and a plurality of wordlines, each coupled to a plurality of memory cells and a masking circuit, coupled to each of the memory tiles, for controlling whether to raise the local CSL plate and the plurality of bitlines based on the a global common source line.

Abstract: A static random access memory structure is provided. The static random access memory structure includes a storage region having a first storage node and a second storage node which is complementary to the first storage node. The static random access memory structure also includes a reading region having a first reading transfer gate and a second reading transfer gate, and a reading word line electrically connecting with the gate of the first reading transfer gate and the gate of the second reading transfer gate. Further, the static random access memory structure includes a writing region independent of the reading region having a first writing transfer gate and a second writing transfer gate and a writing word line electrically connecting with the gate of the first writing transfer gate and the gate of the second transfer gate.

Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.

Abstract: Methods and systems that extend the capability of fuse elements, anti-fuse elements, and combinations thereof to enable multi-time programmable memory elements are provided. Accordingly, significantly reduced area requirements and control circuitry complexity of memory elements is enabled. The provided methods and systems can be used in non-volatile memory storage, and are suitable for use in system on chip (SoC) products.

Abstract: Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in a memory array are enabled to be accessed at the same time. Additional embodiments are described.

Abstract: A memory module is provided. A plurality of DRAMs is mounted on a PCB. At least one DRAM has an operating parameter different from other DRAMs according to a position where the at least one DRAM is mounted on the PCB.

Abstract: A semiconductor memory device according to an embodiment of the present invention includes a memory block, a driving circuit performing a program operation on memory cells and a voltage detector generating a detection signal when an external power supply voltage is reduced to less than a reference voltage level. The driving circuit discharges a voltage applied to a drain selection line during the program operation in response to the detection signal.

Abstract: A method and system for storing and retrieving data using flash memory devices. One example system includes an apparatus within a flash memory configuration. The flash memory configuration includes a plurality of memory cells, where each memory cell has a charge storage capacity for use in implementing digital storage. The apparatus includes a processing arrangement configured to access each of the memory cells in a write operation and a read operation. The apparatus also includes an instruction set for instructing the processor to impose target charge levels for defining a plurality of data values for each of the memory cells. The target charge levels are programmably movable with respect to the charge storage capacity.

Abstract: A circuit includes a first plurality of memory cells coupled with a first data line and a first data transfer circuit coupled with the first data line and a second data line. In a first operation mode of the circuit, the first data line is left floating and is caused to have a first logical value by a current in at least one memory cell of the first plurality of memory cells. In a second operation mode of the circuit, the first data line is configured to reflect data stored in a memory cell of the plurality of memory cells, and the second data line is configured to reflect the data on the first data line through the first data transfer circuit.

Abstract: In some examples, a memory device is configured with non-volatile memory array(s) having one or more associated volatile memory arrays. The memory device may include a non-destructive write mode configured to prevent access to the non-volatile memory array(s) during an initiation or calibration sequence performed by the memory device or an electronic device associated with the memory device to calibrate read and write access timing associated with the memory device.

Abstract: A memory operate in a normal mode of operation or a testing mode of operation. In the testing mode of operation, the memory can measure various benchmarks of performance, such as read speed. The memory can perform an asynchronous read operation to read a word of electronic data that corresponds to an address or a page read operation in which multiple asynchronous read operations are performed to read multiple words of electronic data, also referred to as a page of electronic data, that correspond to multiple addresses. The memory can measure a time required, referred to as read speed, to read the word of electronic data or the multiple words of electronic data from the memory.

Abstract: A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a charge to be stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the write line, the charge having a value determined by a data value having at least three states.

Abstract: A memory cell system/method incorporating reduced transistor counts and/or improved design-for-manufacturability (DFM) is disclosed. The system/method incorporates cross-coupled feedthru (3410)/feedback (3420) amplifiers to implement memory cell state memory, wherein the feedback amplifier incorporates a multi-state output drive capability (3423) allowing the memory cell to be read/written using only one access device (3430) connected to the output (3412) of the feedthru (3410) amplifier. The multi-state output drive capability (3423) modulates the feedback amplifier (3420) drive strength to enable reading/writing of the feedthru amplifier (3410) state with greatly reduced memory cell input fan-in requirements. The invention anticipates replacement of traditional DP/8T/6T/4T memory cell structures with corresponding 6T/6T/5T/3T memory cell configurations, resulting in a 16%-25% transistor reduction depending on memory array application context.

Abstract: A semiconductor device is disclosed in which a plurality of memory cores are provided on a semiconductor chip. Each of the memory cores comprises: first and second circuit regions and a first and second through electrode groups. a first power supply is supplied in the first circuit region in which a data bus for parallel data is driven, and a second power supply separated from the first power supply is supplied in the second circuit region in which the parallel data and serial data are bidirectionally converted. The first through electrode group includes through electrodes supplying the first power supply to the first circuit region, and the second through electrode group includes through electrodes supplying the second power supply to the second circuit region.

Abstract: A circuit includes a Static Random Access Memory (SRAM) array. An SRAM cell is in the SRAM array and includes a p-well region, a first and a second n-well region on opposite sides of the p-well region, and a first and a second pass-gate FinFET. The first pass-gate FinFET and the second pass-gate FinFET are p-type FinFETs. A CVss line is over the p-well region, wherein the CVss line is parallel to an interface between the p-well region and the first n-well region. A bit-line and a bit-line bar are on opposite sides of the CVss line. A CVdd line crosses over the SRAM cell. A CVss control circuit is connected to the CVss line. The CVss control circuit is configured to provide a first CVss voltage and a second CVss voltage to the CVss line, with the first and the second CVss voltage being different from each other.