Abstract: A memory cell includes a true data node, a true pullup transistor, a complement data node and a complement pullup transistor. A true switching circuit selectively supplies a first or second supply voltage to a source of the true pullup transistor. A true bias switching circuit selectively supplies a third or fourth supply voltage to a body of the true pullup transistor. When writing a logic high data value to the true data storage node, a control circuit causes the true switching circuit to supply the second supply voltage and the true bias switching circuit to supply the third supply voltage. The second supply voltage is higher than the first supply voltage, and the fourth supply voltage is higher than the third supply voltage. A similar operation is performed with respect to the complement pullup transistor when writing a logic high data value to the complement data storage node.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: A method of performing cascaded flashcopy (FC) including starting a flashcopy map when a target disk is already a source of an active FC map. A computer storage system includes a configuration that allows a flashcopy (FC) map to be started when a target disk is already the source of an active FC map.

Abstract: A reading method of a semiconductor memory device having a multi-level memory cell includes the steps of: reading flag data indicating whether the most significant bit (MSB) of data programmed in the multi-level memory cell is programmed or not; storing the read flag data; reading the least significant bit (LSB) of the data programmed in the multi-level memory cell, based on the read flag data; and reading the MSB of the data programmed in the multi-level memory cell based on the stored flag data.

Abstract: In a method of reading a nonvolatile memory device, the method comprising, a reading operation of reading data of a selected memory cell; and a read retry operation of performing one or more read operations by changing a non-selection read voltage applied to non-selected memory cells until the read operation succeeds, when it is detected that an error has occurred in the operation of reading data.

Abstract: A non-volatile memory device that includes N planes of non-volatile memory cells (where N is an integer greater than 1). Each plane of non-volatile memory cells includes a plurality of memory cells configured in rows and columns. Each of the N planes includes gate lines that extend across the rows of the memory cells therein but do not extend to others of the N planes of non-volatile memory cells. A controller is configured to divide each of a plurality of words of data into N fractional-words, and program each of the N fractional-words of each word of data into a different one of the N planes of non-volatile memory cells. The controller uses a programming current and a program time period for the programming, and can be configured to vary the programming current by a factor and inversely vary the program time period by the factor.

Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.

Abstract: A state set module arranges states of a memory cell in a first and a second sequence in a first and a second state set, respectively. The memory cell stores first and second bits when programmed to a state. When the states in the first and second state sets are accessed respectively in the first and the second sequence, the first and second bits of the states in the first and second state sets exhibit different number of logical transitions. A write module receives first and second sets of bits to be written as the first and second bits in a plurality of memory cells, and selects states from the first and second state sets in an alternating pattern to write the first and second sets of bits as the first and second bits in the plurality of memory cells.

Abstract: A semiconductor system includes a semiconductor memory device configured to, during a test mode, store received data in a memory cell in response to a write command, read the stored data as information data in response to a read command, and internally store the information data, in response to the read command, in synchronization with a pulse generated when a level of the information data changes.

Abstract: Providing for a non-volatile memory architecture having write and overwrite capabilities providing low write amplification to a storage system is described herein. By way of example, a memory array is disclosed comprising blocks and sub-blocks of two-terminal memory cells. The two-terminal memory cells can be directly overwritten in some embodiments, facilitating a write amplification value as low as one. Furthermore, the memory array can have an input-output multiplexer configuration, reducing sneak path currents of the memory architecture during memory operations.

Abstract: Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the voltage on the selected cell is read to determine any change in voltage caused by systemic offsets such as, for example, floating gate-to-floating gate coupling. These changes are averaged and stored in a table as an offset for use in adjusting a programming voltage or a read voltage in a particular area of memory represented by the offset. Self calibration method for temperature is determined by writing cells at different temperatures and reading at different temperatures to generate temperature offset tables for the write path and read path. These offset tables are used to adjust for systematic temperature related offsets during programming and during read.

Abstract: An example embodiment is a circuit for determining a binary value of a memory cell. The circuit includes shunt capacitors having different capacitances to selectively couple with the memory cell, and a controller configured to iteratively charge the shunt capacitors to a first voltage until a selected shunt capacitor causes the first voltage to decay through the memory cell to a first reference voltage within a predetermined time range, determine a binary value of the most significant bits of the memory cell based on the selected shunt capacitor, charge the selected shunt capacitor to a second voltage after determining the binary value of the most significant bits of the memory cell, and determine a binary value of the least significant bits of the memory cell based on a decay of the second voltage at the selected shunt capacitor through the memory cell.

Abstract: Disclosed is a read timing generation circuit, capable of reducing dynamic power consumption. After a multi-bit address Add1, Add2, . . . , and AddN passes through an address change monitoring unit (100), a response pulse signal corresponding the address is generated. After the response pulse signal passes through an address trigger determination unit (200), a single trigger determination signal ATDPRE is generated. The single trigger determination signal ATDPRE passes through an ATD timing generation unit (300) and a post-timing generation unit (1000), thereby forming a read timing generation circuit in a serial link and generating corresponding read timing. Compared with the conventional read timing generation circuit in which each bit of an address signal corresponds to a stage of structures to execute the trigger, ATD control timing output, and ATD determination process separately, the present invention greatly reduces the total dynamic power consumption of the circuit.

Abstract: A memory module can include a data buffer having a data bus interface and a dynamic random access memory (DRAM) coupled to the data buffer. The memory module may also include a switch connected in parallel with the data buffer, wherein the switch can selectively bypass the data buffer. In one example, the memory module also includes a registered buffer having an address bus interface, where the switch may selectively bypass the data buffer based on a program signal obtained from an address bus via the address bus interface.

Abstract: In the disclosed technology, the device identification code of a memory integrated circuit is changeable. In some cases, multiple device identification codes are stored on the memory integrated circuit, and multiple device identification code selection data are stored on the memory integrated circuit. A device identification code register can store a selected device identification code.

Abstract: A memory circuit includes a plurality of divided memory cell blocks, a write circuit and a read circuit which connect via a pair of bit lines to each of the divided memory cell blocks. The output of write data to one of the bit line of the write circuit is made to be performed by one system. It is possible to achieve an increase of speed by bit lien division while reducing increase in the memory circuit area accompanying the bit line division.

Abstract: This invention proposes a multi-bit resistive-switching memory cell and array thereof. Multiple conduction paths are formed on each memory cell and independent of each other, and each conduction path can be in a high-resistance or low-resistance state, so as to form a multi-bit resistive-switching memory cell. A memory cell array can be formed by arranging a plurality of multi-bit resistive-switching memory cells, and the memory cell array provides a simple, high density, high performance and cost-efficient proposal.

Abstract: An RRAM at an STI region is disclosed with a vertical BJT selector. Embodiments include defining an STI region in a substrate, implanting dopants in the substrate to form a well of a first polarity around and below an STI region bottom portion, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate, forming a hardmask on the active areas, removing an STI region top portion to form a cavity, forming an RRAM liner on cavity side and bottom surfaces, forming a top electrode in the cavity, removing a portion of the hardmask to form spacers on opposite sides of the cavity, and implanting a dopant of the second polarity in a portion of each active area remote from the cavity.

Abstract: A storage unit is provided with a plurality of sub storage units configured to include a plurality of hard disk drives, an enclosure, a printed wiring board, a power supply device, and a cable holder. The sub storage units each operate separately. The enclosure is provided in the array of the hard disk drives so that the distance can be shorter between the enclosure and each of the hard disk drives. With the provision of the cable holder, communications cables can be both brought closer to the printed wiring board. With such a configuration, the coupling point among the communications cables and the printed wiring board, and the enclosure can be favorably reduced. The resulting storage control apparatus can be mounted with a larger number of storage devices, thereby being able to maintain good signal quality.

Abstract: Techniques and circuitry are disclosed for implementing non-volatile storage that exploit bias temperature instability (BTI) effects of high-k/metal-gate n-type or p-type metal oxide semiconductor (NMOS or PMOS) transistors. A programmed bitcell of, for example, a memory or programmable logic circuit exhibits a threshold voltage shift resulting from an applied programming bias used to program bitcells. In some cases, applying a first programming bias causes the device to have a first state, and applying a second programming bias causes the device to have a second state that is different than the first state. Programmed bitcells can be erased by applying an opposite polarity stress, and re-programmed through multiple cycles. The bitcell configuration can be used in conjunction with column/row select circuitry and/or readout circuitry, in accordance with some embodiments.

Abstract: A memory device includes a plurality of memory cells and programming circuitry configured to select a group of memory cells, receive a first data word and program memory cells of the selected group based on the data word. The memory device includes a program circuit configured to receive at least one second data word, and, for each second data word, send a program current in parallel to discriminated memory cells based on the corresponding second data word during a corresponding program phase. The memory device further includes an optimization circuit configured to generate the at least one second data word from the first data word. The number of discriminated memory cells of the second data word is maximized compatibly with a maximum predetermined limit of the total program current provided by the program circuit.

Abstract: Decoding and decoder circuits in memory devices are disclosed. Array lines are biased or floated as memory device operations are performed in the memory device. In at least one embodiment, a decoder circuit includes complementary devices to bias array lines or float array lines in a memory device while particular memory device operations are performed.

Abstract: A memory includes a first cell array configured to include a plurality of first memory cells connected to a plurality of word lines, a second cell array configured to include a plurality of second memory cells connected to the plurality of word lines, wherein a group of the plurality of second memory cells which are connected to a corresponding word line stores the number of activations for the corresponding word line, and an activation number update unit configured to update a value stored in the corresponding group of the plurality of second memory cells connected to the activated word line of the plurality of word lines.

Abstract: An embodiment of the invention discloses an electronic device for reducing degradation in NMOS circuits in a tracking circuit. A first multiplexer selects, based on N bits from a row address in a memory array, which tracking circuit from a group of 2N tracking circuits will be used to provide a signal develop time for a memory cell in the memory array using a dummy word line signal. A second multiplexer selects, based on the N bits from the row address for a memory array, which output from the tracking circuits is used to enable the sense amp enable signal.

Abstract: A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in series with a resistance. The transistor includes a gate dielectric that is switchable between a plurality of different resistance values. The threshold voltage of the transistor changes according to the resistance value of the gate dielectric. Memory states of the memory cells can thus be associated with respective resistance values of the dielectric layer of the transistor.

Abstract: A sacrificial memory bank is added to a block of regular banks in a memory to reduce dynamic power consumption of the memory. The sacrificial bank is accessed by a set of bit lines that is substantially shorter than corresponding bit lines extending through all of the regular memory banks. Memory read and write operations, which are addressed to one of the regular banks, are deliberately redirected to the sacrificial bank having the short bit lines. Tracking circuitry identifies the regular bank that was addressed for each location in the sacrificial bank. Data is moved from the sacrificial bank to a regular bank only when a new write operation does not match the bank of the previous write operation. Dynamic power is reduced because locality of reference causes access to the sacrificial bank without having to access a regular bank for most memory read and write operations.

Abstract: According to one embodiment, an output driver which outputs an output signal to a transmission line, the output driver includes a pre-driver and a main driver. The pre-driver changes the duty ratio of a first drive signal and the duty ratio of a second drive signal to a plurality of patterns in accordance with a control signal. The main driver connects in series a first driver driven by the first drive signal and a second driver driven by the second drive signal. The main driver outputs the output signal to the transmission line from a connection node of the first and second drivers.

Abstract: A circuit for programming a fuse is disclosed. The circuit includes a voltage supply terminal (Vf) and a semiconductor controlled rectifier (222, 224). The fuse is coupled between the voltage supply terminal and the semiconductor controlled rectifier. A switching circuit (200, 202, 208, 210) is coupled to the semiconductor controlled rectifier.

Abstract: A memory device can include a plurality of memory elements programmable between different impedance states; and circuits configured to apply first electrical conditions to one group of memory elements and second electrical conditions, different from the first electrical conditions, to another group of memory elements to vary a speed of an access operation to the different groups of memory elements.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array including cell strings coupled between bit lines and a common source line, each of the cell strings comprising a plurality of memory cells stacked above a substrate. The semiconductor memory device also includes a peripheral circuit configured to supply a negative voltage to one or more word lines coupled to the cell strings and supply a positive voltage to the common source line, wherein the peripheral circuit supplies the positive voltage and the negative voltage before a program operation is performed.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes memory cells having first to fourth middle states corresponding to different threshold voltage distributions. The semiconductor memory device also includes a peripheral circuit configured to perform a first program operation to program memory cells having the third and the fourth middle states to have four upper states and perform a second program operation to program memory cells having the first and the second middle states to have another four upper states.

Abstract: This technology relates to nonvolatile memory devices and methods of manufacturing the same. A nonvolatile memory device can include a memory cell array configured to include a plurality of strings, a page buffer unit connected to the plurality of strings, respectively, and configured to sense data, and a switching unit disposed between the memory cell array and the page buffer unit and configured to comprise a variable resistor.

Abstract: A method including providing a plurality of random access memories having at least a first region, a second region and a third region; storing protected data on the first region on at least two of the random access memories, where the protected data is stored distributed among the at least two random access memories of the first region; storing parity information for the protected data on the second region on at least a third one of the random access memories; and storing unprotected data on the third region.

Abstract: A memory cell array includes memory cells disposed at intersections of first lines and second lines, and each having a rectifying element and a variable resistance element connected in series. A control circuit, when performing an operation to change retained data, applies a first voltage to a selected first line and applies a second voltage to a selected second line; furthermore, applies a third voltage to a non-selected first line; and, moreover, applies a fourth voltage larger than the third voltage to a non-selected second line. An absolute value of a difference between the third voltage and the fourth voltage is set smaller than an absolute value of a difference between the first voltage and the second voltage by an amount of an offset voltage. A value of the offset voltage increases as the absolute value of the difference between the first and second voltages increases.

Abstract: A power supply control circuit which can cut off a power supply independently is provided for each column in a memory cell array. The power supply control circuit is controlled by a circuit which is provided for each column and determines whether or not it is necessary to hold information, whereby a power supply for a memory cell which does not need to hold information is cut off.

Abstract: Structures and methods for controlling operation of a programmable impedance element are disclosed herein. In one embodiment, a method of controlling a programmable impedance element can include: (i) receiving a program or erase command to be executed on the programmable impedance element; (ii) selecting an operation algorithm for executing the command, where the operation algorithm is selected from among a plurality of operation algorithms by decoding at least two bits stored in a register; (iii) determining, using the register, a plurality of option variables for the selected operation algorithm, where the option variables are used to set conditions for one or more of a plurality of program and erase operations of the selected operation algorithm; and (iv) executing the command on the programmable impedance element by performing the one or more of the plurality of program and erase operations of the selected operation algorithm.

Abstract: Embodiments relate to a method for representing data in a graphene-based memory device. The method includes applying a first voltage to a back gate of a graphene-based memory device and a second voltage to a first graphene layer of the graphene-based memory device. The graphene-based memory device includes the first graphene layer and a second graphene layer and a first insulation layer located between the first and second graphene layers. The first insulation layer has an opening between the first and second graphene layers. The back gate is located on an opposite side of the second graphene layer from the first insulation layer. The first graphene layer is configured to bend into the opening of the first insulation layer to contact the second graphene layer based on a first electrostatic force generated by the applying the first voltage to the back gate.

Abstract: A semiconductor apparatus includes: a first bank group comprising a plurality of first banks; a second bank group comprising a plurality of second banks arranged adjacent to the first bank group; a write operation controller arranged between the first and second bank groups so as to be adjacent to the first and second bank groups, and configured to control write operations of the first and second bank groups; and a read operation controller arranged adjacent to any one of the first and second bank groups and configured to control read operations of the first and second bank groups.

Abstract: A memory module that includes a buffer and a plurality of synchronous memory devices. The memory module also includes bidirectional bus lines, and each of the synchronous memory devices has bidirectional data terminals. The buffer is configured to regenerate signals received on the bus lines for receipt by the synchronous memory devices, and to regenerate signals received from any one of the synchronous memory devices for receipt by the bus lines. The memory module may further include command lines and a clock line for providing commands and a clock signal to the synchronous memory devices via a command buffer. The combined data bus width of the memory module may be greater than the data bus width of any single one of synchronous memory device, and the total address space provided by the memory module may be larger than the data space for any single synchronous memory device.

Abstract: A nonvolatile semiconductor memory can reduce variations in an amount of current during data writing operation. This allows for the writing of data to memory cells with high precision. The nonvolatile semiconductor memory includes a plurality of memory cells, word lines connected to the memory cells, and bit lines connected to each of the memory cells. At least two of the bit lines are selected, and a current is simultaneously supplied from a power supply line to those memory cells which are connected to the selected bit lines in order to write data thereto. The nonvolatile semiconductor memory also includes charge amount measurement units for measuring respective amounts of charge stored in the memory cells. The nonvolatile semiconductor memory also includes current path switching circuits connected to the respective bit lines.

Abstract: A memory system that includes a memory device and a memory bank. During operation, the memory device receives a request to concurrently access a data word at a first row in a first storage region of the memory bank and error information associated with the data at a second row in a second storage region of the memory bank. The memory request includes a first row address identifying the first row and a second row address identifying the second row. Next, the memory device routes the first row address and the second row address to a first row decoder and a second row decoder in the memory bank, respectively. Finally, the memory device uses the first row decoder to decode the first row address to access the first row and concurrently uses the second row decoder to decode the second row address to access the second row.

Abstract: A semiconductor memory device includes a memory block configured to store a data inputted/outputted through a data transfer line, a data output block configured to output the data loaded on the data transfer line in response to a source clock, wherein the data output block is controlled to be coupled with the data transfer line in response to a write operation signal, a write operation signal generation block configured to generate the write operation signal in response to an operation selection signal and a reference clock lagging behind the source clock by a set time, and a data input block configured to load the data on the data transfer line in response to the write operation signal.

Abstract: In an embodiment, an integrated circuit includes a memory and a control circuit configured to cause an inversion of at least a portion of the data stored in the memory to more evenly balance the amount of time that a given memory cell in the memory stores a binary one or a binary zero. In some implementations, the inversion may be controlled for the memory as a whole via a global indication. In other implementations, data may be inverted on a row-by-row or column-by-column basis. In other embodiments, the global indication may be changed at each boot of a device including the integrated circuit.

Abstract: In a storage device including a plurality of storage regions, in order to synchronize input/output control of data into/from the storage region, a writing sequence or a reading sequence of the data into or from the storage region is stored, one of the storage regions to be accessed is selected in accordance with the stored sequence, and the synchronization control of input/output processing into/from an intermediate buffer is carried out, which allows an intermediate buffer control mechanism to be applied to various intermediate buffers.

Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.

Abstract: A circuit includes a tracking write circuit and a write circuit. Various write signals of the write circuit are generated based on tracking signals of the tracking write circuit. The write signals are used in a write operation of a memory cell.

Abstract: A method for writing a memory cell in a specific write cycle is provided. The method includes the following steps: providing a first signal having a first transition edge in the specific write cycle; providing a second signal having a second transition edge in the specific write cycle, wherein the second transition edge lags behind the first transition edge; providing a first voltage level to the memory cell; and lowering the first voltage level to a second voltage level in the specific write cycle for writing the memory cell in response to the second transition edge. A memory device is also provided.

Abstract: A storage subsystem implements a background process for selecting voltage reference values to use for reading data from a non-volatile memory array, such as an array of multi-level cell (MLC) flash memory. The process involves performing background read operations using specific sets of voltage reference values while monitoring the resulting bit error counts. The selected voltage reference values for specific pages or other blocks of the array are stored in a table. Read operations requested by a host system are executed using the corresponding voltage reference values specified by the table.

Abstract: Disclosed is a semiconductor device having a memory cell which comprises a transistor having a control gate and a storage gate. The storage gate comprises an oxide semiconductor and is able to be a conductor and an insulator depending on the potential of the storage gate and the potential of the control gate. Data is written by setting the potential of the control gate to allow the storage gate to be a conductor, supplying a potential of data to be stored to the storage gate, and setting the potential of the control gate to allow the storage gate to be an insulator. Data is read by supplying a potential for reading to a read signal line connected to one of a source and a drain of the transistor and detecting the change in potential of a bit line connected to the other of the source and the drain.

Abstract: A memory circuit includes a transistor having a channel in an oxide semiconductor layer, a capacitor, a first arithmetic circuit, a second arithmetic circuit, a third arithmetic circuit, and a switch. An output terminal of the first arithmetic circuit is electrically connected to an input terminal of the second arithmetic circuit. The input terminal of the second arithmetic circuit is electrically connected to an output terminal of the third arithmetic circuit via the switch. An output terminal of the second arithmetic circuit is electrically connected to an input terminal of the first arithmetic circuit. An input terminal of the first arithmetic circuit is electrically connected to one of a source and a drain of the transistor. The other of the source and the drain of the transistor is electrically connected to one of a pair of electrodes of the capacitor and to an input terminal of the third arithmetic circuit.