Abstract: Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory devices incorporating such strings and methods for accessing and forming such strings are provided. For example, non-volatile memory devices are disclosed that utilize vertical structure NAND strings of serially-connected non-volatile memory cells. One such string including two or more serially-connected non-volatile memory cells where each end of the string shares a string select gate with the other end of the string is disclosed.

Abstract: Example reference current distribution circuitry described herein include current mirrors having resistive elements of varying sizes between gate nodes of sense amplifier transistors along a voltage, distribution line. Examples of counter coupling capacitances which may be coupled to the gate nodes of sense amplifier transistors are also described.

Abstract: Systems and methods are disclosed herein, such as those that operate to control a set of delays associated with one or more data clocks to clock a set of data bits into one or more transmit registers, one or more data strobes to transfer the set of data bits to at least one receive register, and/or a set of memory array timing signals to access a memory array on a die associated with a stacked-die memory vault. Systems and methods herein also include those that perform data eye training operations and/or memory array timing training operations associated with the stacked-die memory vault.

Abstract: A method and a system are provided for performing address-based memory access assist. An address is received for a memory access and a determination is made, based on the address, that access assist is enabled for at least one storage cell corresponding to the address. The access assist is applied to the at least one storage cell to perform the memory access.

Abstract: An apparatus may comprise a memory cell configured to operate according to a voltage mode, a voltage controller coupled with the memory cell, wherein the voltage controller is configured to change the voltage mode of the memory cell between a low voltage mode and a high voltage mode, and a memory controller module coupled with the memory cell, wherein the memory controller is configured to invert a logic state stored in the memory cell based on the voltage mode.

Abstract: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.

Abstract: Provided is a semiconductor device including: a memory cell having a variable resistance device; and a control unit that controls a voltage applied to the memory cell, wherein the variable resistance device includes a lower electrode contains a first metal material, an upper electrode containing a second metal material, and an insulating film containing oxygen, the first metal material has a normalized oxide formation energy higher than that of the second metal material, and the control unit applies a positive voltage to the upper electrode at the time of an operation of increasing a resistance value of the insulating film and an operation of decreasing the resistance value thereof, and applies a positive voltage to the lower electrode at the time of an operation of reading out the resistance value of the insulating film.

Abstract: Embodiments disclosed herein may relate to programming a memory cell with a programming pulse that includes a quenching period. The quenching period includes an initial portion and a subsequent portion, with the subsequent portion different than the initial portion. During the initial portion, the amplitude of the programming pulse may be reduced to a first target amplitude level, and during the subsequent portion, the amplitude of the programming pulse may be further reduced to a second target amplitude level.

Abstract: A semiconductor memory device includes a memory cell array layer which includes a first wiring line, a memory cell stacked on the first wiring line, and a second wiring line formed on the memory cell so as to intersect the first wiring line, wherein a step is formed in the first wiring line so that the height of an upper surface of the first wiring line in the memory cell array region where the memory cell array is formed is higher than the height in a peripheral region around the memory cell array region.

Abstract: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.

Abstract: A high density, low voltage, and low-power one time programmable (OTP) memory is based on core cells with a one transistor design. A CLEAN pulse is directed to a single shunt device at the output of the column decoder so spurious charges that may have been stored in the floating nodes can be cleaned up. Such arrangement also allows for the simultaneous initialization of bit lines, data lines, and sensing lines to zero. Core area layout size is substantially reduced, and operational power requirements are exceeding low making these particularly suitable in HF and UHF RFID applications.

Abstract: A device includes a semiconductor substrate, a first penetrating electrode penetrating through the semiconductor substrate, a first test pad, and a first tri-state buffer coupled between the first penetrating electrode and the first test pad. The first tri-state buffer receives a buffer control signal at a control terminal thereof. The device further includes a buffer control circuit supplying the buffer control signal to the first tri-state buffer.

Abstract: A system and method to enable reading from non-volatile memory (NVM) devices is described. In one embodiment, the method includes setting a sensing parameter used to read data stored in a NVM device, reading from pluralities of locations of the NVM device with the sensing parameter set at the first value. The locations of the NVM device store an identical value. The method also includes verifying whether the identical value is read correctly from the locations of the NVM device. The method also includes setting the sensing parameter to a second value when the identical value is not read correctly with the sensing parameter set at the first value. The method further includes determining a third value for the sensing parameter from the identical value and setting the sensing parameter to the third value when the identical value is read correctly.

Abstract: In one aspect, the invention concerns a memory system that compensates for power level variations in sense amplifiers for multilevel memory. For example, a compensation circuit can be employed to compensate for current or voltage variations in the power supplied to multilevel memory sense amplifiers. As another example, compensation can be accomplished by application of a bias voltage to the power supply. Another example is a sense amplifier configured with improved input common mode voltage range. Such sense amplifiers can be two-pair and three-pair sense amplifiers. Further examples of the invention include more simplified sense amplifier configurations, and sense amplifiers having reduced leakage current.

Abstract: A source-synchronous capture unit on a receiving circuit includes a first first-in-first-out (FIFO) unit operable to synchronize a write enable signal to generate a synchronized write enable signal that is synchronized with a first free running clock associated with a memory external to the receiving circuit. The write enable sign is generated in response to a read operation by the receiving circuit. The source-synchronous capture unit also includes a second FIFO unit operable to store data from the memory in response to the first free running clock and the synchronized write enable signal, and to output the data in response to a second free running clock associated with the receiving circuit and a read enable signal.

Abstract: The semiconductor memory device includes a memory cell, a pair of bit lines and a cell power line connected to the memory cell, a first switch connected to the bit lines and a power voltage line, a second switch connected to the cell power line and a write assist cell power line, and a write control circuit configured to control the bit lines, the first switch and the second switch, wherein the write control circuit applies a first voltage of a high level to one bit line and a second voltage of a low level to the other bit line, connects one bit line to the power voltage line and disconnects the other bit line from the power voltage line by the first switch, and then connects the cell power line to the write assist cell power line lower which is than the first voltage by the second switch.

Abstract: Memory sense amplifier voltage modulation. An embodiment of a an apparatus includes a memory including a sense amplifier; a first node for an high voltage rail for the sense amplifier and a second node for a low voltage rail for the sense amplifier; one or more elements to provide a first voltage to the first node and a second voltage to the second node; and a voltage control engine to control the one or more elements, where the voltage control engine is to independently set a value of the first voltage and a value of the second voltage over time.

Abstract: A memory is disclosed that can operate in a normal mode of operation or a testing mode of operation. In the testing mode of operation, the memory can measure various benchmarks of performance, such as read speed. The memory can perform an asynchronous read operation to read a word of electronic data that corresponds to an address or a page read operation in which multiple asynchronous read operations are performed to read multiple words of electronic data, also referred to as a page of electronic data, that correspond to multiple addresses. The memory can measure a time required, referred to as read speed, to read the word of electronic data or the multiple words of electronic data from the memory.

Abstract: A memory system (1) comprising a control logic (2) adapted to receive a number n of write requests (WRs) from input ports and to receive a read request (RR) from an output port within a clock cycle of a clock signal (CLK) applied to said memory system (1), wherein n is a natural number; and n+1 memory banks (4) of a shared memory (3) adapted to store data, wherein the control logic (2) is adapted to control a memory bank occupancy level MBOL of each memory bank (4) such that the differences between memory bank occupancy levels MBOLs of the memory banks (4) are minimized

Abstract: Systems and methods for auto-calibrating a storage memory controller are disclosed. In some embodiments, the systems and methods may be realized as a method for auto-calibrating a storage memory controller including instructing a controllable delay circuit to delay a read strobe signal at one of a plurality of delay settings, receiving data captured at a data latch using the delayed read strobe signal, selecting an adjustment factor from the plurality of delay settings using a multi-scale approach, based on an accuracy of the data captured at the data latch, and instructing the controllable delay circuit to delay the read strobe signal by the adjustment factor.

Abstract: A semiconductor device comprises a first region and a second region. The first region includes a plurality of memory cells each of which holds respective data and a plurality of sense amplifiers that respectively amplify the data in the plurality of memory cells, based on a first voltage. The second region is provided along one side of the first region and includes a first power supply generation circuit that generates the first voltage, based on a second voltage. The second voltage being supplied to the first power supply circuit by a first power supply interconnect extends on the first region in a first direction parallel to the one side of the first region.

Abstract: A system comprises a plurality of first memory macros and a first tracking circuit to be shared by the plurality of first memory macros. The first tracking circuit includes at least one of a first tracking circuit associated with a row of memory cells of a first memory macro of the plurality of first memory macros, a first tracking circuit associated with a column of memory cells of the first memory macro of the plurality of first memory macros, a first decoder tracking circuit associated with decoding circuitries of the first memory macro of the plurality of first memory macros, and a first input-output tracking circuit associated with input-output circuitries of the first memory macro of the plurality of first memory macros.

Abstract: Apparatuses and methods involving accessing memory cells are described. In one such method, chunks of memory cells in a memory array are enabled to be accessed and then one or more of the chunks are disabled from being accessed. In one such apparatus, an array includes chunks of memory cells and a chunk selector circuit coupled to each chunk to enable the memory cells in the respective chunk to be accessed. Additional embodiments are described.

Abstract: An object is to provide a semiconductor device having a novel structure. A first wiring; a second wiring; a third wiring, a fourth wiring; a first transistor including a first gate electrode, a first source electrode, and a first drain electrode; a second transistor including a second gate electrode, a second source electrode, and a second drain electrode are included. The first transistor is provided over a substrate including a semiconductor material and a second transistor includes an oxide semiconductor layer.

Abstract: In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.

Abstract: Apparatuses and methods including a plurality of memory units are disclosed. An example apparatus includes a plurality of memory units. Each of the plurality of memory units include a master/slave identification (ID) node coupled to a first voltage source node via a resistive element. Each of the plurality of memory units further include a master/slave ID circuit configured to determine whether a memory unit is a master memory unit or a slave memory unit based on a voltage level detected at the master/slave ID node. The master/slave ID node of each of the plurality of memory units other than a first memory unit is further coupled to a respective second voltage source node via a through-substrate via (TSV) of a respective adjacent memory unit of the plurality of memory units.

Abstract: Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell, and accessing the cell.

Abstract: A non-volatile memory built-in self-trim mechanism is provided by which product reliability can be improved by minimizing drift of reference current used for accessing the non-volatile memory and for performing initial trimming of the reference current. Embodiments perform these tasks by using an analog-to-digital converter to provide a digital representation of the reference current (Iref) and then comparing that digital representation to a stored target range value for Iref and then adjusting a source of Iref accordingly. For a reference current generated by a NVM reference bitcell, program or erase pulses are applied to the reference cell as part of the trimming procedure. For a reference current generated by a bandgap-based circuit, the comparison results can be used to adjust the reference current circuit. In addition, environmental factors, such as temperature, can be used to adjust the measured value for the reference current or the target range value.

Abstract: In the disclosed technology, the device identification code of a memory integrated circuit is changeable. In some cases, multiple device identification codes are stored on the memory integrated circuit, and multiple device identification code selection data are stored on the memory integrated circuit. A device identification code register can store a selected device identification code.

Abstract: A memory array includes a plurality of columns of memory cells and each column of memory cells of the memory array is coupled to a local voltage source, a bit line, and a bit line bar. Provide a working voltage to pre-charge the bit line and the bit line bar of the column of memory cells when a memory cell of the column of memory cells is selected to be read, and meanwhile use local voltage sources coupled to remaining columns of memory cells of the memory array to provide high voltages lower than the working voltage to pre-charge bit lines and bit line bars of the remaining columns of memory cells.

Abstract: A system, method and computer program product for operating a three-dimensional memory array. An example array includes access transistors with first, second and gate terminals. Bit lines are coupled to the first terminals, word lines coupled to the gate terminals, and vertical lines are coupled to the second terminals. The bit, word, and vertical lines are perpendicular to one another. Memory cells are positioned along the vertical lines, including a bidirectional access device coupled in series with a memory element. The memory element is programmable to first and second states by application of first and second write voltages, opposite in polarity to one another. The array includes conductive plates parallel to the word and bit lines, and perpendicular to the vertical lines. The conductive plates are coupled to memory cells of the same height and separated by insulating layers.

Abstract: A memory device includes a memory array, an array gap, a voltage provider, and a voltage divider. The voltage provider is disposed in the array gap and coupled to a column of memory cells of the memory array for providing a first voltage to the column of memory cells when a memory cell of the column is selected at a write cycle. The voltage provider is coupled to the voltage provider and the column of memory cells for providing a second voltage lower than the first voltage to the column of memory cells when the memory of the column is half selected at the write cycle.

Abstract: A method includes selecting a word line for programming in an array of analog memory cells that are arranged in rows associated with respective word lines and columns associated with respective bit lines. Word-line voltages, which program the memory cells in the selected word line, are applied to the respective word lines. Bit-line voltages, which cause one or more additional memory cells outside the selected word line to be programmed as a result of programming the selected word line, are applied to the respective bit lines. Using the applied word-line and bit-line voltages, data is stored in the memory cells in the selected word line and the additional memory cells are simultaneously programmed.

Abstract: A method includes, in an array of analog memory cells that are arranged in rows associated with respective word lines, reading a first group of the memory cells in a selected word line, including one or more memory cells that store a status of at least one word line in the array other than the selected word line. A readout configuration for a second group of the memory cells is set responsively to the read status. The second group of the memory cells is read using the readout configuration.

Abstract: A method includes causing, by a first circuit, a first signal transition at a first node based on a clock signal. A first edge, from a first level to a second level, of a word line signal is generated responsive to the first signal transition. A second signal transition at a second node is caused by a second circuit based on the clock signal. The second circuit and the first circuit are configured to cause the second signal transition to occur later than the first signal transition by a delay time. A first edge, from a third logic level to a fourth level, of a tracking word line signal is generated responsive to the second signal transition.

Abstract: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

Abstract: A semiconductor storage device includes a first cell array including a plurality of memory cells that are connected to a first word line and each of which is connected to each member of a first pair of bit lines. The semiconductor storage device also includes a second cell array including a plurality of memory cells that are connected to a second word line and each of which is connected to each member of a second pair of bit lines. The semiconductor storage device further includes a redundant cell array including a plurality of memory cells that are connected to a word line different from the first and the second word lines and each of which is connected to one member of the first pair of bit lines and to one member of the second pair of bit lines.

Abstract: A nonvolatile memory includes multiple banks, control logic and multiple read and write (RW) circuits. Each bank includes multiple memory cells. The control logic includes multiple storage units corresponding to the banks, respectively, and configured to output write enable signals and read enable signals to respective banks based on mode information stored in respective storage units. The RW circuits are connected to the banks, respectively, and are configured to independently enable or disable write and read operations of the respective banks in response to the write enable signals and the read enable signals of the respective banks. In an initial state after the mode information is stored in the respective storage units, the control logic activates the write enable signals and the read enable signals of the respective banks regardless of the mode information stored in the respective storage units.

Abstract: Disclosed is an apparatus and method for determining a parameter for programming a non-volatile memory circuit. On receiving write or erase operation a parameter is determined as a function of a circuit characteristic associated with a memory block. An adjusted condition, for example, read or write time, or the standard deviation of voltage thresholds in a distribution of cells, is then determined as a function of the parameter, and a command provided to the memory circuit to use the parameter in the next write or erase operation performed on the memory block. The method can be triggered by an event such as P/E cycle times and the condition is dynamically adjusted to extend the life of the memory circuit.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnects which extend in a first direction and are arranged in a second direction perpendicular to the first direction, a plurality of second interconnects which extend in the second direction and are arranged in the first direction, and a plurality of first storage modules which are formed in regions where the first interconnects and the second interconnects cross. The semiconductor memory device further comprises a first interconnect control module which supplies a voltage to the first interconnects, detects a first current flowing in the first interconnects, and outputs a first voltage corresponding to the first current, a reference voltage generator module which generates a second voltage based on a second current, and a regulator which generates a third voltage based on the first voltage and the second voltage.

Abstract: Embodiments relate to a method for representing data in a graphene-based memory device. The method includes applying a first voltage to a back gate of a graphene-based memory device and a second voltage to a first graphene layer of the graphene-based memory device. The graphene-based memory device includes the first graphene layer and a second graphene layer and a first insulation layer located between the first and second graphene layers. The first insulation layer has an opening between the first and second graphene layers. The back gate is located on an opposite side of the second graphene layer from the first insulation layer. The first graphene layer is configured to bend into the opening of the first insulation layer to contact the second graphene layer based on a first electrostatic force generated by the applying the first voltage to the back gate.

Abstract: An adaptive synchronous FIFO includes a plurality of input data latch stages that sample variable-length input data at a write clock frequency, and a data compression circuit that combines the variable-length input data, together with partial-row data from a row of the FIFO storage array, and writes the combined data at a read clock frequency. The number of data latch stages is adaptive according to the ratio of the read and write clock frequencies.

Abstract: Techniques for refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region coupled to a source line and a second region coupled to a carrier injection line. Each memory cell may also include a body region capacitively coupled to at least one word line and disposed between the first region and the second region and a decoupling resistor coupled to at least a portion of the body region.

Abstract: Disclosed is a semiconductor memory device that includes a plurality of channel memories mounted within a package and is capable of minimizing or reducing the number of through-silicon vias. With the semiconductor memory device, a row command or a row address on two or more channels is applied through a shared bus. The semiconductor memory device is capable of reducing an overhead of a die size by reducing the number of through-silicon vias. A method of driving a multi-channel semiconductor memory device including a plurality of memories, using a shared bus, is also provided.

Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data.

Abstract: A memory device is provided. The memory device includes a plurality of memory cells and a controller to write data to and read data from the memory cells. Each memory cell includes a first semiconductor material having a spontaneous polarization, a resistive ferroelectric material having a switchable spontaneous polarization, and a second semiconductor material having a spontaneous polarization, the resistive ferroelectric material being positioned between and in contact with the first and second semiconductor materials. The memory device can be configured to store energy that can be released by applying a voltage pulse to the memory device.

Abstract: A nonvolatile memory is provided which includes a memory cell array including a plurality of nonvolatile memory cells; a decoder connected with the memory cell array through a plurality of word lines; a data input/output circuit connected with the memory cell array through a plurality of bit lines; a voltage detector configured to detect a variation in a power supply voltage to output a voltage variation signal; and control logic configured to control the decoder and the data input/output circuit such that data stored at the memory cell array is invalidated in response to the voltage variation signal.

Abstract: Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state, after the first applying, determining that the memory cell failed to place in the desired state, after the determining, second applying a second signal to the memory cell, wherein the second signal corresponds to another state which is different than the desired state, and after the second applying, third applying a third signal to the memory cell to program the memory cell to the desired state, wherein the third signal corresponds to the desired state. Additional method and apparatus are described.

Abstract: A memory cell includes a true data node, a true pullup transistor, a complement data node and a complement pullup transistor. A true switching circuit selectively supplies a first or second supply voltage to a source of the true pullup transistor. A true bias switching circuit selectively supplies a third or fourth supply voltage to a body of the true pullup transistor. When writing a logic high data value to the true data storage node, a control circuit causes the true switching circuit to supply the second supply voltage and the true bias switching circuit to supply the third supply voltage. The second supply voltage is higher than the first supply voltage, and the fourth supply voltage is higher than the third supply voltage. A similar operation is performed with respect to the complement pullup transistor when writing a logic high data value to the complement data storage node.

Abstract: A page buffer circuit of a memory device including a plurality of Multi-Level Cells (MLCs) connected to at least a pair of bit lines includes a Most Significant Bit (MSB) latch, a Least Significant Bit (LSB) latch, a data I/O circuit, an inverted output circuit, a MSB verification circuit, and a LSB verification circuit. The MSB latch is configured to sense a voltage of a sensing node in response to a control signal and store an upper sensing data, and output an inverted upper sensing data, or store an input data and output an inverted input data. The LSB latch is configured to sense a voltage of the sensing node in response to the control signal, and store and output a lower sensing data, or store and output an input data received through the MSB latch. The data I/O circuit is connected to the MSB latch and a data I/O line, and is configured to perform the input and output of a sensing data or the input and output of a program data.