Abstract: A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.

Abstract: Among other things, one or more semiconductor devices and techniques for forming such semiconductor devices are provided. The semiconductor device comprises a strip-ground field plate. The strip-ground field plate is connected to a source region of the semiconductor device and/or a ground plane. The strip-ground field plate provides a release path for a gate edge electric field. The release path directs an electrical field away from a gate region of the semiconductor device. In this way, breakdown voltage and gate charge are improved.

Abstract: Embodiments include epitaxial source/drain regions having curved top surfaces and methods of forming the same. According to an exemplary embodiment, an epitaxial semiconductor region having a curved top surface may be formed by providing a region having a substantially planar bottom made of semiconductor material and sidewalls made of non-semiconductor material substantially perpendicular to the planar bottom, depositing a semiconductor layer having a crystalline portion on the flat bottom and amorphous portions on the sidewalls using a low pressure chemical vapor deposition process with a nitrogen carrier gas, and removing the amorphous portions from the sidewalls.

Abstract: The present disclosure provides semiconductor device structures with a first PMOS active region and a second PMOS active region provided within a semiconductor substrate. A silicon germanium channel layer is only formed over the second PMOS active region. Gate electrodes are formed over the first and second PMOS active regions, wherein the gate electrode over the second PMOS active region is formed over the silicon germanium channel.

Abstract: A semiconductor device includes a substrate, a stack structure and a transistor. The substrate includes a first region and a second region. The stack structure is formed over the substrate in the first region. The transistor structure has a gate formed in the second region. A bottom portion of the gate structure is disposed at a height from the substrate that is less than a height between the substrate and a bottom portion of the stack structure.

Abstract: The present invention discloses to a method of depositing the metal barrier layer comprising silicon dioxide. It is applied in the transistor device comprising a silicon substrate, a gate and a gate side wall. The method comprises the following steps: ions are implanted into the silicon substrate to form an active region in the said silicon substrate; a first dense silicon dioxide film is deposited; a second normal silicon dioxide film is deposited; the said transistor device is high temperature annealed. The present invention ensures that the implanted ion is not separated out of the substrate during the annealing. And it prevents the warping and fragment of the silicon surface.

Abstract: For the formation of a stressor on one or more of a source and drain defined on a fin of FINFET semiconductor structure, a method can be employed including performing selective epitaxial growth (SEG) on one or more of the source and drain defined on the fin, separating the fin from a bulk silicon substrate at one or more of the source and drain, and further performing SEG on one or more of the source and drain to form a wrap around epitaxial growth stressor that stresses a channel connecting the source and drain. The formed stressor can be formed so that the epitaxial growth material defining a wrap around configuration connects to the bulk substrate. The formed stressor can increase mobility in a channel connecting the defined source and drain.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) includes a semiconductor substrate and a interlayer dielectric (ILD) over the semiconductor substrate. A gate structure is formed within the ILD and disposed on the semiconductor substrate, wherein the gate structure includes a high-k dielectric material layer and a metal gate stack. One or more portions of a protection layer are formed over the gate stack, and a contact etch stop layer is formed over the ILD and over the one or more portions of the protection layer. The metal gate stack includes aluminum and the protection layer includes aluminum oxide.

Abstract: A semiconductor structure is provided including a transistor, the transistor including one or more elongated semiconductor regions, each of the one or more elongated semiconductor regions having a channel region, a gate electrode, wherein the gate electrode is provided at least at two opposite sides of each of the one or more elongated semiconductor regions, and a layer of a stress-creating material, the stress-creating material providing a variable stress, wherein the layer of stress-creating material is arranged to provide a stress at least in the channel region of each of the one or more elongated semiconductor regions, the stress provided in the channel region of each of the one or more elongated semiconductor regions being variable.

Abstract: A method includes depositing a first metal layer on a native SiO2 layer that is disposed on at least one of a source and a drain of a metal-oxide-semiconductor field-effect transistor (MOSFET). A metal oxide layer is formed from the native SiO2 layer and the first metal layer, wherein the remaining first metal layer, the metal oxide layer, and the at least one of the source and the drain form a metal-insulator-semiconductor (MIS) contact.

Abstract: One illustrative device disclosed herein includes a substrate fin formed in a substrate comprised of a first semiconductor material, wherein at least a sidewall of the substrate fin is positioned substantially in a <100> crystallographic direction of the crystalline structure of the substrate, a replacement fin structure positioned above the substrate fin, wherein the replacement fin structure is comprised of a semiconductor material that is different from the first semiconductor material, and a gate structure positioned around at least a portion of the replacement fin structure.

Abstract: A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a germanium (Ge) material layer formed on the semiconductor substrate, a diffusion barrier layer formed on the Ge material layer, a high-k dielectric having a high dielectric constant greater than approximately 3.9 formed over the diffusion barrier layer, and a conductive electrode layer formed above the high-k dielectric layer.

Abstract: A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm.

Abstract: Various aspects of the technology include a quad semiconductor power and/or switching FET comprising a pair of control/sync FET devices. Current may be distributed in parallel along source and drain fingers. Gate fingers and pads may be arranged in a serpentine configuration for applying gate signals to both ends of gate fingers. A single continuous ohmic metal finger includes both source and drain regions and functions as a source-drain node. A set of electrodes for distributing the current may be arrayed along the width of the source and/or drain fingers and oriented to cross the fingers along the length of the source and drain fingers. Current may be conducted from the electrodes to the source and drain fingers through vias disposed along the surface of the fingers. Heat developed in the source, drain, and gate fingers may be conducted through the vias to the electrodes and out of the device.

Abstract: A method including forming a dummy gate on a substrate, wherein the dummy gate includes an oxide, forming a pair of dielectric spacers on opposite sides of the dummy gate, and forming an inter-gate region above the substrate and in contact with at least one of the pair of dielectric spacers, the inter-gate region comprising a protective layer on top of a first oxide layer, wherein the protective layer comprises a material resistant to etching techniques designed to remove oxide. The method may further include removing the dummy gate to leave an opening, and forming a gate within the opening.

Abstract: A semiconductor element and a manufacturing method and an operating method of the same are provided. The semiconductor element includes a substrate, a first well, a first heavily doping region, at least a second heavily doping region, a gate layer, a third heavily doping region, and a fourth heavily doping region. The first well and the third heavily doping region are disposed on the substrate. The first and fourth heavily doping regions are disposed in the first well. The second heavily doping region is disposed in the first heavily doping region. The gate layer is disposed on the first well. The first, third, and fourth heavily doping regions having a first type doping are separated from one another. The first well and the second heavily doping region have a second type doping complementary to the first type doping.

Abstract: An electronic device can include a transistor having a drain region, a source region, a dielectric layer, and a gate electrode. The dielectric layer can have a first portion and a second portion, wherein the first portion is relatively thicker and closer to the drain region; the second portion is relatively thinner and closer to the source region. The gate electrode of the transistor can overlie the first and second portions of the dielectric layer. In another aspect, an electronic device can be formed using two different dielectric layers having different thicknesses. A gate electrode within the electronic device can be formed over portions of the two different dielectric layers. The process can eliminate masking and doping steps that may be otherwise used to keep the drain dopant concentration closer to the concentration as originally formed.

Abstract: The present disclosure relates to a device and method of forming enhanced channel carrier mobility within a transistor. Silicon carbon phosphorus (SiCP) source and drain regions are formed within the transistor with cyclic deposition etch (CDE) epitaxy, wherein both resistivity and strain are controlled by substitutional phosphorus. A carbon concentration of less than approximately 1% aids in control of the phosphorus dopant diffusion. Phosphorus dopant diffusion is also controlled by an anneal step which promotes uniform doping through both source and drain, as well as lightly-doped drain regions.

Abstract: A method for forming metal contacts within a semiconductor device includes forming a first-layer contact into a first dielectric layer that surrounds at least one gate electrode, the first-layer contact extending to a doped region of an underlying substrate. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second-layer contact extending through the second dielectric layer to the first-layer contact.

Abstract: An electronic device can include a buried conductive region and a semiconductor layer over the buried conductive region. The electronic device can further include a horizontally-oriented doped region and a vertical conductive region, wherein the vertical conductive region is electrically connected to the horizontally-oriented doped region and the buried conductive region. The electronic device can still further include an insulating layer overlying the horizontally-oriented doped region, and a first conductive electrode overlying the insulating layer and the horizontally-oriented doped region, wherein a portion of the vertical conductive region does not underlie the first conductive electrode. The electronic device can include a Schottky contact that allows for a Schottky diode to be connected in parallel with a transistor. Processes of forming an electronic device allow a vertical conductive region to be formed after a conductive electrode, a gate electrode, a source region, or both.

Abstract: A memory array and a method for electrically coupling memory cell access devices to a word line. The memory array includes a source line electrically coupled to each source terminal of the memory cell access devices. The memory array also includes a first set of at least two vertical pillars positioned above and electrically coupled to the source line. A second set of vertical pillars electrically isolated from the source line and positioned such that the source line does not extend below the second set of vertical pillars is also included. Furthermore, gate terminals of the memory cell access devices laterally surround the first set of vertical pillars and the second set of vertical pillars. Finally, a first word line contact is positioned between two of the second set of vertical pillars. The first word line contact is electrically coupled to the gate terminals.

Abstract: The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.

Abstract: A method for producing a semiconductor component structure in a semiconductor body. In one embodiment, the method includes producing two differently doped semiconductor zones of the same conduction type, and carrying out a first implantation, implanting dopant atoms of a first conduction type into the semiconductor body via one of the sides over the whole area. A mask is produced on the one side, partly leaving free the one side. A second implantation is carried out, implanting dopant atoms of the first conduction type into the region left free by the mask proceeding from the one of the sides.

Abstract: A power MOS field effect transistor (FET) has a plurality of transistor cells, each cell having a source region and a drain region to be contacted through a surface of a silicon wafer die. A first dielectric layer is disposed on the surface of the silicon wafer die and a plurality of grooves are formed in the first dielectric layer above the source regions and drain regions, respectively and filled with a conductive material. A second dielectric layer is disposed on a surface of the first dielectric layer and has openings to expose contact areas to said grooves. A metal layer is disposed on a surface of the second dielectric layer and filling the openings, wherein the metal layer is patterned and etched to form separate metal wires connecting each drain region and each source region of the plurality of transistor cells, respectively through the grooves.

Abstract: A method for fabricating FinFETs is described. A semiconductor substrate is patterned to form odd fins. Spacers are formed on the substrate and on the sidewalls of the odd fins, wherein each spacer has a substantially vertical sidewall. Even fins are then formed on the substrate between the spacers. A semiconductor structure for forming FinFETs is also described, which is fabricated using the above method.

Abstract: According to one embodiment, a nonvolatile memory device includes a first wiring layer. The device includes a second wiring layer intersecting with the first wiring layer. And the device includes a first memory layer provided at a position where the first wiring layer and the second wiring layer intersect. And the first memory layer contacts with the first wiring layer, and the first wiring layer is a layer which is capable of supplying a metal ion to the first memory layer.

Abstract: Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.

Abstract: An organic light emitting display device includes a substrate, a plurality of sub-pixels on the substrate, each sub-pixel including a first region configured to emit light and a second region configured to transmit external light, a plurality of thin film transistors disposed in the first region of the each sub-pixel, a plurality of first electrodes disposed in the first region of each sub-pixel and electrically connected to the thin film transistors, a first insulating layer on at least a portion of the first region of each sub-pixel to cover a portion of the first electrode, an organic emission layer on the first electrode, a second insulating layer on at least a portion of the second region of each sub-pixel, the second insulating layer including a plurality of openings therein, and a second electrode covering the organic emission layer, the first insulating layer, and the second insulating layer.

Abstract: A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.

Abstract: The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.

Abstract: A display substrate includes a switching transistor electrically connected to a gate line and a data line, the data line extending in a first direction substantially perpendicular to the gate line extending in a second direction, the switching transistor including a switching active pattern comprising amorphous silicon, a driving transistor electrically connected to a driving voltage line and the switching transistor, the driving voltage line extended in the first direction, the driving transistor including a driving active pattern comprising a metal oxide; and a light-emitting element electrically connected to the driving transistor.

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A diffusion barrier layer is disposed on top of the second III-V compound layer. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode.

Abstract: An apparatus and a method of manufacturing a thin film semiconductor device having a thin film transistor with improved electrical properties in organic light-emitting display apparatus are described.

Abstract: A nonvolatile memory structure includes a semiconductor substrate having thereon a first oxide define (OD) region, a second OD region and a third OD region arranged in a row. The first, second, and third OD regions are separated from one another by an isolation region. The isolation region includes a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second OD region and the third OD region. A select gate transistor is formed on the first OD region. A floating gate transistor is formed on the second OD region. The floating gate transistor is serially coupled to the select gate transistor. The floating gate transistor includes a floating gate that is completely overlapped with the underlying second OD region and is partially overlapped with the first and second intervening isolation regions.

Abstract: Transistors with memorized stress and methods for making such transistors. The methods include forming a transistor structure having a channel region, a source and drain region, and a gate dielectric; depositing a stressor over the channel region of the transistor structure, wherein the stressor provides a stress to the channel region; removing the stressor metal after the stress is memorized within the channel region; and depositing a work function metal over the channel region of the transistor structure, where the work function metal applies less stress to the channel region than the stress applied by the stressor. A transistor with memorized stress includes a source and drain region on a substrate; a stress-memorized channel region on the substrate that retains an externally applied stress; and a gate structure including a work function gate metal that applies less stress to the stress-memorized channel region than the externally applied stress.

Abstract: A method of forming a field effect transistor (FET) device includes forming a gate structure over a substrate, the gate structure including a wide bottom portion and a narrow portion formed on top of the bottom portion; the wide bottom portion comprising a metal material and having a first width that corresponds substantially to a transistor channel length, and the narrow portion also including a metal material having a second width smaller than the first width.

Abstract: A FinFET structure is formed by forming a hardmask layer on a substrate including a silicon-containing layer on an insulating layer. The hardmask layer includes first, second and third layers on the silicon-containing layer. An array of fins is formed from the hardmask layer and the silicon-containing layer. A gate is formed covering a portion but not all of a length of each of the array of fins. The portion covers each of the fins in the array. The gate defines source/drain regions on either side of the gate. A spacer is formed on each side of the gate, the forming of the spacer performed to remove the third layer from portions of the fins in the source/drain regions. The second layer of the hardmask layer is removed from the portions of the fins in the source/drain regions, and the fins in the source/drain regions are merged.

Abstract: A semiconductor device, which comprises: a semiconductor substrate; a channel region on the semiconductor substrate, said channel region including a quantum well structure; a source region and a drain region on the sides of the channel region; a gate structure on the channel region; wherein the materials for the channel region, the source region and the drain region have different energy bands, and a tunneling barrier structure exists between the source region and the channel region.

Abstract: A semiconductor device featuring a semiconductor chip including a MOSFET and having a first main surface and a second, opposing main surface, a source electrode pad and a gate electrode pad over the first main surface, a drain electrode over the second main surface, a source external terminal and a gate external terminal, each having a first main surface electrically connected to the source electrode pad and gate electrode pad of the chip, respectively, and a drain external terminal having a first main surface and a second, opposing main surface and being electrically connected to the second main surface of the chip, each of the source, gate and drain external terminals having second main surfaces thereof in a same plane, and, in a plan view of the external terminals, the gate external terminal has a portion located between the source and drain external terminals in at least one direction.

Abstract: A FinFET structure is formed by forming a hardmask layer on a substrate including a silicon-containing layer on an insulating layer. The hardmask layer includes first, second and third layers on the silicon-containing layer. An array of fins is formed from the hardmask layer and the silicon-containing layer. A gate is formed covering a portion but not all of a length of each of the array of fins. The portion covers each of the fins in the array. The gate defines source/drain regions on either side of the gate. A spacer is formed on each side of the gate, the forming of the spacer performed to remove the third layer from portions of the fins in the source/drain regions. The second layer of the hardmask layer is removed from the portions of the fins in the source/drain regions, and the fins in the source/drain regions are merged.

Abstract: A semiconductor device includes a first conductivity type well region formed by counter doping; a transistor having source and drain regions having a second conductivity type, at least one of the regions being arranged in the well region; a LOCOS region arranged around the at least one region in the well region; and a channel stop region having the first conductivity type arranged under the LOCOS region. The at least one region is arranged at a distance from a tip of a bird's beak of the LOCOS in a direction parallel to a channel width of the transistor. The channel stop region is arranged at a distance from the tip of the bird's beak at an opposite side to the at least one region.

Abstract: A method comprising, introducing a dopant type into a semiconductor layer to define a well region of the semiconductor layer, the well region comprising a channel region, and introducing a dopant type into the well region to define a multiple implant region substantially coinciding with the well region but excluding the channel region.

Abstract: One of objects is to provide a semiconductor film having stable characteristics. Further, one of objects is to provide a semiconductor element having stable characteristics. Further, one of objects is to provide a semiconductor device having stable characteristics. Specifically, a structure which includes a seed crystal layer (seed layer) including crystals each having a first crystal structure, one of surfaces of which is in contact with an insulating surface, and an oxide semiconductor film including crystals growing anisotropically, which is on the other surface of the seed crystal layer (seed layer) may be provided. With such a heterostructure, electric characteristics of the semiconductor film can be stabilized.

Abstract: Embodiments of the present disclosure are a FinFET device, and methods of forming a FinFET device. An embodiment is a method for forming a FinFET device, the method comprising forming a semiconductor strip over a semiconductor substrate, wherein the semiconductor strip is disposed in a dielectric layer, forming a gate over the semiconductor strip and the dielectric layer, and forming a first recess and a second recess in the semiconductor strip, wherein the first recess is on an opposite side of the gate from the second recess. The method further comprises forming a source region in the first recess and a drain region in the second recess, and recessing the dielectric layer, wherein a first portion of the semiconductor strip extends above a top surface of the dielectric layer forming a semiconductor fin.

Abstract: A method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process is disclosed, including a multi-step residue cleaning, including exposing the substrate to an aqua regia solution, followed by an exposure to a solution having hydrochloric acid and hydrogen peroxide. The SC2 solution can further react with remaining platinum residues, rendering it more soluble in an aqueous solution and thereby dissolving it from the surface of the substrate.

Abstract: Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers that are formed along the sidewall of the gate caps. Additionally, the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The two-step gate oxide combined with the self-aligned source contacts allow for the production of devices with a pitch in the deep sub-micron level. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract: A graphene electronic device includes a graphene channel layer on a substrate, a source electrode on an end portion of the graphene channel layer and a drain electrode on another end portion of the graphene channel layer, a gate oxide on the graphene channel layer and between the source electrode and the drain electrode, and a gate electrode on the gate oxide. The gate oxide has substantially the same shape as the graphene channel layer between the source electrode and the drain electrode.

Abstract: Methodology enabling a reduction of edge and strap cell size, and the resulting device are disclosed. Embodiments include: providing first and second NW regions on a substrate; providing first and second RX regions on the first and second NW regions, respectively; providing a contact on the substrate connecting the first and second RX regions; and providing a dummy PC on the substrate connecting the first and second RX regions. Other embodiments include: determining an RX region of an IC design; determining a PPLUS mask region extending along a horizontal direction and being on an entire upper surface of the RX region; determining a NW region extending along a vertical direction and separated from the RX region; and comparing an area of an overlap of the NW region and PPLUS mask region to a threshold value.

Abstract: An LDMOS device includes: a semiconductor layer formed over a semiconductor substrate; a gate structure disposed over the semiconductor layer; a first doped region disposed in the semiconductor layer adjacent to a first side of the gate structure; a second doped region disposed in the semiconductor layer adjacent to a second side of the gate structure; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a trench formed in the third doped region, the first doped region and the semiconductor layer under in the first doped region; an insulating layer covering the third doped region, the gate structure, and the fourth doped region; a conductive layer conformably formed over a bottom surface and sidewalls of the trench; a dielectric layer disposed in the trench; and a diffused region disposed in the semiconductor layer under the trench.