Abstract: Provided are an arithmetic circuit and an arithmetic apparatus capable of performing comparison involving conditional branch of three or more values at high speed. The arithmetic circuit includes a plurality of computing units, a plurality of selection circuits and a decision unit. The plurality of computing units perform arithmetic computations on input data and output flag information generated based on a result of the computations. The plurality of selection circuits select any one of the data input to the plurality of computing units. The decision unit receives the flag information from the plurality of computing units and controls select operation of each of the plurality of selection circuits.

Abstract: An arithmetic device includes a database that stores a first indicator representing a base unit included in a unit system being assigned with a prime number other than a prime factor of a prefix, and a second indicator derived by combining the base units, in a form of a simple fraction; a conversion section that obtains a plurality of physical quantities each including a quantity, a prefix, and possibly a unit, to derive a third indicator by converting the unit into the first indicator and multiplying the converted first indicator by the prefix, or when the unit belongs to the derived unit, by converting the unit into the second indicator and multiplying the converted second indicator by the prefix; and an arithmetic section that performs calculation between the quantities of the plurality of physical quantities and between the third indicators.

Abstract: An arithmetic processing device includes: a reception unit for receiving information including a numerical value and an operator; a generation unit generating arithmetic information regarding an arithmetic operation and having a plurality of codes including the numerical value and the operator that are received; and an information transmission unit transmitting the generated arithmetic information to an external device. The generation unit generates the arithmetic information in which the codes are arranged so that, when a plurality of rows including numerical values and operators are displayed on a display unit of the external device in accordance with the arithmetic information, an arrangement of a numerical value and an operator in each displayed row and an arrangement of a numerical value and an operator in another displayed row are matched to each other.

Abstract: A calculating unit for reducing an input number with respect to a modulus, wherein the input number has input number portions of different significances, wherein the input number portions represent the input number with respect to a division number, wherein the modulus has modulus portions of different significances, and wherein the modulus portions represent the modulus with respect to the division number, includes a unit for estimating a result of an integer division of the input number by the modulus using a stored most significant portion of the number, a stored most significant portion of the modulus and the number, and for storing the estimated result in a memory of the calculating unit, and a unit for calculating a reduction result based on a subtraction of a product of the modulus and a value derived from the estimated result from the number.

Abstract: Disclosed is a method of modular multiplication of two L-bit numbers (X, Y), the result defined from XY+mM, where M is the modulo, of L bits, and m is a number of L bits found and is divisible by 2L. L/k iterations are performed, an iteration i involving XYi+miM+R, Yi, mi being k-bit digits of rank i of Y, m from least significant bits, and R the previous iteration result. In each iteration, a first sub-loop of k/p iterations calculates a partial result of XYi+miM+R on k least significant bits of X, M, R, following decomposition of X, mi into p-bit digits. Starting each sub-loop iteration, the p bits of the current digit of mi are simultaneously produced. A second sub-loop calculates and sums the remaining partial results of XYi+miM+R using mi from the first sub-loop.

Abstract: In one exemplary embodiment of the invention, a method for computing a resultant and a free term of a scaled inverse of a first polynomial v(x) modulo a second polynomial fn(x), including: receiving the first polynomial v(x) modulo the second polynomial fn(x), where the second polynomial is of a form fn(x)=xn±1, where n=2k and k is an integer greater than 0; computing lowest two coefficients of a third polynomial g(z) that is a function of the first polynomial and the second polynomial, where g(z)?i=0n?1(v(?i)?z), where ?0, ?1, . . . , ?n?1 are roots of the second polynomial fn(x) over a field; outputting the lowest coefficient of g(z) as the resultant; and outputting the second lowest coefficient of g(z) divided by n as the free term of the scaled inverse of the first polynomial v(x) modulo the second polynomial fn(x).

Abstract: A logic circuit computes various modal interval arithmetic values using a plurality of arithmetic function units. A multiplexer gates the desired arithmetic values to a storage register.

Abstract: Embodiments of the present invention include an apparatus, method, and system for acoustic modeling. In an embodiment, an arithmetic logic unit for computing a one-dimensional score between a feature vector and a Gaussian probability distribution vector is provided. The arithmetic logic unit includes a computational logic unit configured to compute a first value based on a mean value and a variance value associated with a dimension of the Gaussian probability distribution vector and a dimension of a feature vector, a look up table module configured to output a second value based on the variance value, and a combination module configured to combine the first value and the second value to generate the one-dimensional score.

Abstract: Various systems, apparatuses, processes, and programs may be used to calculate a multiply-sum of two carry-less multiplications of two input operands. In particular implementations, a system, apparatus, process, and program may include the ability to use input data busses for the input operands and an output data bus for an overall calculation result, each bus including a width of 2n bits, where n is an integer greater than one. The system, apparatus, process, and program may also calculate the carry-less multiplications of the two input operands for a lower level of a hierarchical structure and calculating the at least one multiply-sum and at least one intermediate multiply-sum for a higher level of the structure based on the carry-less multiplications of the lower level. A certain number of multiply-sums may be output as an overall calculation result dependent on mode of operation using the full width of said output data bus.

Abstract: A pipelined circuit for performing a divide operation on small operand sizes. The circuit includes a plurality of stages connected together in a series to perform a subtractive divide algorithm based on iterative subtractions and shifts. Each stage computes two quotient bits and outputs a partial remainder value to the next stage in the series. The first and last stages utilize a radix-4 serial architecture with edge modifications to increase efficiency. The intermediate stages utilize a radix-4 parallel architecture. The divide architecture is pipelined such that input operands can be applied to the divider on each clock cycle.

Abstract: An arithmetic processing device includes: an arithmetic unit configured to execute an arithmetic operation; and a stream engine configured to execute stream processing, wherein a data bus of the arithmetic unit and a data bus of the stream engine are tightly coupled with each other.

Abstract: A method of showing the time of day by displaying a mathematical expression. A display capable of showing numbers, letters, and other characters is used. A plurality of numbers in conjunction with one or more mathematical symbols is displayed to create a mathematical expression which changes at regular intervals. Evaluating the expression according to mathematical conventions yields a number that represents the current time of day. Such a device will serve to stimulate the mind by providing a different mental exercise at regular intervals, with the built-in reward for success being the ability to determine the time of day. Expressions can be easy or difficult to evaluate, geared to any number of different types and abilities of viewers.

Abstract: A multiplier circuit and method multiply a signed value by a constant. The signed value received at an input port is separable into two or more splices. A first splice is a most significant one of the splices, and a second splice is another one of the splices. One or more memories provide respective partial products for the splices, and these memories include a shared memory. The shared memory provides the respective partial products for the first and second splices from storage locations in the shared memory. The storage locations that are readable to provide the respective partial product for the second splice are a subset of the storage locations that are readable to provide the respective partial product for the first splice. An addition circuit sums the respective partial products for the splices.

Abstract: An information processing device includes: plural input registers including a first input register and a second input register; an added value register; a first adding unit that performs addition processing for stored data of the first input register and stored data of the second input register; a second adding unit that performs addition processing for connected data, which is obtained by connecting the stored data of the first input register and the stored data of the second input register, and stored data of the added value register; and plural output registers in which a processing result of the first adding unit or the second adding unit is stored, wherein in each of given execution cycles, the first adding unit stores a processing result of the first adding unit in any one of the plural output registers and the second adding unit stores a processing result of the second adding unit in any one of the plural output registers.

Abstract: A configuration for FPGA logic is provided to perform random access channel (RACH) preamble detection used in 3G mobile communications to identify individual rows of a Hadamard matrix using a Walsh Hadamard Transform (WHT). The configuration provides minimal add/subtract circuit blocks for the WHT by using stages, each stage containing a shift register connected to an add/subtract circuit. The shift register has outputs provided from a tap into its nth and n/2 elements, the outputs being connected to an add/subtract circuit, wherein n is the order of the Hadamard matrix. In a further embodiment parallel connected shift registers are used in each stage to increase operation speed.

Abstract: A system, method, and computer program product for generating executable code for performing large integer operations on a parallel processing unit is disclosed. The method includes the steps of compiling a source code linked to a large integer library to generate an executable file and executing the executable file to perform a large integer operation using a parallel processing unit. The large integer library includes functions for processing large integers that are optimized for the parallel processing unit.

Abstract: A computer program obfuscating system including a processor to provide a computer program including at least one computer program variable, and add an opaque predicate to the computer program to obfuscate the computer program so that the opaque predicate added to the computer program comprises at least one polynomial including a polynomial P, during execution of the obfuscated computer program, the polynomial P is evaluated yielding at least one result including a first result R1, and during execution of the obfuscated computer program, the opaque predicate is evaluated based on the at least one result R1 such that a decision as to whether or not to perform the first command is dependent upon comparing the first result R1 to at least one value in accordance with a predetermined mathematical relationship. Related apparatus and methods are also included.

Abstract: A math circuit for computing an estimate of a transcendental function is described. A lookup table storage circuit has stored therein several groups of binary values, where each group of values represents a respective coefficient of a first polynomial that estimates the function to a high precision. A computing circuit uses a portion of a binary value, that is also taken from one of the groups of values, to evaluate a second polynomial that estimates the function to a low precision. Other embodiments are also described and claimed.

Abstract: Embodiments of the invention relate to processing queries. A query operation to be performed on a table of data is translated into a series of bit level logical operations using expansion and/or saturation operations. A mask is created from the series of bit level logical operations. This mask is then simultaneously applied to multiple rows from the table of data.

Abstract: A system for performing public key encryption is provided. The system supports mathematical operations for a plurality of public key encryption algorithms such as Rivert, Shamir, Aldeman (RSA) and Diffie-Hellman key exchange (DH) and Elliptic Curve Cryptosystem (ECC). The system supports both prime fields and different composite binary fields.

Abstract: Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

Abstract: A method, system and computer program product for verifying a result of a floating point square root operation is provided. The method includes: receiving a result of a floating point square root operation for an operand; performing a comparison of a magnitude of a least significant bit (LSB) of the operand and a magnitude of a most significant bit (MSB) of a remainder; and determining whether the result is correct based on the comparison.

Abstract: An arithmetic logic unit (ALU) for use within a flight control system is provided. The ALU comprises a first register configured to receive a first operand, a second register configured to receive a second operand, and an adder coupled to the first register and the second register. The adder is configured to generate a sum of the first operand and the second operand and to generate intermediate sums that are used to determine a product of the first operand and the second operand.

Abstract: Digital signal processing (“DSP”) block circuitry on an integrated circuit (“IC”) is adapted for use (e.g., in multiple instances of the DSP block circuitry on the IC) for implementing finite-impulse-response (“FIR”) digital filters in systolic form. Each DSP block may include (1) first and second multiplier circuitry and (2) adder circuitry for adding (a) outputs of the multipliers and (b) signals chained in from a first other instance of the DSP block circuitry. Systolic delay circuitry is provided for either the outputs of the first multiplier (upstream from the adder) or at least one of the sets of inputs to the first multiplier. Additional systolic delay circuitry is provided for outputs of the adder, which are chained out to a second other instance of the DSP block circuitry.

Abstract: A method and apparatus for implementation of high order MASH by reuse of single stage MASH have been described.

Abstract: A method, system and computer program product for verifying a result of a floating point division operation are provided. The method includes: receiving a result of a floating point division operation for a dividend and a divisor; performing a comparison of a magnitude of a least significant bit (LSB) of the dividend and a magnitude of a most significant bit (MSB) of a remainder; and determining whether the result is correct based on the comparison.

Abstract: A method for performing a m-ary right-to-left exponentiation using a base x, a secret exponent d and a modulus N, wherein m is a power of 2.

Abstract: An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step.

Abstract: An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectively provide a memory address to a memory unit in a first mode of operation and to selectively provide an arithmetic output in a second mode of operation. Further, the arithmetic logic and shifting device includes a programmable shifter device that has a first input to receive data from the memory unit, a second input to receive the arithmetic output, a third input to receive an operation code of a computer execution instruction, and a shifted output to provide shifted data.

Abstract: A processing unit, system, and method for performing a multiply operation in a multiply-add pipeline. To reduce the pipeline latency, the unrounded result of a multiply-add operation is bypassed to the inputs of the multiply-add pipeline for use in a subsequent operation. If it is determined that rounding is required for the prior operation, then the rounding will occur during the subsequent operation. During the subsequent operation, a Booth encoder not utilized by the multiply operation will output a rounding correction factor as a selection input to a Booth multiplexer not utilized by the multiply operation. When the Booth multiplexer receives the rounding correction factor, the Booth multiplexer will output a rounding correction value to a carry save adder (CSA) tree, and the CSA tree will generate the correct sum from the rounding correction value and the other partial products.

Abstract: Systems and/or methods that facilitate secure electronic communication of data are presented. A cryptographic component facilitates securing data associated with messages in accordance with a cryptographic protocol. The cryptographic component includes a randomized exponentiation component that facilitates decryption of data and generation of digital signatures by exponentiating exponents associated with messages. An exponent is divided into more than one subexponent at an exponent bit that corresponds to a random number. Exponentiation of the first subexponent can be performed based on a left-to-right-type of exponentiation algorithm, and exponentiation of the second subexponent can be performed based on a right-to-left square-and-multiply-type of exponentiation algorithm. The final value is based on the exponentiations of the subexponents and can be decrypted data or a digital signature, which can be provided as an output.

Abstract: Methods, apparatuses, and computer program products for squaring an operand include identifying a fixed-point value with a fixed word size and a substring size for substrings of the fixed-point value, wherein the fixed-point value comprises a binary bit string. A square of the fixed-point value can be determined using the fixed point value, the substring size, and least significant bits of the fix-point value equal to the substring size.

Abstract: A Generalized Programmable Counter Array (GPCA) is a reconfigurable multi-operand adder, which can be reprogrammed to sum a plurality of operands of arbitrary size. The GPCA is configured to compress the input words down to two operands using parallel counters. Resulting operands are then summed using a standard Ripple Carry Adder to produce the final result. The GPCA consists of a linear arrangement of identical compressor slices (CSlice).

Abstract: An arithmetic logic unit (ALU) for use within a flight control system is provided. The ALU comprises a first register configured to receive a first operand, a second register configured to receive a second operand, and an adder coupled to the first register and the second register. The adder is configured to generate a sum of the first operand and the second operand and to generate intermediate sums that are used to determine a product of the first operand and the second operand.

Abstract: In a digital system with more than one clock source, lack of synchronization between the clock sources may cause overflow or underflow in sample buffers, also called sample slipping. Sample slipping may lead to undesirable artifacts in the processed signal due to discontinuities introduced by the addition or removal of extra samples. To smooth out discontinuities caused by sample slipping, samples are filtered to when a buffer overflow condition occurs, and the samples are interpolated to produce additional samples when a buffer underflow condition occurs. The interpolated samples may also be filtered. The filtering and interpolation operations can be readily implemented without adding significant burden to the computational complexity of a real-time digital system.

Abstract: A system including a processor for adjusting the dynamic range of an image including a plurality of pixels. The processor segments the pixels into blocks, and computes statistical values for each block based on intensity values of the pixels. The processor also adjusts the dynamic range of the image by controlling the intensity values of the pixels based on the statistical values.

Abstract: A digital processor for recovering a source bitstream from an encoded bitstream that has been encoded according to a context adaptive binary arithmetic coding (CABAC) algorithm. The processor includes a first execution unit and a second execution unit. The first execution unit generates first execution data by operating on a first register and a second register, and stores the first execution data in the first register. The first execution data includes a current output bit, a temporary range value and a temporary offset value. The current output bit corresponds to a bit of the source bitstream. The second execution unit generates second execution data by operating on the first register and the second register, and stores the second execution data in the second register. The second execution data includes a normalized range value and a normalized offset value.

Abstract: A mantissa/exponent splitter splits an input value X=(1+X1/223)×(2^X2) into a mantissa X1 and an exponent X2. An interpolation processor references the mantissa/exponent splitter using the mantissa X1 and determines a power value (log2(1+X1/223)) through an interpolation process. A logarithmic calculator determines a logarithmic value Z=log2 XY=Y(X2+log2(1+X1/223)) from the exponent X2 and the power value from the interpolation processor. The integer/fraction splitter splits the logarithmic value Z into an integer Zint and a fraction Zamari. The interpolation processor references a power of fraction table storage unit in response to the fraction Zamari and determines a power value (2^Zamari) through the interpolation process. The power calculator determines XY=2^Z=(2^Zamari)×(2^Zint), thereby resulting in the input value X to the power of Y.

Abstract: Techniques are generally described for generating an identification number for an integrated circuit (IC). In some examples, methods for generating an identification of an IC may comprise selecting circuit elements of the IC, evaluating measurements of an attribute of the IC for the selected circuit elements, wherein individual measurements are associated with corresponding input vectors previously applied to the IC, solving a plurality of equations formulated based at least in part on the measurements taken of the attribute of the IC for the selected circuit elements to determine scaling factors for the selected circuit elements, and transforming the determined scaling factors for the selected circuit elements to generate an identification number of the IC. Additional variants and embodiments may also be disclosed.

Abstract: Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

Abstract: An arithmetic logic stage in a graphics pipeline includes a number of arithmetic logic units (ALUs). The ALUs each include, for example, a multiplier and an adder. The ALUs are interconnected by circuitry that, for example, routes the output from the multiplier in one ALU to both the adder in that ALU and an adder in another ALU.

Abstract: An arithmetic logic unit (ALU) for use within a flight control system is provided. The ALU comprises a first register configured to receive a first operand, a second register configured to receive a second operand, and an adder coupled to the first register and the second register. The adder is configured to generate a sum of the first operand and the second operand and to generate intermediate sums that are used to determine a product of the first operand and the second operand.

Abstract: An arithmetic circuit includes: a detection unit that detects a code error for plural signals respectively modulated by different modulation methods and encoded by a predetermined encoding method; a measurement unit that measures a number of times of signal variations at a predetermined frequency or less generated in the plural signals in a period from detection of the code error in the detection unit to first detection of predetermined data contained in the plural signals with respect to each of the plural signals; and a selection unit that selects one signal from the plural signals based on a measurement result of the measurement unit.

Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

Abstract: A modular arithmetic unit includes a first input generator receiving first data to generate a first operand; a second input generator receiving second data to generate a second operand; an accumulator performing an accumulate/shift operation to add the first and second operands and outputting the carry and sum; a carry propagation adder adding the carry and the sum to output a result; and a data handler receiving either external data or the result and outputting the first data and the second data.

Abstract: The present invention enables efficient matrix multiplication operations on parallel processing devices. One embodiment is a method for mapping CTAs to result matrix tiles for matrix multiplication operations. Another embodiment is a second method for mapping CTAs to result tiles. Yet other embodiments are methods for mapping the individual threads of a CTA to the elements of a tile for result tile computations, source tile copy operations, and source tile copy and transpose operations. The present invention advantageously enables result matrix elements to be computed on a tile-by-tile basis using multiple CTAs executing concurrently on different streaming multiprocessors, enables source tiles to be copied to local memory to reduce the number accesses from the global memory when computing a result tile, and enables coalesced read operations from the global memory as well as write operations to the local memory without bank conflicts.

Abstract: An arithmetic logic unit is provided. The arithmetic logic unit preferably includes a minimum of routing delays. An arithmetic logic unit according to the invention preferably receives a plurality of operands from a plurality of operand registers, performs an arithmetic operation on the operands, obtains a result of the arithmetic operation and that transmits the result to a result register. The arithmetic logic unit includes a signal propagation path that includes no greater than two routing paths that connect non-immediately adjacent logic elements.

Abstract: Digital signal processing (“DSP”) block circuitry on an integrated circuit (“IC”) is adapted for use (e.g., in multiple instances of the DSP block circuitry on the IC) for implementing finite-impulse-response (“FIR”) digital filters in systolic form. Each DSP block may include (1) first and second multiplier circuitry and (2) adder circuitry for adding (a) outputs of the multipliers and (b) signals chained in from a first other instance of the DSP block circuitry. Systolic delay circuitry is provided for either the outputs of the first multiplier (upstream from the adder) or at least one of the sets of inputs to the first multiplier. Additional systolic delay circuitry is provided for outputs of the adder, which are chained out to a second other instance of the DSP block circuitry.

Abstract: A data encoding scheme for transmission of data from one circuit to another circuit considers the Hamming Weight of combined multiple words to determine whether to invert or not invert an individual word to be transmitted. The multi-word data encoding scheme performs DBI encoding with data inversion conducted based on the total HW in the combined multiple words. The decision to invert or not invert each of the multiple words is made based on the sum of the individual Hamming Weights of each of the words. Such encoding has the advantage that SSO noise is dramatically reduced when the encoded data has a large number of words transmitted from one circuit to another circuit over a wide parallel bus.

Abstract: Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.