Abstract: The invention relates to an input module (32) for a programmable logic controller able to be connected to a plurality of elements of an automated chain, the module (32) comprising: inputs (32A, 32B), each input (32A, 32B) being able to receive the signal from at least one element of the plurality of elements, interfaces (40A, 40B), each interface (40A, 40B) being associated with a single input and comprising at least one output (40A6, 40B6) able to operate in three different states, a test block (42), and a processing sub-module (24) able to compare the state of the output (40A6, 40B6) of each interface (40A, 40B) with the state imposed by the test block (42) and to deduce an operating anomaly of the module (32, 34) therefrom.

Abstract: A semiconductor memory device according to an embodiment comprises: a memory cell array, the memory cell array including a memory block, the memory block including a memory cell, the memory cell including a semiconductor layer, a conductive layer, and a charge accumulation layer, the charge accumulation layer being disposed between the semiconductor layer and the conductive layer; and a control circuit that executes an access operation on the memory cell, the control circuit, triggered by the access operation, detecting a leak current of the conductive layer, and when the leak current is a certain value or more, executing a faulty memory block processing that registers as an access-prohibited region the memory block including the conductive layer.

Abstract: An integrated circuit package is presented. In an embodiment, the integrated circuit package has contact pads formed on the top side of a package substrate, a die electrically attached to the contact pads, and input/output (I/O) pads formed on the top side of the package substrate. The I/O pads are electrically connected to the contact pads. The integrated circuit package also includes a flex cable receptacle electrically connected to the I/O pads on the top side of the package substrate. The flex cable receptacle is non-compressively attachable to a flex cable connector and includes receptacle connection pins electrically connected to the I/O pads.

Abstract: Active surveillance of potential lead anomalies in implanted medical leads utilizes test signal(s) delivered through an output current pathway and induced signals monitored via an independent monitor current pathway to detect for any reactions to the test signals in the induced signals. Various specific responses can be initiated if a potential insulation breach or anomaly in the implanted medical lead is identified due to detection of a “positive” test result in the induced signals on the monitor current pathway in reaction to a test signal applied to the output current pathway.

Abstract: A compatibility indication system includes a connectable module that includes a first connector and a first wireless communication device that is configured to transmit connectable module information. A computing system includes a second connector and a second wireless communication device that is configured to receive the connectable module information when the connectable module is located adjacent the second connector. A compatibility engine in the computing system is coupled to the second wireless communication device and configured to receive the connectable module information, determine a compatibility level of the connectable module, and activate a warning that is based on the compatibility level before the first connector on the connectable module is connected to the second connector on the computing system.

Abstract: Methods and articles of manufacture for hosting a safety critical application on an uncontrolled data processing device are provided. Various combinations of installation, functional, host integrity, coexistence, interoperability, power management, and environment checks are performed at various times to determine if the safety critical application operates properly on the device. The operation of the SCA on the UDPD may be controlled accordingly.

Abstract: Embodiments of the present invention provide methods, program products, and systems for testing a memory cell arrangement. Embodiments of the present invention can determine categories of memory fail conditions by checking memory cells of with a sequence of test parameter configurations for a malfunction using test parameters, storing for test parameter configurations for which a malfunction is detected, and assigning the respective test parameter configuration with a bit fail count comprising the number of malfunctioning memory cells. Embodiments of the present invention can be used to create a relational data structure representing test parameter configurations and can combine one or more test parameter configurations and can create a representation of the bit fail counts of the respective test parameter configurations.

Abstract: A method and electronic device for identifying when to replace/clean a probe card or socket are provided. The method includes receiving an ID of the probe card or socket from a tag associated with the probe card or socket before performing an insertion on a test system. For the received ID, there is determined a count of insertions performed on the probe card, and an indication to replace/clean the probe card or socket is generated when the count of insertions equals the threshold value.

Abstract: A touch panel includes electrode lines and a detecting circuit. The detecting circuit includes driving units and detecting units. The driving units are configured to sequentially output driving signals to the electrodes lines according to a first clock signal, so as to change the voltage levels of the electrode lines. Two ends of each of the electrode lines are respectively coupled to a driving unit and a corresponding detecting unit. The detecting units are configured to sequentially scan the voltage levels of the electrode lines according to a second clock signal and to output scan signals, in which the first clock signal and the second clock signal have different frequencies. The detecting circuit generates a detecting signal according to the scan signals.

Abstract: A semiconductor device operates with electric power supplied from a direct-current power supply to an internal circuit in a state where a bypass capacitor is connected to a power supply terminal. The semiconductor device includes a load current control unit and a detection unit. The load current control unit changes an electric current supplied from the power supply terminal only in a predetermined operation period. The detection unit detects a voltage of the power supply terminal. The detection unit outputs a detection signal when the voltage is higher than a threshold upper limit in a case of being provided with the threshold upper limit. Alternatively, the detection unit outputs a detection signal when the voltage is lower than a threshold lower limit in a case of being provided with the threshold lower limit.

Abstract: Some forms relate to an electronic assembly that includes a plurality of electronic package. The electronic assembly includes a frame and a first electronic package mounted on the frame. The first electronic package includes a first pin grid array. The electronic assembly further includes a second electronic package mounted on the frame. The second electronic package includes a second pin grid array. The electronic assembly further includes an actuation mechanism on the frame. The actuation mechanism is configured to move the first electronic package and the second electronic package relative to the frame during operation of the actuation mechanism.

Abstract: A saturation edge detection circuit for testing a saturation level in an insulated gate bipolar transistor (“IGBT”) includes a first input operable to receive an on signal, a second input coupled to an IGBT driver circuit, and an output coupled to a control electrode of the IGBT. The output indicates a change in a state of a saturation voltage associated with the IGBT during operation of the IGBT.

Abstract: A semiconductor device may include a semiconductor substrate; a test circuit array region; a pad region on the semiconductor substrate and at at least a first side of the test circuit array region and outside of the test circuit array region, transistors arranged in the test circuit array region in a first direction and a second direction perpendicular to the first direction, source lines spaced apart from each other in the second direction, each of the source lines extending in the first direction and electrically connected to corresponding source electrodes of the transistors, and drain lines spaced apart from each other in the second direction, each of the drain lines extending in the first direction and electrically connected to drain electrodes of the transistors.

Abstract: Provided are a tester configured to test a semiconductor device and a test system including the same. The tester may include at least one contact unit and at least one memory controller. The contact unit is in contact with the semiconductor device. The memory controller is connected to the contact unit. The memory controller controls data input/output (I/O) operations of the semiconductor device and tests the semiconductor device.

Abstract: Methods and articles of manufacture for hosting a safety critical application on an uncontrolled data processing device are provided. Various combinations of installation, functional, host integrity, coexistence, interoperability, power management, and environment checks are performed at various times to determine if the safety critical application operates properly on the device. The operation of the SCA on the UDPD may be controlled accordingly.

Abstract: An inspection apparatus for inspecting an inspection object. The inspection object includes a base body and wiring passing through the base body. The inspection apparatus includes an insulating substrate, a first electrode in the substrate with a portion of the first electrode exposed from a surface of the substrate to form a connection portion which may be electrically connected with the wiring, and a second electrode in the substrate. The first electrode and the second electrode are spaced apart, have mutually parallel portions, and are electrically insulated from each other.

Abstract: Methods and articles of manufacture for hosting a safety critical application on an uncontrolled data processing device are provided. Various combinations of installation, functional, host integrity, coexistence, interoperability, power management, and environment checks are performed at various times to determine if the safety critical application operates properly on the device. The operation of the SCA on the UDPD may be controlled accordingly.

Abstract: Methods and articles of manufacture for hosting a safety critical application on an uncontrolled data processing device are provided. Various combinations of installation, functional, host integrity, coexistence, interoperability, power management, and environment checks are performed at various times to determine if the safety critical application operates properly on the device. The operation of the SCA on the UDPD may be controlled accordingly.

Abstract: Methods and articles of manufacture for hosting a safety critical application on an uncontrolled data processing device are provided. Various combinations of installation, functional, host integrity, coexistence, interoperability, power management, and environment checks are performed at various times to determine if the safety critical application operates properly on the device. The operation of the SCA on the UDPD may be controlled accordingly.

Abstract: Methods and articles of manufacture for hosting a safety critical application on an uncontrolled data processing device are provided. Various combinations of installation, functional, host integrity, coexistence, interoperability, power management, and environment checks are performed at various times to determine if the safety critical application operates properly on the device. The operation of the SCA on the UDPD may be controlled accordingly.

Abstract: Methods and articles of manufacture for hosting a safety critical application on an uncontrolled data processing device are provided. Various combinations of installation, functional, host integrity, coexistence, interoperability, power management, and environment checks are performed at various times to determine if the safety critical application operates properly on the device. The operation of the SCA on the UDPD may be controlled accordingly.

Abstract: Methods and articles of manufacture for hosting a safety critical application on an uncontrolled data processing device are provided. Various combinations of installation, functional, host integrity, coexistence, interoperability, power management, and environment checks are performed at various times to determine if the safety critical application operates properly on the device. The operation of the SCA on the UDPD may be controlled accordingly.

Abstract: Methods and articles of manufacture for hosting a safety critical application on an uncontrolled data processing device are provided. Various combinations of installation, functional, host integrity, coexistence, interoperability, power management, and environment checks are performed at various times to determine if the safety critical application operates properly on the device. The operation of the SCA on the UDPD may be controlled accordingly.

Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.

Abstract: A semiconductor device may include a target voltage generation section configured to generate first and second target voltages. The semiconductor device may include a comparison signal generation section configured to compare levels of the first and second target voltages with levels of first and second internal voltages, and generate first and second comparison signals. The semiconductor device may include a latch code generation section configured to latch global codes and output first and second latch codes in response to the first and second comparison signals. The semiconductor device may include a selection code generation section configured to generate first and second selection codes for adjusting levels of the first and second internal voltages using either the global codes or the first and second latch codes.

Abstract: A device for monitoring a working environment in which electronic circuit boards are present includes: a) test circuit boards with pairs of traces and circuitry for determining the electrical resistance between the traces, the test boards being positioned in a pathway effective for directing air across the test traces; b) control elements for controlling the flow of air through the pathway and for controlling power applied to the test board traces; c) data storage for storing data relating to acceptable electrical resistance between test traces; d) circuitry for comparing measured electrical resistance between two test traces to a stored value for the acceptable electrical resistance between two test traces; and e) an output for communicating the results of the comparison between the measured electrical resistance between two test traces and the stored value for the acceptable electrical resistance between two test traces.

Abstract: A test apparatus includes a multi-channel probe plate having an electrically insulating body with opposing first and second main surfaces, and a plurality of spaced apart electrically conductive coupling regions embedded in or attached to the body at the first main surface. Each of the electrically conductive coupling regions is configured to cover a different zone of a semiconductor package when the semiconductor package is positioned in close proximity to the first main surface of the plate. The test apparatus further includes circuitry electrically connected to each of the coupling regions of the probe plate via a different channel. The circuitry is operable to measure a parameter indicative of the degree of capacitive coupling between each electrically conductive coupling region of the probe plate and the zone of the semiconductor package covered by the corresponding electrically conductive coupling region.

Abstract: A method for diagnosing a frequency converter is used for a frequency converter having a positive and negative DC link voltage which is applied via bridges of switching elements in an alternating sequence to phases of a motor. Pulse width modulation (PWM) signals drive the switching elements for a respective one of the phases and current sensors capture phase currents. In a step a), PWM signals are applied as test patterns to the switching elements. In a step b), sensor signals of the current current sensors are picked up. In a step c), the sensor signals are evaluated by ascertaining a presence of the DC link voltage upon a displacement current being recognized in the sensor signals.

Abstract: A test system may be provided in which devices under test are loaded into test trays and tested at a plurality of test stations. To test a device under test at a given test station, the test tray may be installed into a test fixture at the test station. Test equipment at each test station may communicate with the device under test via the test fixture and the test tray. Each test tray may have a spring-loaded corner portion that may be used to secure the device under test to the test tray. The test tray may have contacts that mate with corresponding contacts at each test fixture and may have a built in cable that connects to the device under test. The test fixture may have a detector that can detect whether or not a test tray is present on the test fixture.

Abstract: An electrostatic capacitive touch screen panel includes a plurality of first touch electrodes divided in a first direction and a second direction crossing the first direction; a plurality of second touch electrodes disposed between first touch electrodes neighboring in the first direction and extending in the second direction; and a plurality of grounding/floating electrodes disposed between the first touch electrodes and second touch electrodes arranged in the second direction and extending in the second direction.

Abstract: A connection device for computing devices is described. In one or more implementations, a connection device comprises a plurality of connection portions that are physically and communicatively coupled, one to another. Each of the plurality of connection portions has at least one communication contact configured to form a communicative coupling with a respective one of a plurality of computing devices and with at least one other communication contact of another one of the connections portions to support communication between the plurality of computing devices. Each of the plurality of connection portions also includes a magnetic coupling device to form a removable magnetic attachment to the respective one of the plurality of computing devices.

Abstract: A system and method for performing stress measurement on rotating parts is disclosed. The system may include a laser assembly configured to emit a plurality of laser beams having different wavelengths, and a probe assembly mounted proximal to a rotatable part in a device. The probe assembly may be configured to output a reflected laser beam onto a first target on the rotatable part. The probe assembly may be configured to output another reflected laser beam onto a second target on the rotatable part. The probe assembly may include a redirector, and a lens assembly mounted proximal to the redirector and configured to converge the laser beams. The redirector may be configured to change the direction of each emitted laser beam.

Abstract: Embodiments of the present invention provide methods, program products, and systems for testing a memory cell arrangement. Embodiments of the present invention can determine categories of memory fail conditions by checking memory cells of with a sequence of test parameter configurations for a malfunction using test parameters, storing for test parameter configurations for which a malfunction is detected, and assigning the respective test parameter configuration with a bit fail count comprising the number of malfunctioning memory cells. Embodiments of the present invention can be used to create a relational data structure representing test parameter configurations and can combine one or more test parameter configurations and can create a representation of the bit fail counts of the respective test parameter configurations.

Abstract: A magnetic flowmeter for measuring flow of a process fluid in a pipe includes a magnetic coil disposed adjacent to the pipe configured to apply a magnetic field to the process fluid. First and second electrodes are disposed within the pipe and electrically coupled to the process fluid and configured to sense an electromotive force (EMF) induced in the process fluid due to the applied magnetic field and flow of the process fluid. Input circuitry is coupled to the first and second electrodes and provides an output related to the sensed EMF. Diagnostic circuitry coupled to the input circuitry is configured to identify a saturation related condition and responsively provide a diagnostic output. In another embodiment, saturation prevention circuitry prevents saturation of the input circuitry.

Abstract: In embodiments of the present invention improved capabilities are described for a Radio Frequency Identification (RFID) tag comprising a memory system with a plurality of one time programmable (OTP) non-volatile memory locations configured to emulate at least one multiple time programmable (MTP) memory location, wherein the plurality of OTP non-volatile memory locations configured to emulate the at least one MTP memory location are associated with one address, the one address being readable and writable.

Abstract: This disclosure relates generally to an electrical circuit and method. A capacitive element can be configured to be coupled in series with an electronic package component. A path resistance can be electrically coupled to the capacitive element. A driver can be configured to electrically charge the capacitive element. A voltage detector can be coupled to the capacitive element and configured to identify a condition of the electronic package component based on a measured voltage of the capacitive element.

Abstract: A system, comprising a control regulation system, an inverter, a DC link capacitor, which is coupled to input connections of the inverter, at least one control apparatus, which is coupled to semiconductor switches of a half-bridge of the inverter, wherein the control apparatus is configured to actuate the semiconductor switch on the basis of a control signal from the control regulation system, at least one temperature sensor, which is configured to determine a change in temperature of the semiconductor switches in the half-bridge of the inverter, and a voltage sensor, which is configured to determine the voltage at the DC link capacitor is disclosed.

Abstract: A probe apparatus 10 has a movable mounting table 12 that mounts a wafer W on which multiple power devices are formed; a probe card 14 that is provided above the mounting table 12 and has multiple probes 14A; a conductive film electrode 13 formed on a mounting surface of the mounting table 12 and an outer peripheral surface thereof; and a measurement line 16 that electrically connects the conductive film electrode 13 to a tester 17. Further, the probe apparatus measures electrical characteristics of the power devices on the mounting table 12 at a wafer level. Furthermore, the measurement line 16 includes a switch device 18 configured to open and close an electric path of the measurement line 16 between the conductive film electrode 13 and the tester 17.

Abstract: A lighting circuit comprises a first rectifying diode (D1), a second rectifying diode (D2), a third rectifying diode (D3), a fourth rectifying diode (D4), a first group of LEDs (LED11, . . . , LED1n), a second group of LEDs (LED21, . . . , LED2n), a third group of LEDs (LED31, . . . , LED3n), and a fourth group of LEDs (LED41, . . . , LED4n). The first group of LEDs (LED11, . . . , LED1n) is connected between the anode and the cathode of the first rectifying diode (D1); the second group of LEDs (LED21, . . . , LED2n) is connected between the anode and the cathode of the second rectifying diode (D2); the third group of LEDs (LED31, . . . , LED3n) is connected between the anode and the cathode of the third rectifying diode (D3); the fourth group of LEDs (LED41, . . . , LED4n) is connected between the anode and the cathode of the fourth rectifying diode (D4).

Abstract: An apparatus for testing a thyristor valve includes: a current source circuit that provides an electric current when a thyristor valve as a test target is turned on; a voltage source circuit that provides a reverse voltage or a forward voltage when the thyristor valve is turned off; and a first auxiliary valve provided between a connection point between the thyristor valve and the voltage source circuit and the current source circuit, and that insulates the current source circuit from the voltage source circuit to protect the current source circuit from a high voltage of the voltage source circuit.

Abstract: Methods and systems determine an original statistical variance of an original failure distribution of a component (that is common to all chips tested) that occurs during manufacturing of wafers containing such chips. These methods and systems determine a first statistical variance of a reconstructed failure distribution, relative to sample size; and determine a second statistical variance of a mean time to failure of the component, relative to sample size. The first and second statistical variances are combined into a total reconstruction variance. Methods and systems determine whether the original statistical variance is less than the total reconstruction variance to identify whether the process of creating the reconstructed failure distribution can be used. Therefore, these methods and systems prohibit testing of the additional wafers manufactured using the specific wafer design and manufacturing process when on the original statistical variance is less than the total reconstruction variance.

Abstract: Custom antenna structures may be used to compensate for manufacturing variations in electronic device antennas. An antenna may have an antenna feed and conductive structures such as portions of a peripheral conductive electronic device housing member. The custom antenna structures compensate for manufacturing variations that could potentially lead to undesired variations in antenna performance. The custom antenna structures may make customized alterations to antenna feed structures or conductive paths within an antenna. An antenna may be formed from a conductive housing member that surrounds an electronic device. The custom antenna structures may be formed from a printed circuit board with a customizable trace. The customizable trace may have a contact pad portion on the printed circuit board. The customizable trace may be customized to connect the pad to a desired one of a plurality of contacts associated with the conductive housing member to form a customized antenna feed terminal.

Abstract: The load drive device of the present invention comprises a load drive unit for switching on/off output current that flows to an inductive load; and an overcurrent protection circuit for detecting whether the output current is in an overcurrent state, wherein the load drive unit has an output transistor connected to one end of the inductive load; and a pre-driver for generating a control signal of the output transistor in accordance with an input signal, and the pre-driver has a first drive unit for switching on/off the output transistor during normal operation; and a second drive unit for switching off the output transistor more slowly than the first drive unit during overcurrent protection operation.

Abstract: In one general embodiment, a method is provided for fabricating magnetic structures using post-deposition tilting. A thin film magnetic transducer structure is formed on a substantially planar portion of a substrate such that a plane of deposition of the thin film transducer structure is substantially parallel to a plane of the substrate. Additionally, the thin film transducer structure is caused to tilt at an angle relative to the plane of the substrate. The thin film transducer is fixed at the angle after being tilted.

Abstract: An overcurrent protection circuit includes a load drive section driving a load, a wire coupled with the load and the load drive section, a current detection section detecting a load current value of an electric current that flows to the load, an addition and subtraction section determining an addition and subtraction value based on the load current value and transmitting an integration result of addition and subtraction, a comparison circuit comparing the integration result with a threshold value, and a control circuit controlling the load drive section based on the comparison result. The addition and subtraction section includes an addition value determination circuit that determines an addition value in the addition and subtraction value based on the load current value and a function expression or information indicating a relationship between the load current value and the addition value.

Abstract: A driver circuit may include a first node, and a first circuit to generate on the first node an inverted replica of an input signal during driver switching between a first supply voltage and a first reference voltage, the inverted replica having a threshold voltage value based upon a second reference voltage greater than the first supply voltage. The driver circuit may include a cascode stage to be controlled by the second reference voltage and to be coupled between a second supply voltage and the first node, a delay circuit to generate a delayed replica of the input signal, an amplifier, and a switching network to couple the control terminal of the active load transistor to one of the first reference voltage and the first node based upon the input signal.

Abstract: A test apparatus includes a test apparatus may include a core suitable for accommodating a semiconductor device to be tested, a wrapper data register suitable for storing data used for testing the semiconductor device, and a bandwidth controller suitable for adaptively controlling a data bandwidth between the core and the wrapper data register according to the semiconductor device to be tested.

Abstract: Methods and apparatus concern testing a disk drive suspension. Testing includes moving a first portion of a suspension relative to a second portion. A pair of motors is mounted on the suspension. The testing further includes measuring an electrical signal that is intrinsically produced by the motors, combined in a circuit, in response to the relative movement. The testing further includes identifying a characteristic of the electrical signal and determining whether an orientation of one or both of the motors is reversed relative to an intended motor orientation based on the characteristic of the electrical signal. The testing can determine whether the orientation of both motors matches the intended motor orientation, whether the orientation of one motor is reversed in a same polarity condition, whether the orientations of both motors are reversed in a mutual reverse polarity condition, or whether the suspension has a mechanical or electrical defect.

Abstract: To supply a signal in which the occurrence of delays is prevented to a storage circuit. To provide a novel semiconductor device in which a load applied to a logic circuit is low. The following structure is completed: a storage circuit to which a plurality of data signals and a selection signal are supplied connects two combination circuits, and a storage circuit has a function of selecting one of a plurality of data signals in accordance with the selection signal. A selection circuit is not necessarily provided between the storage circuit and the combination circuit. As a result, the combination circuit can supply a signal in which the occurrence of delays is prevented to the storage circuit.

Abstract: Some of the embodiments of the present disclosure provide a method for operating a testing system to test a device, wherein the testing system comprises a pressing module, the method comprising attaching the device to the pressing module of the testing system; while the testing system operates in a first mode of testing, pressing the pressing module to a first position such that (i) the device is electrically coupled to a first component via a first pin, and (ii) the device is electrically isolated from a second component via a second pin; and while the testing system operates in a second mode of testing, pressing the pressing module to a second position such that (i) the device is electrically isolated from first component via the first pin, and (ii) the device is electrically coupled to the second component via the second pin.