Abstract: An integrated leadframe and bezel structure includes a planar carrier frame, a plurality of bonding leads, a die pad region, and a bezel structure. The bezel structure includes a bending portion shaped and disposed to facilitate a portion of said bezel structure being bent out of the plane of said carrier frame. A sensor IC may be secured to the die pad region, and wire bonds made to permit external connection to the sensor IC. The bezel structure includes portions which are bent such that their upper extent is in or above a sensing surface. The assembly is encapsulated, exposing on the top surface part of the bezel portions and the upper surface of the sensor IC, and on the bottom surface the contact pads. Two or more bezel portions may be provided, one or more on each side of the sensor IC.

Abstract: A method is provided for fabricating a semiconductor device. The method includes removing a silicon material from a gate structure located on a substrate through a cycle including: etching the silicon material to remove a portion thereof, where the substrate is spun at a spin rate, applying a cleaning agent to the substrate, and drying the substrate; and repeating the cycle, where a subsequent cycle includes a subsequent spin rate for spinning the substrate during the etching and where the subsequent spin rate does not exceed the spin rate of the previous cycle.

Abstract: Optimized electrodes for ReRAM memory cells and methods for forming the same are discloses. One aspect comprises forming a first electrode, forming a state change element in contact with the first electrode, treating the state change element, and forming a second electrode. Treating the state change element increases the barrier height at the interface between the second electrode and the state change element. Another aspect comprises forming a first electrode in a manner to deliberately establish a certain degree of amorphization in the first electrode, forming a state change element in contact with the first electrode. The degree of amorphization of the first electrode is either at least as great as the degree of amorphization of the state change element or no more than 5 percent less than the degree of amorphization of the state change element.

Abstract: An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a method of forming the same. The crack deflecting scribe seal includes continuous metal layers and continuous contacts and continuous vias between the continuous metal layers. The continuous metal layers do not extend past the continuous contacts and continuous vias. The continuous contacts and continuous vias are recessed from edges of the underlying continuous metal layers on the scribeline side of the scribe seal, providing an angled outer surface on the scribe seal which may desirably terminate crack propagation or deflect crack propagation upward to a top surface of the scribeline or the crack deflecting scribe seal.

Abstract: An integrated circuit includes a visually discernable indicator formed as part of the integrated circuit to indicate a directionality of a non-visually discernable characteristic of the integrated circuit.

Abstract: In accordance with the invention, the structure (10A, 10B) of a patterned nanoscale or near nanoscale device (“nanostructure”) is repaired and/or enhanced by liquifying the patterned device in the presence of appropriate guiding conditions for a period of time and then permitting the device to solidify. Advantageous guiding conditions include adjacent spaced apart or contacting surfaces (12, 13A, 13B) to control surface structure and preserve verticality and unconstrained boundaries to permit smoothing of edge roughness. In an advantageous embodiment, a flat planar surface (12) is disposed overlying a patterned nanostructure surface (13A, 13B) and the surface (13A, 13B) is liquified by a high intensity light source to repair or enhance the nanoscale features.

Abstract: A guard ring structure for use in a semiconductor device. The guard ring structure includes a semiconductor layer stack having a first layer and a second layer on top of the first layer, gates structures formed in the first layer; and guard rings formed in the first layer. The second layer has a dopant concentration that is higher than the dopant concentration of the first layer. The gates and the guard rings are formed simultaneously using a single mask.

Abstract: Structures of a system on a chip are disclosed. In one embodiment, the system on a chip (SoC) includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary, and a conductive cage disposed enclosing the RF component. The conductive cage shields the semiconductor component from electromagnetic radiation originating from the RF circuit.

Abstract: Provided is a method for fabricating a semiconductor device that includes providing a semiconductor substrate having a front side and a backside, where active or passive devices are formed in the front side, rotating the semiconductor substrate, and etching the backside of the semiconductor substrate by introducing a first etchant while the substrate is rotated, the first etchant including an R—COOH.

Abstract: Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes a semiconductor substrate including unit pixels, a metal line and an interlayer dielectric layer formed on the semiconductor substrate, a passivation layer formed on the inter-layer dielectric layer and provided on a surface thereof with lens patterns corresponding to the unit pixels, and lens-type color filters formed on the lens patterns.

Abstract: A PRAM and method of forming the same are disclosed. In various embodiments, the PRAM includes a lower insulation layer formed on a semiconductor substrate, a phase change material pattern formed on the lower insulation layer and a heating electrode contacting the phase change material pattern. The heating electrode can be formed of a material having a positive temperature coefficient such that specific resistance of the material increases as a function of temperature.

Abstract: An interconnect layer is formed on a lower face of a silicon wafer, a support substrate is adhered over a lower face of the interconnect layer, and a thickness reduction of the silicon wafer is performed from an upper face side. Next, a photodiode is formed in an upper face of the silicon wafer, and a microlens is formed at a position corresponding to the photodiode. An adhesive layer is formed on the silicon wafer in a region not covering the microlens, a low refractive index layer having a lower refractive index than the microlens is formed in a region covering the microlens, and a glass substrate is adhered to the silicon wafer by the adhesive layer. The support substrate is removed from the interconnect layer, and a solder ball is bonded to a lower face of the interconnect layer. Thereafter, a CMOS image sensor is manufactured by dicing the silicon wafer.

Abstract: Winged via structures to increase overlay margin are generally described. In one example, a method comprises depositing a sacrificial layer to an interlayer dielectric, the interlayer dielectric being coupled with a semiconductor substrate, forming at least one trench structure in the sacrificial layer wherein the trench structure comprises a first direction along a length of the trench structure and a second direction along a width of the trench structure wherein the second direction is substantially perpendicular to the first direction, depositing a light sensitive material to the trench structure and the sacrificial layer, and patterning at least one winged via structure in the light sensitive material to overlay the trench structure wherein the winged via structure extends in the second direction beyond the width of the trench structure onto the sacrificial layer.

Abstract: Methods and structures are provided for implementing reduced hot spot thermal effects for silicon-on-insulator (SOI) circuits. A silicon-on-insulator (SOI) structure includes a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, an active layer carried by the thin BOX layer, and a pad oxide layer carried by the active layer. A thermal conductive path is built to reduce thermal effects of a hotspot area in the active layer and extends from the active layer to the backside of the SOI structure. A trench etched from the topside to the active layer, and is filled with a thermal connection material. A thermal connection from a backside of the SOI structure includes an opening etched into the silicon substrate layer from the backside and filled with a thermal connection material.

Abstract: A method of fabrication of laser gain material and utilization of such media includes the steps of introducing a transitional metal, preferably Cr2+ thin film of controllable thickness on the ZnS crystal facets after crystal growth by means of pulse laser deposition or plasma sputtering, thermal annealing of the crystals for effective thermal diffusion of the dopant into the crystal volume with a temperature and exposition time providing the highest concentration of the dopant in the volume without degrading laser performance due to scattering and concentration quenching, and formation of a microchip laser either by means of direct deposition of mirrors on flat and parallel polished facets of a thin Cr:ZnS wafer or by relying on the internal reflectance of such facets.

Abstract: An IPS mode LCD device and a method for fabricating the same are disclosed. A switching device is formed at each unit pixel and then a passivation layer is formed thereon. A first concave pattern and a second concave pattern at each unit pixel by using one mask are formed, and a common electrode is formed in the first concave pattern and a pixel electrode is formed in the second concave pattern. Accordingly, the entire fabrication process is simplified.

Abstract: Disclosed here in is a method for patterning an active region in a semiconductor device using a space patterning process that includes forming a partition pattern having partition pattern elements arranged in a square shape on a semiconductor substrate; forming a spacer on side walls of the partition pattern; removing the partition pattern; separating the spacer into first and second spacer portions to expose a portion of the semiconductor substrate; and etching the exposed portion of the semiconductor substrate to form a trench, wherein portions of the semiconductor substrate overlapped with the first and second spacer portions define an active region.

Abstract: To provide a semiconductor substrate whose columnar member for alignment is difficult to fall off and a manufacturing method thereof. An alignment mark 24 (columnar member for alignment) and protection posts 26 surrounding the alignment mark 24 to protect the alignment mark are disposed in an alignment mark forming region 14 of a semiconductor wafer 101 (semiconductor substrate). Each of the protection posts has a diameter (maximum diameter) of, for example, 0.6 ?m. The protection posts 26 are arranged such that the diameter of each of the columnar protection posts 26 is greater than a diameter (for example, 0.2 ?m) of the alignment mark 24. That is, the protection posts 26 are arranged such that the contact area between each of the protection posts 26 and an underlayer thereof (dummy wire layer 22) is greater than the contact area between the alignment mark 24 and an underlayer thereof (dummy wire layer 22).

Abstract: A semiconductor device includes a semiconductor chip and at least one metal line over a first side of the semiconductor chip. The semiconductor device includes a molded body covering at least a second side of the semiconductor chip. The molded body includes at least one recess.

Abstract: A fabricating process for a substrate with an embedded passive component is provided. The fabricating process includes the following steps. First, a substrate including a top conductive layer, a bottom conductive layer, and at least a dielectric layer is provided. The top conductive layer and the bottom conductive layer are separately disposed on a top surface and a bottom surface of the dielectric layer. Next, a plurality of plating through holes is formed in the substrate. Then, the top and the bottom conductive layers are patterned to form a patterned top conductive layer and a patterned bottom conductive layer separately, and the dielectric layer is exposed in part. The patterned top conductive layer and the patterned bottom conductive layer have many traces and many trenches formed by the traces. Thereafter, the trenches are filled with a material, wherein the traces and the material are adapted for forming the passive component.

Abstract: A semiconductor device includes a tunnel insulating film formed on a semiconductor substrate, a charge storage insulating film formed on the tunnel insulating film and including at least two separated low oxygen concentration portions and a high oxygen concentration portion positioned between the adjacent low oxygen concentration portions and having a higher oxygen concentration than the low oxygen concentration portions, a charge block insulating film formed on the charge storage insulating film, and control gate electrodes formed on the charge block insulating film and above the low oxygen concentration portions.

Abstract: A capacitor includes a bottom electrode, a dielectric layer and a top electrode over a substrate. A RuXTiYOZ film is included in at least one of the bottom and top electrodes, where x, y and z are positive real numbers. A method of fabricating the capacitor through a sequential formation of a bottom electrode, a dielectric layer and a top electrode over a substrate includes forming a RuXTiYOZ film during a formation of at least one of the bottom electrode and top electrode, where x, y and z are positive real numbers.

Abstract: A fuse part in a semiconductor device has a plurality of fuse lines extended along a first direction with a given width along a second direction. The fuse part includes a first conductive pattern having a space part formed in a fuse line region over a substrate, wherein portions of the first conductive pattern are spaced apart by the space part along the first direction. The fuse part includes a first insulation pattern formed over the space part, the first insulation pattern having a width smaller than a width of the first conductive pattern along the second direction and a thickness greater than a thickness of the first conductive pattern, and a second conductive pattern formed over the first insulation pattern, the second conductive pattern having a width greater than the width of the first insulation pattern along the second direction.

Abstract: A lead frame including a shield plate, a main frame, interconnection arms, support arms, and terminals is sealed with a resin mold including a base portion for embedding the shield plate and a peripheral wall for embedding the interconnection arms and support arms, thus forming a package base. The interconnection arms and support arms are subjected to bending so as to depress the shield plate in position compared with the main frame. At least one semiconductor chip (e.g. a microphone chip) is mounted on the base portion just above the shield plate. A cover having conductivity is attached onto the main frame exposed on the upper end of the peripheral wall, thus completely producing a semiconductor device encapsulated in a package. A sound hole is formed in the cover or the package base so as to allow the internal space of the package to communicate with the external space.

Abstract: A method for forming a pattern of a semiconductor device includes: forming a first mask film and a second mask film over an underlying layer; partially etching the first and second mask films using a photoresist mask pattern as an etching mask to form a intermediate mask pattern having a protrusion shape and including first and second mask film layers, over a remaining portion of the first mask film; forming a first spacer at sidewalls of the intermediate mask pattern etching the remaining portion of the first mask film and the first mask film layer of the intermediate mask pattern using the first spacer and the second mask film layer of the intermediate mask pattern as an etching mask to expose the underlying layer and form a mask pattern having first and second mask film layers; forming a second spacer at sidewalls of the mask pattern; and removing the mask pattern to form a symmetrical spacer pattern.

Abstract: A method for manufacturing CMOS image sensor is provided. The method includes: forming an interlayer dielectric on a semiconductor substrate on which a plurality of photodiodes are formed; forming a plurality of color filters at regular intervals on the interlayer dielectric; forming a planarization layer on an entire surface of the semiconductor substrate including the color filters; forming sacrificial resist patterns on the planarization layer, the sacrificial resist patterns being spaced apart from each other; forming spacers at sidewalls of the sacrificial resist patterns; removing the sacrificial resist patterns; forming a resist layer on the planarization layer on which only the spacers remain; removing the spacers; and reflowing the resist layer at a predetermined temperature to form a microlens.

Abstract: A solid electrolytic capacitor includes a package for a capacitor element including an anode lead portion and a cathode portion. The package includes an insulating resin member which is arranged to cover the capacitor element and which includes hole portions formed therethrough. An anode terminal of the solid electrolytic capacitor includes a metal-plating layer which is placed in the hole portion to be electrically connected to the anode lead portion through the hole portion. A cathode terminal of the solid electrolytic capacitor includes a metal-plating layer which is placed in the hole portion to be electrically connected to the cathode conducting portion through the hole portion.

Abstract: A nonvolatile semiconductor memory that allows simultaneous implementation of high performance transistors in a low-voltage circuit region and transistors with high withstand voltages in a high-voltage circuit region.

Abstract: A method of manufacturing a semiconductor device is provided which comprises: forming a first gate insulating film and a second gate insulating film in an active region of a semiconductor substrate; introducing an impurity of a first conductivity type into a first site where a first body region is to be formed, the first site being disposed under the first gate insulating film in the active region; forming a gate electrode on each of the first gate insulating film and the second gate insulating film; and introducing an impurity of the first conductivity type into the first site and a second site where a second body region is to be formed, the second site being disposed under the second gate insulating film in the active region, to form the first body region and the second body region, respectively.

Abstract: An integrated circuit includes a plurality of memory cells, each memory cell including a memory element and a select device; and a plurality of word lines and bit lines connected to the memory cells. The bit lines, word lines, and the memory elements are arranged above the select devices.

Abstract: A method for manufacturing a non-volatile memory device having a charge trap layer comprises in one embodiment: forming a first dielectric layer over a semiconductor substrate; forming a second dielectric layer having a higher dielectric constant than that of the first dielectric layer over the first dielectric layer; forming a nitride buffer layer for preventing an interfacial reaction over the second dielectric layer; forming a third dielectric layer by supplying a radical oxidation source onto the nitride buffer layer to oxidize the nitride buffer layer, thereby forming a tunneling layer comprising the first, second, and third dielectric layers; and forming a charge trap layer, a shielding layer, and a control gate electrode layer over the tunneling layer.

Abstract: The liquid crystal display device includes a first substrate 1110a, a second substrate 1110b placed to face the first substrate, and a liquid crystal layer 1120 interposed between the first substrate and the second substrate. The liquid crystal display device has a plurality of pixels each including a first electrode 1111 formed on the first substrate, a second electrode 1131 formed on the second substrate, and the liquid crystal layer interposed between the first electrode and the second electrode. The second electrode 1131 has at least one opening 1114 formed at a predetermined position in the pixel, the first substrate has a shading region in gaps between the plurality of pixels, and a wall structure 1115 is placed regularly on the surface of the first substrate facing the liquid crystal layer in the shading region.

Abstract: In an embodiment, a simplified method of manufacturing a semiconductor device reduces a step between cell and peripheral areas. First and second openings are formed through a plurality of thin layers including a support layer on a substrate. A storage electrode and a guide ring are formed on sidewalls and bottoms of the first and second openings, respectively. A support pattern is formed so that the support layer in the cell area is partially etched and the support layer in the peripheral area remains un-etched, thus the support pattern supports and surrounds the storage electrodes adjacent to each other in the cell area and prevents an etching of a layer underlying the support layer in the peripheral area. A dielectric layer and a plate electrode are formed on the storage electrode to complete a semiconductor device with the reduced step.

Abstract: InP epitaxial material is directly bonded onto a Silicon-On-Insulator (SOI) wafer having Vertical Outgassing Channels (VOCs) between the bonding surface and the insulator (buried oxide, or BOX) layer. H2O and other molecules near the bonding surface migrate to the closest VOC and are quenched in the buried oxide (BOX) layer quickly by combining with bridging oxygen ions and forming pairs of stable nonbridging hydroxyl groups (Si—OH). Various sizes and spacings of channels are envisioned for various devices.

Abstract: Provided is a semiconductor package having a power device and methods of fabricating the same. The semiconductor package includes a lead frame, a polymer layer component on the lead frame, a metal layer component on the polymer layer component, and a semiconductor chip on the metal layer component. The polymer layer component may include a material formed by adding alumina Al2O3 an aluminum nitride (AlN), or a boron nitride BN to an epoxy resin. The polymer layer component may have high thermal conductivity and good electric insulating characteristics.

Abstract: A surface of a single crystal semiconductor substrate is irradiated with ions to form a damaged region, an insulating layer is formed over the surface of the single crystal semiconductor substrate, and a surface of a substrate having an insulating surface is made to be in contact with a surface of the insulating layer to bond the substrate having an insulating surface to the single crystal semiconductor substrate. Then, the single crystal semiconductor substrate is separated at the damaged region by performing heat treatment to form a single crystal semiconductor layer over the substrate having an insulating surface, and the single crystal semiconductor layer is patterned to form a plurality of island-shaped semiconductor layers. One of the island-shaped semiconductor layers is irradiated with a laser beam which is shaped to entirely cover the island-shaped semiconductor layer.

Abstract: System and method for reducing contact resistance and improving barrier properties is provided. An embodiment comprises a dielectric layer and contacts extending through the dielectric layer to connect to conductive regions. A contact barrier layer is formed between the conductive regions and the contacts by electroless plating the conductive regions after openings have been formed through the dielectric layer for the contact. The contact barrier layer is then treated to fill the grain boundary of the contact barrier layer, thereby improving the contact resistance. In another embodiment, the contact barrier layer is formed on the conductive regions by electroless plating prior to the formation of the dielectric layer.

Abstract: A reliability of a semiconductor device having a phase-change memory is improved. A phase-change memory device has a bottom-electrode plug buried in an interlayer insulator that is provided on a main surface of a semiconductor substrate, an electric conductive material layer provided on an upper portion of the bottom-electrode plug and on the interlayer insulator, a phase-change material layer provided on the electric conductive material layer, and an upper-electrode plug provided on the phase-change material layer. The bottom-electrode plug and the upper-electrode plug which configure the phase-change memory device are provided at respective different positions in a plane of the semiconductor substrate.

Abstract: A liquid crystal display device includes a reflection region for reflecting incident light toward a display surface, wherein, the reflection region includes a metal layer formed on a substrate, a semiconductor layer formed above the metal layer, and a reflective layer formed above the semiconductor layer; and the reflection region includes a first recess formed on a surface of the reflective layer, a second recess formed on the surface of the reflective layer in the first recess, and a third recess formed on the surface of the reflective layer in the second recess. The liquid crystal display device provides a low-cost transflective-type or reflection-type liquid crystal display device having a high image quality.

Abstract: A method for fabricating a semiconductor device and the device made thereof are disclosed. In one aspect, the method includes providing a substrate comprising a semiconductor material. The method further includes patterning at least one fin in the substrate, the fin comprising a top surface, at least one sidewall surface, and at least one corner. A supersaturation of point defects is created in the at least one fin. The at least one fin is annealed and then cooled down such that semiconductor atoms of the semiconductor material migrate via the point defects.

Abstract: A fuse of a semiconductor device, and a method for forming the same, wherein the fuse includes a zigzag-shaped fuse portion on a planar structure, thereby reducing energy when the fuse is cut. The laser irradiation time can be reduced, thereby preventing fuse cutting defects and damages on a neighboring fuse. Also, a laser point where a laser is irradiated is not affected by misalignment, thereby improving characteristics of the fuse.

Abstract: A method for forming a tungsten plug is provided. The method can include forming a first tungsten seed layer on an insulating layer having a via hole, forming a second tungsten seed layer on the first tungsten seed layer, and forming a tungsten-buried layer in the via hole. The second tungsten seed layer can be from about 1.3 times to about 2.5 times thicker than the first tungsten seed layer.

Abstract: The invention concerns a method of producing at least one mechanical component of a MEMS or NEMS structure from a monocrystalline silicon substrate, comprising the steps of: forming anchoring zones in one face of the substrate to delimit the mechanical component, forming, on the face of the substrate, a lower protective layer made of material other than silicon and obtained by epitaxy from the face of the substrate, forming, on the lower protective layer, a silicon layer obtained by epitaxy from the lower protective layer, forming an upper protective layer on the silicon layer, etching the upper protective layer, the silicon layer and the lower protective layer, according to a pattern defining the mechanical component, until the substrate is reached and to provide access routes to the substrate, forming a protective layer on the walls formed by the etching of the pattern of the mechanical component in the epitaxied silicon layer, releasing the mechanical component by isotropic etching of the substrate from

Abstract: A method for forming dielectric films including metal nitride silicate on a silicon substrate, comprises a first step of depositing a film containing metal and silicon on a silicon substrate in a non-oxidizing atmosphere using a sputtering method; a second step of forming a film containing nitrogen, metal and silicon by nitriding the film containing metal and silicon; and a third step of forming a metal nitride silicate film by oxidizing the film containing nitrogen, metal and silicon.

Abstract: In an embodiment, a method of creating an alignment mark on a substrate includes forming a plurality of lines segmented into electrically conducting line segments and space segments, thereby forming spaces between the lines to form a macroscopic structure in a first layer of the substrate, creating a plurality of electrically conducting trenches in a second layer of the substrate, and arranging the plurality of trenches to be in electrical contact with the line segments and overlapping the space segments at least partially.

Abstract: The invention relates to microelectronic semiconductor devices, and to mass-production of the same on semiconductor wafers with novel crack-deflecting structures and methods. According to the invention, a semiconductor device includes an active circuit area surrounded by an inactive area and circumscribed with a bulwark having a crack-deflecting face oriented toward the periphery of the device. Embodiments of the invention are disclosed, in which a semiconductor device, or multiple devices on a wafer, include bulwarks having series of minor arcs with their chords oriented toward the peripheries of the devices. Additional embodiments of the invention described include bulwarks having series of right angles oriented toward the peripheries of the devices. Examples of the invention also include preferred embodiments wherein the bulwarks further comprise series of discrete pickets, parallel bulwarks, and bulwarks in combination with scribe seals.

Abstract: By forming thermocouples in a contact structure of a semiconductor device, respective extension lines of the thermocouples may be routed to any desired location within the die, without consuming valuable semiconductor area in the device layer. Thus, an appropriate network of measurement points of interest may be provided, while at the same time allowing the application of well-established process techniques and materials. Hence, temperature-dependent signals may be obtained from hot spots substantially without being affected by design constraints in the device layer.

Abstract: A mountable integrated circuit package system includes: providing a base; depositing a photoresist on the base; patterning the photoresist with an opening; filling the opening with a metal; depositing a further metal on the metal to form a lead pad; removing the photoresist; attaching a die over the base; bonding wires between the die and the lead pad; encapsulating the die and the lead pad in an encapsulation formed into a lead pad lock adjacent the lead pad; and removing the base.

Abstract: Provided is a light emitting diode (LED). The LED, in one embodiment, includes a reflective layer located over a substrate and a quarter wave plate emitter layer located over the reflective layer. The quarter wave plate emitter layer, in this embodiment, is substantially crystalline in nature, and further wherein an extra-ordinary axis of the quarter wave plate emitter layer is located in a plane thereof. The LED, in this embodiment, further includes a transmissive/reflective polarization layer located over the quarter wave plate emitter layer, wherein a transmission direction of the transmissive/reflective polarization layer is oriented at about 45 degrees with respect to the extra-ordinary axis.

Abstract: The invention is directed to particular polymer compositions that may be generally characterized by the formula: wherein the variables L, M and N represent the relative molar fractions of the monomers and satisfy the expressions 0<L?0.8; 0<M?0.2; 0<L?0.35; and L+M+N=1; and, wherein R1, R2 and R3 are independently selected from C1-C6 alkyls and derivatives thereof. The invention is also directed to polymer compositions that, when used to form a buffer layer or pattern, can be more easily removed from the surface of a semiconductor substrate, thereby increasing productivity and/or reducing the likelihood of defects and failures associated with residual photoresist material.