Abstract: A solution for designing a semiconductor device, in which two or more attributes of a pair of electrodes are determined to, for example, minimize resistance between the electrodes, is provided. Each electrode can include a current feeding contact from which multiple fingers extend, which are interdigitated with the fingers of the other electrode in an alternating pattern. The attributes can include a target depth of each finger, a target effective width of each pair of adjacent fingers, and one or more target attributes of the current feeding contacts. Subsequently, the device and/or a circuit including the device can be fabricated.

Abstract: Methods of forming a substrate for microelectronic packaging may include electroplating a metal seed layer onto a sidewall of a trench extending through the substrate. The sidewall may be patterned to have at least one slot therein that extends through the substrate. This slot is formed to be sufficiently narrow to block plating of the metal seed layer onto sidewalls of the slot. Thereafter, the at least a pair of electrodes are selectively electroplated onto side-by-side portions of the metal seed layer on the sidewall of the trench. During this electroplating step, the slot is used to provide a self-aligned separation between the pair of electrodes.

Abstract: An adhesion layer and a supporting substrate are provided on the entire surface of the first surface side of a substrate with a metal seed film provided on the first surface side of the substrate. After the removal of the adhesion layer and the supporting substrate provided on the first surface of the substrate, an exposed part of the metal seed film is removed. After this, a plurality of semiconductor chips is stacked and first reflow is performed to the semiconductor chips.

Abstract: In a static memory cell comprising six MOS transistors, the MOS transistors have a structure in which the drain, gate and source formed on the substrate are arranged in the vertical direction and the gate surrounds the columnar semiconductor layer, the substrate comprises a first active region having a first conductive type and a second active region having a second conductive type, and diffusion layers constructing the active regions are mutually connected via a silicide layer formed on the substrate surface, thereby realizing an SRAM cell with small surface area. In addition, drain diffusion layers having the same conductive type as a first well positioned on the substrate are surrounded by a first anti-leak diffusion layer and a second anti-leak diffusion layer having a conductive type different from the first well and being shallower than the first well, and thereby controlling leakage to the substrate.

Abstract: A method of forming metal lines of a semiconductor device, comprising providing a semiconductor substrate in which a plurality of gates and junctions formed between the gates are included in a cell area and a peripheral area; forming an insulating layer over the semiconductor substrate including the gates; forming an etch protection layer over the insulating layer; etching the etch protection layer and the insulating layer, and gap-filling conductive material to form contact plugs contacting the junctions of the cell area; and, forming first metal lines contacting the contact plugs and forming second metal lines contacting the junctions of the peripheral area by etching the etch protection layer and the insulating layer.

Abstract: Methods of forming capping structures on one or more different material surfaces are provided. One embodiment includes disposing a semiconductor structure in a reduced pressure chamber, forming a capping GCIB within the reduced pressure chamber, and directing the capping GCIB onto at least one of the one or more different material surfaces, so as to form at least one capping structure on the one or more surfaces onto which the capping GCIB is directed.

Abstract: A multi-layer thick metallization structure for a microelectronic device includes a first barrier layer (111), a first metal layer (112) over the first barrier layer, a first passivation layer (113) over the first metal layer, a via structure (114) extending through the first passivation layer, a second barrier layer (115) over the first passivation layer and in the via structure, a second metal layer (116) over the second barrier layer, and a second passivation layer (117) over the second metal layer and the first passivation layer.

Abstract: There is provided a method of forming a semiconductor device having stacked transistors. When forming a contact hole for connecting the stacked transistors to each other, ohmic layers on the bottom and the sidewall of the common contact hole are separately formed. As a result, the respective ohmic layers are optimally formed to meet requirements or conditions. Accordingly, the contact resistance of the common contact may be minimized so that it is possible to enhance the speed of the semiconductor device.

Abstract: A method of forming a method a conductive wire. The method includes forming a dielectric hardmask layer on a dielectric layer; forming an electrically conductive hardmask layer on the dielectric hardmask layer; forming a trench extending through the conductive and dielectric hardmask layers into the dielectric layer; depositing a liner/seed layer on the conductive hardmask layer and the sidewalls and bottom of the trench; filling the trench with a fill material; removing the liner/seed layer from the top surface of the conductive hardmask layer; removing the fill material from the trench; electroplating a metal layer onto exposed surfaces of the conductive hardmask layer and liner/seed layer; and removing the metal layer and the conductive hardmask layer from the dielectric hardmask layer so the metal layer and edges of the liner/seed layer are coplanar with the top surface of the dielectric hardmask layer.

Abstract: A ball grid array (BGA) package having a half-etched bonding pad and a cut plating line and a method of fabricating the same. In the BGA package, the plating line is cut to form a predetermined uneven bonding pad using half-etching, thereby increasing the contact area between the bonding pad and a solder ball. The BGA package includes a first external layer having a first circuit pattern and a wire bonding pad pattern wherein a chip is connected to a wire bonding pad using wire bonding. A second external layer includes a second circuit pattern, a cut plating line pattern, and a half-etched uneven solder ball pad pattern. In the second external layer, another chip is mounted on a solder ball pad. An insulating layer having a through hole interposed between the first and second external layers and electrically connects the first and second external layers therethrough.

Abstract: A chip package transmitting slow speed signals via edge connectors and high speed signals by means of through-silicon-vias. The edge connectors are formed in recesses formed in the sidewalls of the package.

Abstract: A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming at least one gate structure over the substrate; forming a plurality of doped regions in the substrate; forming an etch stop layer over the substrate; removing a first portion of the etch stop layer, wherein a second portion of the etch stop layer remains over the plurality of doped regions; forming a hard mask layer over the substrate; removing a first portion of the hard mask layer, wherein a second portion of the hard mask layer remains over the at least one gate structure; and forming a first contact through the second portion of the hard mask layer to the at least one gate structure, and a second contact through the second portion of the etch stop layer to the plurality of doped regions.

Abstract: Metallization contact structures and methods for forming a multiple-layer electrode structure on solar cells include depositing a conductive contact layer on a semiconductor substrate and depositing a metal bearing ink onto a portion of the conductive contact layer, wherein exposed portions of the conductive contact layer are adjacent to the metal bearing ink. The conductive contact layer is patterned by removing exposed portions of the conductive contact layer from the semiconductor substrate. The metal bearing ink is aligned with openings in a dielectric layer of the semiconductor substrate and with unexposed portions of the conductive contact layer. The unexposed portions of the conductive contact layer are interposed between the metal bearing ink and the dielectric layer such that the conductive contact layer pattern is aligned with metal bearing ink. The semiconductor substrate is thermally processed to form a current carrying metal gridline by sintering the metal bearing ink.

Abstract: A mask frame assembly for thin film deposition including a frame having an opening portion and a support portion, and a mask having a deposition area in a position corresponding to the opening portion, wherein the mask includes a first layer including the deposition area and a peripheral portion disposed outside the deposition area and a second layer including a first surface and a second surface opposite to the first surface, at least a part of the first surface of the second layer faces the first layer and contacts the peripheral portion, and the second surface is welded to the support portion of the frame.

Abstract: A manufacturing method of a dual damascene structure is provided. First, a first dielectric layer, a second dielectric layer, and a mask layer are formed. A first trench structure is formed in the mask layer. A via structure is formed in the mask layer, the second dielectric layer, and the first dielectric layer. A portion of the second dielectric layer is then removed, so as to transform the first trench structure into a second trench structure. Here, a bottom of the second trench structure exposes the first dielectric layer.

Abstract: Methods for fabricating a back-end-of-line (BEOL) wiring structure that includes an on-chip inductor and an on-chip capacitor, as well as methods for tuning and fabricating a resonator that includes the on-chip inductor and on-chip capacitor. The fabrication methods generally include forming the on-chip capacitor and on-chip inductor in different metallization levels of the BEOL wiring structure and laterally positioned to be substantially vertical alignment. The on-chip capacitor may serve as a Faraday shield for the on-chip inductor. Optionally, a Faraday shield may be fabricated either between the on-chip capacitor and the on-chip inductor, or between the on-chip capacitor and the substrate. The BEOL wiring structure may include at least one floating electrode capable of being selectively coupled with the directly-connected electrodes of the on-chip capacitor for tuning, during circuit operation, a resonance frequency of an LC resonator that further includes the on-chip inductor.

Abstract: A method of manufacturing a thin film transistor (“TFT”) substrate includes forming a gate insulating film and an active layer on a substrate, forming a data metal layer including a first, second, and third metal layers on the active layer, forming a first photoresist pattern on the data metal layer, dry-etching the third metal layer by using the first photoresist pattern, simultaneously dry-etching the second and first metal layers by using the first photoresist pattern, dry-etching the active layer by using the first photoresist pattern, etching the first photoresist pattern to form a second photoresist pattern by which the channel region is removed and forming a source electrode and a drain electrode by dry-etching the channel region of the data metal layer by using the second photoresist pattern.

Abstract: Methods and associated structures of forming a microelectronic structure are described. Those methods may comprise dissolving a metal precursor in a non-aqueous solvent in a bath; placing a substrate comprising an interconnect opening in the bath, wherein the metal precursor forms a monolayer within the interconnect opening; and placing the substrate in a coreactant mixture, wherein the coreactant reacts with the metal precursor to form a thin barrier monolayer.

Abstract: A storage cell, integrated circuit (IC) chip with one or more storage cells that may be in an array of the storage cells and a method of forming the storage cell and IC. Each storage cell includes a stylus, the tip of which is phase change material. The phase change tip may be sandwiched between an electrode and conductive material, e.g., titanium nitride (TiN), tantalum nitride (TaN) or n-type semiconductor. The phase change layer may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) (GST) layer.

Abstract: A semiconductor device includes a first aerial wiring including a first wiring layer which is formed in an air gap and contains Cu as a main component and a via layer which is electrically connected to the first wiring layer, is formed in an inter-level insulating film containing a preset constituent element and contains Cu as a main component, and a first porous film formed on the first aerial wiring. The semiconductor device further includes a first barrier film which is formed to cover the surface of the first aerial wiring and contains a compound of the preset constituent element and a preset metal element as a main component.

Abstract: A method includes forming a release layer of a semiconductor device being fabricated, where the release layer has a trapezoidal shape. The method also includes forming a cantilever, which has a cantilever arm formed over the release layer. The method further includes removing at least part of the release layer from under the cantilever arm. The release layer could be formed using a photo-resist material. The photo-resist material can be patterned by exposing the photo-resist material using multiple exposures. A first exposure could expose a portion of the photo-resist material, where the exposed portion has substantially vertical sides. A second exposure could give the exposed portion of the photo-resist material slanted sides. A wet etch could be performed to remove the release layer from under the cantilever arm.

Abstract: A structure and method of forming landing pads for through substrate vias in forming stacked semiconductor components are described. In various embodiments, the current invention describes landing pad structures that includes multiple levels of conductive plates connected by vias such that the electrical connection between a through substrate etch and landing pad is independent of the location of the bottom of the through substrate trench.

Abstract: Compositions and methods for forming metal films on semiconductor substrates are disclosed. One of the disclosed methods comprises: heating the semiconductor substrate to obtain a heated semiconductor substrate; exposing the heated semiconductor substrate to a composition containing at least one metal precursor comprising at least one ligand, an excess amount of neutral labile ligands, a supercritical solvent, and optionally at least one source of B, C, N, Si, P, and mixtures thereof; exposing the composition to a reducing agent and/or thermal energy at or near the heated semiconductor substrate; disassociating the at least one ligand from the metal precursor; and forming the metal film while minimizing formation of metal oxides.

Abstract: An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.

Abstract: Disclosed are a semiconductor device and a method for manufacturing the same, capable of improving the performance of a barrier and inhibiting a discontinuous step coverage and an overhang. The semiconductor device includes an interlayer dielectric layer having a via hole disposed on a semiconductor substrate, a first layer disposed in the via hole and including ruthenium (Ru), a second layer disposed on the first layer and including ruthenium oxide (RuO2), and a metal line disposed on the second layer and including a copper material.

Abstract: A memory array having memory cells comprising a diode and an antifuse can be made smaller and programmed at lower voltage by using an antifuse material having a higher dielectric constant and a higher acceleration factor than those of silicon dioxide, and by using a diode having a lower band gap than that of silicon. Such memory arrays can be made to have long operating lifetimes by using the high acceleration factor and lower band gap materials. Antifuse materials having dielectric constants between 5 and 27, for example, hafnium silicon oxynitride or hafnium silicon oxide, are particularly effective. Diode materials with band gaps lower than that of silicon, such as germanium or a silicon-germanium alloy, are particularly effective.

Abstract: Embodiments of the invention describe TiN deposition methods suitable for high volume manufacturing of semiconductor devices on large patterned substrates (wafers). One embodiment describes a chemical vapor deposition (CVD) process using high gas flow rate of a tetrakis(ethylmethylamino) titanium (TEMAT) precursor vapor along with an inert carrier gas at a low process chamber pressure that provides high deposition rate of conformal TiN films with good step coverage in surface reaction limited regime. Other embodiments describe cyclical TiN deposition methods using TEMAT precursor vapor and a nitrogen precursor.

Abstract: An improvement is provided in a manufacturing yield of a semiconductor device including transistors in which gate insulating films have different thicknesses. After a high-breakdown-voltage insulating film is formed over a silicon substrate, a surface of the high-breakdown-voltage insulating film is abraded for a reduction in the thickness thereof so that a middle-breakdown-voltage insulating film is formed to be adjacent to the high-breakdown-voltage insulating film. The high-breakdown-voltage insulating film is formed by a thermal oxidation method so as to extend from an inside of the main surface of the silicon substrate to an outside thereof. The middle-breakdown-voltage insulating film is formed so as to be thinner than the high-breakdown-voltage insulating film.

Abstract: Alternative methods of constructing a vertically offset structure are disclosed. An embodiment includes forming a flexible layer having first and second end portions, an intermediate portion coupling the first and second portions, and upper and lower surfaces. The distance between the upper and lower surfaces at the intermediate portion is less than the distance between the upper and lower surfaces at the first and second end portions. The first end portion is bonded to a base member. The second end portion of the flexible layer is deflected until the second end portion contacts the base member. The second end portion is bonded to the base member.

Abstract: A semiconductor system includes: providing a dielectric layer; providing a conductor in the dielectric layer, the conductor exposed at the top of the dielectric layer; capping the exposed conductor; and modifying the surface of the dielectric layer, modifying the surface of the dielectric layer, wherein modifying the surface includes cleaning conductor ions from the dielectric layer by dissolving the conductor in a low pH solution, dissolving the dielectric layer under the conductor ions, mechanically enhanced cleaning, or chemisorbing a hydrophobic layer on the dielectric layer.

Abstract: A combined wide-image and loop-cutter pattern is provided for both cutting and forming a wide-image section to a hard mask on a substrate formed by sidewall imaging techniques in a reduced number of photolithographic steps. A single mask is formed which provides a wide mask section while additionally providing a mask to protect the critical edges of an underlying hard mask during hard mask etching. After the hard mask is cut into sections, the protective portions of the follow-on mask are removed to expose the critical edges of the underlying hard mask while maintaining shapes necessary for defining wide-image sections. Thus, the hard mask cutting, hard mask critical edge protecting, and large area mask may be formed in a reduced number of steps.

Abstract: A method for fabricating an integrated circuit providing an enlarged contact process window while reducing device size is disclosed. The method comprises providing a substrate including a first region and a second region, the first and second regions having one or more gate structures including a dummy gate layer; removing the dummy gate layer from at least one of the one or more gate structures in the first and second regions to form one or more trenches in the first and second regions; filling the one or more trenches in the first and second regions with a conductive layer; selectively etching back the conductive layer of the one or more gate structures in the second region of the substrate; forming a protective layer over the etched back conductive layer of the one or more gate structures in the second region; and forming one or more contact openings in the first and second regions.

Abstract: Methods of forming a barrier layer for an interconnection structure are provided. In one embodiment, a method for forming an interconnect structure includes providing a substrate having a first conductive layer disposed thereon, incorporating oxygen into an upper portion of the first conductive layer, depositing a first barrier layer on the first conductive layer, and diffusing the oxygen incorporated into the upper portion of the first conductive layer into a lower portion of the first barrier layer. In another embodiment, a method for forming an interconnection structure includes providing a substrate having a first conductive layer disposed thereon, treating an upper surface of the first conductive layer with an oxygen containing gas, depositing a first barrier layer on the treated conductive layer, and depositing a second conductive layer on the first barrier layer while driving a portion of oxygen atoms from the treated conductive layer into the first barrier layer.

Abstract: An approach is provided for semiconductor devices and methods for providing a contact structure. Methods may include forming a gate pattern on a substrate including a device isolation pattern provided to define an active region, the gate pattern crossing over the active region and being disposed on the device isolation pattern, and forming a first doped region and a second doped region in the active region adjacent to opposite sides of the gate pattern, respectively. The methods may include sequentially forming a gate spacer and a sacrificial spacer on both sidewalls of the gate pattern, forming an interlayer dielectric on the entire surface of the substrate, planarizing the interlayer dielectric to expose the gate spacer and the sacrificial spacer, removing a portion of the sacrificial spacer to form a groove to expose the first doped region, and forming a contact structure in the groove.

Abstract: A method of making an integrated circuit includes providing a low-k dielectric layer on a substrate, the low-k dielectric layer including or adjacent to a plurality of conductive features; patterning the low-k dielectric layer to form trenches; patterning the low-k dielectric layer to form conductive vias and dummy vias, wherein each of the conductive vias is aligned with at least one of the plurality of the conductive features and at least one of the trenches, and each of the dummy vias is a distance above the plurality of conductive features; filling the trenches, conductive vias, and dummy vias using one or more conductive materials; and planarizing the conductive material(s).

Abstract: The invention is concerned with a method for manufacturing a local wiring in a semiconductor device, comprising the manufacturing of at least two electrically conducting structures essentially in the same horizontal level in a layered stack on a substrate, the at least two electrically conducting structures being separated by a gap filled with at least one dielectric material, the gap being electrically bridged by conductive material, to form at least one contact element electrically connecting the at least two electrically conducting structures, whereby at least one contact element is produced in a single lithographic step.

Abstract: A semiconductor device and method for manufacturing. One embodiment provides a semiconductor device including an active cell region and a gate pad region. A conductive gate layer is arranged in the active cell region and a conductive resistor layer is arranged in the gate pad region. The resistor layer includes a resistor region which includes a grid-like pattern of openings formed in the resistor layer. A gate pad metallization is arranged at least partially above the resistor layer and in electrical contact with the resistor layer. An electrical connection is formed between the gate layer and the gate pad metallization, wherein the electrical connection includes the resistor region.

Abstract: A method of forming contacts between at least one metallic layer and at least one semiconductor substrate through at least one layer of dielectric in a semiconductor device. The semiconductor device includes, on at least one base face of the semiconductor substrate, the dielectric layer. The metallic layer is stacked on the dielectric layer. The heated ends of plural protruding elements assembled on a support are brought into contact with the metallic layer simultaneously, thereby creating zones of melted metal under the heated ends of the protruding elements. The melted metal traverses the dielectric and amalgamates with the semiconductor of the substrate at the level of the zones of melted metal, thereby creating the contacts.

Abstract: A semiconductor device and a method for fabricating the same that includes a drain contact that can prevent bridging between contact metals in metal contact line (M1C) processes. The method includes forming a contact hole extending through an interlayer dielectric film in a space between respective gate electrodes to expose an undercut region, filling the contact hole and the undercut region with a photosensitive material, removing the photosensitive material from the contact hole and then forming a drain contact in the contact hole.

Abstract: An insulating film on a semiconductor substrate has a first titanium nitride film, an aluminum film, and a second titanium nitride film formed thereon, and an insulating film is formed so as to cover a lower electrode wiring. Then, the insulating film is dry-etched anisotropically so that the insulating film on the lower electrode wiring is removed, and a portion of the insulating film on the lower electrode wiring is left as a sidewall. A deposit deposited during the etching of the insulating film on the lower electrode wiring is removed by radical etching without using ion bombardment. The deposit contains Ti that is a metal element forming the second titanium nitride film. Subsequently, the second titanium nitride film is nitrided through ammonium plasma, and an insulating film to cover the lower electrode wiring is formed.

Abstract: Multi-functional electronic switching and current control device comprising a chalcogenide material. The devices include a load terminal, a reference terminal and a control terminal. Application of a control signal to the control terminal permits the device to function in one or more of the following modes reversibly: (1) a gain mode in which gain is induced in the current passing between the load and reference terminals; (2) a conductivity modulation mode in which the conductivity of the chalcogenide material between the load and reference terminals is modulated; (3) a current modulation mode in which the current or current density between the load and reference terminals is modulated; and/or (4) a threshold modulation mode in which the voltage required to switch the chalcogenide material between the load and reference terminals from a resistive state to a conductive state is modulated. The devices may be used as interconnection devices or signal providing devices in circuits and networks.

Abstract: A semiconductor device capable of preventing an electrical short between contacts and their adjacent contact pads and a method of manufacturing the same are provided. A first interlayer insulating layer is formed on the semiconductor substrate including the active region. Contact pads pass through the first interlayer insulating layer and contact with the active region. Contacts are formed on the contact pads and are connected to a conductive layer disposed above the contacts. The contact pads have a height lower than a top surface of the first interlayer insulating layer such that the contact pads have smaller thickness than the first interlayer insulating layer.

Abstract: A semiconductor device having a VIA hole without disconnection caused by step is achieved. A semiconductor device and its manufacturing method, the semiconductor device comprising: a semi-insulating substrate 11 in which an electrode (12) is formed on a surface (11a) of one side and in which an aperture (11c) passed through from the surface 11a of one side to a surface (11b) of another side is formed; and a conductive layer (17) formed in an inner surface of the aperture (11c), and electrically connected with the electrode (12); wherein the aperture (11c) has a tapered region (11d) where an inside diameter of a part located in the surface (11b) of another side is larger than an inside diameter of a part located in the surface (11a) of one side.

Abstract: A method for providing metallization upon a semiconductor substrate utilizing a stencil having at least one aperture extending from the contact side to the fill side, the contact side of the stencil being substantially flat and forming a sharp edge with a wall of the at least one aperture, the at least one aperture being tapered such that an area of a cross-section of the at least one aperture at the fill side is larger than an area of the cross-section of the at least one aperture at the contact side. A method of forming a stencil for depositing metallization lines on a semiconductor substrate is also disclosed.

Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case (particularly in the latter), capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material (e.g.

Abstract: Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.

Abstract: A method of manufacturing a semiconductor device, includes steps of forming an organic insulating film over a semiconductor substrate, irradiating an electron beam to a surface of the organic insulating film, forming recesses in the organic insulating film, forming a conductive material over the organic insulating film and in the recesses, and removing the conductive material on the organic insulating film by a polishing to expose the surface of the organic insulating film and to leave the conductive material buried in recesses of the organic insulating film.

Abstract: Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.

Abstract: A method of making a semiconductor device includes forming at least one layer over a substrate, forming at least two spaced apart features of imagable material over the at least one layer, forming sidewall spacers on the at least two features and filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature. The method also includes selectively removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the at least one layer using the first feature, the filler feature and the second feature as a mask.

Abstract: An insulation layer including a landing plug is formed over a substrate. An amorphous carbon hard mask is formed over a certain portion of the insulation layer. The insulation layer is etched using the amorphous carbon hard mask to form a storage node contact hole exposing the landing plug. A conductive material is formed in the storage node contact hole to form a storage node contact plug. Other embodiments are also described.