Abstract: A vertical memory device includes a channel, a ground selection line (GSL), word lines, a string selection line (SSL), and a contact. The channel includes a vertical portion and a horizontal portion. The vertical portion extends in a first direction substantially perpendicular to a top surface of a substrate, and the horizontal portion is connected to the vertical portion and parallel to the top surface of the substrate. The GSL, the word lines and the SSL are formed on a sidewall of the vertical portion of the channel sequentially in the first direction, and are spaced apart from each other. The contact is on the substrate and electrically connected to the horizontal portion of the channel.

Abstract: The disclosure provides a customized manufacturing method for an optoelectrical device. The customized manufacturing method comprises the steps of providing a manufacturing flow including a front-end flow, a customized module subsequent to the front-end flow, and a pause step between the front-end flow and the customized module, processing a predetermined amount of semi-manufactured products queued at the pause step, tuning the customized module in accordance with a customer's request, and processing the semi-manufactured products by the tuned customized module to fulfill the customer's request.

Abstract: A method of forming an integrated circuit structure includes forming a first and a second plurality of tracks parallel to a first direction and on a wafer representation. The first and the second plurality of tracks are allocated in an alternating pattern. A first plurality of patterns is laid out on the first plurality of tracks and not on the second plurality of tracks. A second plurality of patterns is laid out on the second plurality of tracks and not on the first plurality of tracks. The first plurality of patterns is extended in the first direction and in a second direction perpendicular to the first direction, so that each of the second plurality of patterns is surrounded by portions of the first plurality of patterns, and substantially none of neighboring ones of the first plurality of patterns on the wafer representation have spacings greater than a pre-determined spacing.

Abstract: A method of making a semiconductor device includes forming a layer over a substrate, forming a plurality of spaced apart features of imagable material over the layer, forming sidewall spacers on the plurality of features and filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature. The method also includes removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the layer using the first feature, the filler feature and the second feature as a mask.

Abstract: A multilayer interconnection substrate is disclosed that includes a multilayer interconnection layer having at least a first interconnection layer and a second interconnection layer stacked with an insulating layer provided therebetween, and a connection via configured to electrically connect the first interconnection layer and the second interconnection layer. The connection via includes an internal conductor and a metal film covering the internal conductor. The internal conductor is an aggregate of metal particles.

Abstract: Embodiments of the invention relate to a silicon semiconductor device, and a conductive paste for use in the front side of a solar cell device.

Abstract: The invention relates to a method for producing vertical electrical connections in semiconductor wafers, the method including the following steps: application of a protective resist to the wafer front side; patterning of the protective resist such that the contacts to be connected to the wafer rear side become free; laser drilling of passage holes at the contact connection locations from the wafer rear side through the semiconductor substrate, the active layers and the contacts to be connected on the wafer front side; cleaning of the wafer; application of a plating base to the wafer rear side and into the laser-drilled passage holes; application of gold by electrodeposition onto the metallized wafer rear side and the passage holes; resist stripping of the protective resist; and application of an antiwetting layer in the region of the entrance openings of the passage holes at the wafer rear side.

Abstract: A semiconductor device includes: element formation regions each including a cell region where a semiconductor element is formed, a termination trench region; and a dicing line region including a groove separating the element formation regions. The termination trench region includes four trenches surrounding four sides of the cell region. Two of the trenches extend longitudinally in parallel to an X direction and the other two trenches extend longitudinally in parallel to a Y direction perpendicular to the X direction. The termination trench region is perpendicularly in contact with longitudinal sides of the dicing line region while the trenches extending longitudinally in parallel to the X direction intersect the trenches extending longitudinally in parallel to the Y direction at four corners of the element formation region, while vertical sections of the termination trench region in a cross direction are opened in four side surfaces of the element formation region.

Abstract: A method for manufacturing a semiconductor device includes the steps of forming a plug on a semiconductor substrate, forming an insulation layer over the semiconductor substrate having the plug formed thereon, defining a line type trench through a first etching of a partial thickness of the insulation layer; and defining a contact hole through a second etching of a portion of the insulation layer corresponding to the bottom of the trench so as to expose the plug.

Abstract: Photoelectrochemical cells and methods are provided, in particular, to the functionalization of semiconductor surfaces such that its semiconducting and light generating properties are maintained and the surface becomes stable in wet environments. In particular the preferred embodiments relate to unstable semiconductor materials which have photocurrent generating properties, and to methods for the functionalization of surfaces with metallic carbon nanotubes (CNTs).

Abstract: Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate.

Abstract: A method of manufacturing a semiconductor device, including: forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body formed of stacked layers of a plurality of interlayer insulating films lower in dielectric constant than a SiO2 film and including the multilayer interconnection structure; forming a groove in the layered body between the moisture resistant ring and a scribe line, the groove reaching a surface of a semiconductor substrate; forming a film including Si and C as principal components and covering sidewall surfaces and a bottom surface of the groove; and forming a protection film on the film along the sidewall surfaces and the bottom surface of the groove.

Abstract: It is an object of the invention to provide a lightweight semiconductor device having a highly reliable sealing structure which can prevent ingress of impurities such as moisture that deteriorate element characteristics, and a method of manufacturing thereof. A protective film having superior gas barrier properties (which is a protective film that is likely to damage an element if the protective film is formed on the element directly) is previously formed on a heat-resistant substrate other than a substrate with the element formed thereon. The protective film is peeled off from the heat-resistant substrate, and transferred over the substrate with the element formed thereon so as to seal the element.

Abstract: A switchable electronic device comprises a hole blocking layer and a layer comprising a conductive material between first and second electrodes, wherein the conductivity of the device may be irreversibly switched upon application of a current having a current density of less than or equal to 100 A cm?2 to a conductivity at least 100 times lower than the conductivity of the device before switching. The conductive material is a doped organic material such as doped optionally substituted poly(ethylene dioxythiophene).

Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a first conductive layer over a substrate. The first conductive layer has a top surface and sidewalls, wherein the first conductive layer comprises an overhang of a non-conductive material along the sidewalls. The method further includes forming an insulating layer on the first conductive layer, and forming a sacrificial layer over the insulating layer and the overhang of the first conductive layer. The sacrificial layer is partially removed wherein a residue of the sacrificial layer remains beneath the overhang, and a second conductive layer is formed on the insulating layer.

Abstract: Methods for forming a dense dielectric layer over the surface of an opening in a porous inter-layer dielectric having an ultra-low dielectric constant are disclosed. The disclosure provides methods for exposing the sidewall surface and the bottom surface of the opening to a plurality of substantially parallel ultra-violet (UV) radiation rays to form a dense dielectric layer having a substantially uniform thickness over both the sidewall surface and the bottom surface.

Abstract: The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.

Abstract: A pressure sensor includes a sense element port, a support ring and a plurality of interference fit slits to provide a flexible interference fit between the sense element port and the support ring to form a substantially flush lap joint. The sensor also includes an electronics board inside the support ring and attached to planar mounting tabs which provide a stable mounting. Gel flow barriers protect electronics board features from unwanted non-conductive gel. Double-ended symmetrical, tapered contact springs provide manufacturing cost savings and contribute to improved alignment of an interface connector of the sensor.

Abstract: A method of forming an interconnect joint includes providing a first metal layer (210, 310), providing a film (220, 320) including metal particles (221, 321) and organic molecules (222, 322), placing the film over the first metal layer, placing a second metal layer (230, 330) over the film, and sintering the metal particles such that the organic molecules degrade and the first metal layer and the second metal layer are joined together.

Abstract: A method of forming dual damascene features in a porous low-k dielectric layer is provided. Vias are formed in the porous low-k dielectric layer. An organic planarization layer is formed over the porous low-k dielectric layer, wherein the organic layer fills the vias. A photoresist mask is formed over the organic planarization layer. Features are etched into the organic planarization layer comprising providing a CO2 containing etch gas and forming a plasma from the CO2 containing etch gas, which etches the organic planarization layer. Trenches are etched into the porous low-k dielectric layer using the organic planarization layer as a mask. The organic planarization layer is stripped.

Abstract: A first film containing a first metal material having a diffusion preventing function for copper, a second film containing oxygen-contained copper film, a third film containing copper and a second metal material which exhibits a diffusion preventing function for copper by bonding with oxygen, and a fourth film of copper as the main material are formed in an opening formed in an insulating film, and then a barrier layer containing the first metal material, the second metal material and oxygen is formed by thermal processing between the insulating film and the fourth film.

Abstract: A method for fabricating a semiconductor device includes forming an interlayer dielectric layer over a substrate; forming a dual storage node contact plug to be buried in the interlayer dielectric layer, forming a first damascene pattern to isolate the dual storage node contact plug, forming a protective layer pattern inside the first damascene pattern, etching the interlayer dielectric layer to form a second damascene pattern to be coupled to the first damascene pattern, and forming bit lines inside the first and second damascene patterns.

Abstract: The embodiments generally relate to methods of making semiconductor devices, and more particularly, to methods for making semiconductor pillar structures and increasing array feature pattern density using selective or directional gap fill. The technique has application to a variety of materials and can be applied to making monolithic two or three-dimensional memory arrays.

Abstract: A method for manufacturing a semiconductor device. The method includes forming an energy cured resin layer on a semiconductor substrate having an electrode pad and a passivation film; fusing the resin layer so that fusion of a surface section is progressed more than of a central section by a first energy supply processing; forming a resin boss by curing and shrinking the resin layer by a second energy supply processing; and forming an electrical conducting layer which is electrically connected to the electrode pad and passes over the resin boss.

Abstract: An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first metallization layer over the substrate and electrically connected to the substrate; forming a viabar or a via group over the first metallization layer; and forming a second metallization layer over the first metallization layer and electrically connected to the first metallization layer through either the viabar or the via group.

Abstract: A method for semiconductor fabrication using a trench first metal hard mask (TFMHM) process for damascene structures includes forming a secondary metal hard mask layer above a first metal hard mask layer after trench opening for the via (and trench) etching. The secondary metal hard mask layer is formed of metal material substantially resistant to the etching process which enables via etching to self-align (using an edge of the secondary metal mask layer). In one embodiment, the secondary metal mask layer is formed using an electroless deposition process, and may include nickel (Ni), cobalt (Co), gold, (Au), palladium (Pd), cadmium (Cd) silver (Ag), ruthenium (Ru), and alloys and/or combinations thereof. Because the first metal hard mask is usually formed of TiN, the trench and via etching process removes a significant amount of the TiN layer. Utilization of the secondary metal hard mask to protect the first metal hard mask layer further enables a reduction in the thickness of the first metal hard mask layer.

Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface-electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.

Abstract: (a) A recess is formed through an insulating film formed over a semiconductor substrate. (b) After the recess is formed, a temperature of the substrate is raised to 300° C. or higher at a temperature rising rate of 10° C./s or slower and a first degassing process is executed. (c) After the first degassing process, a conductive film is deposited on the insulating film, the conductive film being embedded in the recess. (d) The deposited conductive film is polished until the insulating film is exposed. It is possible to suppress occurrence of defects during CMP to be performed after a conductive member is deposited on the surface of the insulating film having a recess formed therethrough.

Abstract: Methods of manufacturing semiconductor devices are provided in which a first contact plug is formed on a first active region in a substrate and a second contact plug is formed on a second active region in the substrate. A height of an upper surface of the second contact plug from the substrate is greater than a height of an upper surface of the first contact plug from the substrate. A third contact plug is formed on the second contact plug. A first spacer is formed on a side surface of the third contact plug. A third interlayer insulation layer is formed that covers the third contact plug. The third interlayer insulation layer is patterned to form a third opening that exposes the first contact plug. A fourth contact plug is formed in the third opening that is electrically connected to the first contact plug.

Abstract: There is provided a method of fabricating an electronic device including flip-chip mounting a device chip on a substrate, and supplying solder between adjacent device chips by supplying the solder on the device chips and applying heat and pressure on the solder, and a contact angle of the device chip and the solder is greater than 90° with the solder melted.

Abstract: There are provided an ohmic electrode, which includes a contact layer made of an Al alloy and formed on a nitride-based semiconductor layer functioning as a light emitting layer, a reflective layer made of Ag metal, formed on the contact layer and having some particles in-diffused to the semiconductor layer, and a protective layer formed on the reflective layer to restrain out-diffusion of the reflective layer; a method of forming the ohmic electrode; and a semiconductor light emitting element having the ohmic electrode. The present invention has strong adhesive strength and low contact resistance since the reflective layer and the light emitting layer directly form an ohmic contact due to the interface reaction during heat treatment, and the present invention has high light reflectance and excellent thermal stability since the contact layer and the protective layer restrain out-diffusion of the reflective layer during heat treatment.

Abstract: An electronic device including a first region belonging to a semiconductor device having a first surface; a second region having a second surface; and an adhesion layer, set between the first and second regions, including first fibrils each having respective first and second ends. The first fibrils extend between the first and second surfaces and are fixed in a chemico-physical way to the first and second surfaces at the respective first and second ends.

Abstract: A semiconductor element includes a semiconductor layer, an electrode, an adhesion layer, and an insulating layer. The electrode is disposed over the semiconductor layer and has a first upper surface and a second upper surface disposed further away from the semiconductor layer than the first upper surface. The adhesion layer is disposed on the first upper surface of the electrode so that the second upper surface of the electrode is disposed further away from the semiconductor layer than an upper surface of the adhesion layer. The insulating layer covers from the upper surface of the adhesion layer to the semiconductor layer.

Abstract: A method of making a semiconductor device includes forming at least one layer over a substrate, forming at least two spaced apart features of imagable material over the at least one layer, forming sidewall spacers on the at least two features and filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature. The method also includes selectively removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the at least one layer using the first feature, the filler feature and the second feature as a mask.

Abstract: A manufacturing method for a silicon carbide semiconductor device is disclosed. It includes an etching method in which an Al film and Ni film are laid on an SiC wafer in this order and wet-etched, whereby a two-layer etching mask is formed in which Ni film portions overhang Al film portions. Mesa grooves are formed by dry etching by using this etching mask.

Abstract: A method for fabricating an FET device is disclosed. The method includes Fin-FET devices with fins that are composed of a first material, and then merged together by epitaxial deposition of a second material. The fins are vertically recesses using a selective etch. A continuous silicide layer is formed over the increased surface areas of the first material and the second material, leading to smaller resistance. A stress liner overlaying the FET device is afterwards deposited. An FET device is also disclosed, which FET device includes a plurality of Fin-FET devices, the fins of which are composed of a first material. The FET device includes a second material, which is epitaxially merging the fins. The fins are vertically recessed relative to an upper surface of the second material. The FET device furthermore includes a continuous silicide layer formed over the fins and over the second material, and a stress liner covering the device.

Abstract: This invention provides a semiconductor device having a semiconductor element that has low-resistance and a stable contact connection, even when the wiring is connected from the side of the single-crystal silicon layer on which the impurity concentration is lower. This invention provides a semiconductor device comprising, on a substrate, a semiconductor device having a single-crystal semiconductor film and a wiring connected to the single-crystal semiconductor film, and in the single-crystal semiconductor film, an impurity concentration on one surface side is different from an impurity concentration on another surface side, the wiring being connected to the surface side on which the impurity concentration is lower, the resistivity of a region of the single-crystal semiconductor film to which the wiring is connected being no less than 1 ??cm and no more than 0.01 ?cm.

Abstract: The present disclosure provides methods for forming semiconductor devices with laser-etched vias and apparatus including the same. In one embodiment, a method of fabricating a semiconductor device includes providing a substrate having a frontside and a backside, and providing a layer above the frontside of the substrate, the layer having a different composition from the substrate. The method further includes controlling a laser power and a laser pulse number to laser etch an opening through the layer and at least a portion of the frontside of the substrate, filling the opening with a conductive material to form a via, removing a portion of the backside of the substrate to expose the via, and electrically coupling a first element to a second element with the via. A semiconductor device fabricated by such a method is also disclosed.

Abstract: An object is to provide an insulating film for a semiconductor device which has characteristics of a low permittivity, a low leakage current, and a high mechanical strength, undergoes less change in these characteristics with the elapse of time, and has an excellent water resistance, as well as to provide a process and an apparatus for producing the insulating film for a semiconductor device, a semiconductor device, and a process for producing the semiconductor device.

Abstract: Various semiconductor devices and methods of testing such devices are disclosed. In one aspect, a method of manufacturing is provided that includes forming a bore from a backside of a semiconductor chip through a buried insulating layer and to a semiconductor device layer of the semiconductor chip. A conductor structure is formed in the bore to establish an electrically conductive pathway between the semiconductor device layer and the conductor structure. The conductor structure may provide a diagnostic pathway.

Abstract: An electronic component comprises a plurality of layers at least two of which comprise predominantly organic functional materials with improved through-plating through certain of the layers. The through-plating is formed in one embodiment by a disruption element on a first lower layer which results in a void in the subsequently applied layers, which void is filled with a material which may be conductive to form the through plating. In a second embodiment, the through plating is formed on the first lower layer prior to the subsequent application of the other layers, in the form of a free-standing truncated frusto-conical raised portion, and forms a disruption or non-welting element for the subsequently applied other layers, formed on the first lower layer and which are engaged with and surround the through plating after their application.

Abstract: Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform and precise deposition of metal-containing films on semiconductor substrates as well as the uniform and precise removal of materials from such substrates. In one embodiment, the process includes, providing a supercritical fluid containing at least one reactant, the supercritical fluid being maintained at above its critical point, exposing at least a portion of the surface of the semiconductor substrate to the supercritical fluid, applying acoustic energy, and reacting the at least one reactant to cause a change in at least a portion of the surface of the semiconductor substrate.

Abstract: A method of manufacturing a semiconductor apparatus includes forming back surface electrode 4 on back surface of semiconductor wafer 20, that bends convexly toward the front surface side due to back surface electrode 4 being formed; treating the back surface with a plasma for removing the deposits on the back surface; sticking removable adhesive tape 23 to the back surface along the warp thereof for maintaining the bending state of semiconductor wafer 20 after the step of sticking; electrolessly plating to form film 26 on the front surface of semiconductor wafer 20; peeling off removable adhesive tape 23; cutting out semiconductor chips; and mounting the semiconductor chip by bonding with a solder for manufacturing a semiconductor apparatus. The manufacturing method prevents external appearance anomalies from occurring on the back surface electrode, improves the reliability, and allows manufacture of the semiconductor apparatuses with a high throughput of non-defective products.

Abstract: Methods of forming a roughened metal surface on a substrate are provided, along with structures comprising such roughened surfaces. In preferred embodiments roughened surfaces are formed by selectively depositing metal or metal oxide on a substrate surface to form discrete, three-dimensional islands. Selective deposition may be obtained, for example, by modifying process conditions to cause metal agglomeration or by treating the substrate surface to provide a limited number of discontinuous reactive sites. The roughened metal surface may be used, for example, in the manufacture of integrated circuits.

Abstract: The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.

Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case (particularly in the latter), capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material (e.g.

Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.

Abstract: A semiconductor device package and a method of fabricating the same are disclosed. The semiconductor device package includes a substrate, a first chip, a jumper chip, a plurality of first bonding wires and a plurality of second bonding wires. The substrate has a plurality of contact pads. The first chip is disposed and electrically connected to the substrate via the first bonding wires. The jumper chip is disposed on the first chip and has a plurality of metal pads. Each of the metal pads is electrically connected to two contact pads of the substrate via two second bonding wires, respectively.

Abstract: An electronic device, a package including the same, and a method of fabricating the package, the electronic device including a substrate having an operation structure therein; a first passivation layer on a first side of the substrate; and first conductive patterns on a second side of the substrate, the first conductive patterns being electrically connected to the operation structure, wherein the first passivation layer has a higher flexibility than the substrate when the substrate and the first passivation layer are bent.

Abstract: Etching is performed on an insulating layer 23 and a conductive layer 32 with a photoresist 41 as the mask, to form an opening 51 in the conductive layer 32. After removing the photoresist 41, another insulating layer 24 is formed all over, which is etched back so as to expose a surface of a conductive layer 31, to thereby cover the inner wall of the opening 51. Then etching is performed on the conductive layer 31 with the latter insulating layer 24 as the mask, so as to form another opening 52 in the conductive layer 31. Then still another insulating layer 25 is formed all over, which is then etched back so as to expose a surface of the conductive layer 32, to thereby fill the opening 52 with the last formed insulating layer 25.