To Form Insulating Layer Thereon, E.g., For Masking Or By Using Photolithographic Technique (epo) Patents (Class 257/E21.24)

  • Patent number: 8536073
    Abstract: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about ?600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: September 17, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Vishwanathan Rangarajan, George Andrew Antonelli, Ananda Banerji, Bart Van Schravendijk
  • Patent number: 8524569
    Abstract: In a method of forming an isolation layer, first and second trenches are formed on a substrate. The first and the second trenches have first and second widths, respectively, and the second width is greater than the first width. A second isolation layer pattern partially fills the second trench. A first isolation layer pattern and the third isolation layer pattern are formed. The first isolation layer pattern fills the first trench, and the third isolation layer pattern is formed on the second isolation layer pattern and fills a remaining portion of the second trench.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: September 3, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Hyuk Kang, Jung-Won Lee, Bo-Un Yoon, Kun-Tack Lee
  • Publication number: 20130224964
    Abstract: A method of forming a dielectric film having Si—C bonds on a semiconductor substrate by atomic layer deposition (ALD), includes: (i) adsorbing a precursor on a surface of a substrate; (ii) reacting the adsorbed precursor and a reactant gas on the surface; and (iii) repeating steps (i) and (ii) to form a dielectric film having at least Si—C bonds on the substrate. The precursor has a Si—C—Si bond in its molecule, and the reactant gas is oxygen-free and halogen-free and is constituted by at least a rare gas.
    Type: Application
    Filed: February 28, 2012
    Publication date: August 29, 2013
    Applicant: ASM IP HOLDING B.V.
    Inventors: Atsuki Fukazawa, Noboru Takamure
  • Publication number: 20130224952
    Abstract: An apparatus for and a method of forming a semiconductor structure is provided. The apparatus includes a substrate holder that maintains a substrate such that the processing surface is curved, such as a convex or a concave shape. The substrate is held in place using point contacts, a plurality of continuous contacts extending partially around the substrate, and/or a continuous ring extending completely around the substrate. The processing may include, for example, forming source/drain regions, channel regions, silicides, stress memorization layers, or the like.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 29, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Ming Chang, Wen-Huei Guo, Chih-Hao Chang, Shou-Zen Chang, Clement Hsingjen Wann, Tung Ying Lee, Cheng-Long Chen, Jui-Chien Huang
  • Publication number: 20130217155
    Abstract: According to one embodiment, a pattern forming method using a template containing a pattern that has at least one recess section or protrusion section to transfer the shape of the pattern to a resin layer on a substrate, is provided. The method includes a process for coating the resin on the substrate, a process for making the hardness of the first portion as a portion of the resin higher than the hardness of the second portion as the portion other than the first portion, and a process in which the portion other than the pattern of the template makes contact with the first portion, in a state where a gap is maintained between the template and the resin, the shape of the pattern is transferred to the second portion, and the resin is cured. Embodiments of an apparatus for pattern forming are also provided.
    Type: Application
    Filed: September 7, 2012
    Publication date: August 22, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuya Fukuhara, Masayuki Hatano
  • Publication number: 20130217217
    Abstract: According to one embodiment, a pattern forming method is disclosed. A resist pattern having a top surface is formed pattern on a substrate. A coating film having a first thickness distribution is formed on the substrate. The coating film covers the resist pattern. The coating film is thinned to expose the top surface of the resist pattern. The first thickness distribution is changed into a second thickness distribution which is more uniform than the first thickness distribution. The resist pattern is removed without removing the coating film. A pattern is formed in the substrate by processing the substrate by using the coating film as a mask.
    Type: Application
    Filed: September 5, 2012
    Publication date: August 22, 2013
    Inventors: Katsutoshi Kobayashi, Daisuke Kawamura
  • Publication number: 20130210241
    Abstract: A method of depositing a film on a substrate surface includes providing a substrate in a reaction chamber; selecting a silicon-containing reactant from a precursor group consisting of di-tert-butyl diazidosilane, bis(ethylmethylamido)silane, bis(diisopropylamino)silane, bis(tert-butylhydrazido)diethylsilane, tris(dimethylamido) silylazide, tris(dimethylamido)silylamide, ethylsilicon triazide, diisopropylaminosilane, and hexakis(dimethylamido)disilazane; introducing the silicon-containing reactant in vapor phase into the reaction chamber under conditions allowing the silicon-containing reactant to adsorb onto the substrate surface; introducing a second reactant in vapor phase into the reaction chamber while the silicon-containing reactant is adsorbed on the substrate surface, and wherein the second reactant is introduced without first sweeping the silicon-containing reactant out of the reaction chamber; and exposing the substrate surface to plasma to drive a reaction between the silicon-containing reactant and
    Type: Application
    Filed: March 1, 2012
    Publication date: August 15, 2013
    Applicant: Novellus Systems Inc.
    Inventors: Adrien LaVoie, Mark J. Saly, Daniel Moser, Rajesh Odedra, Ravi Kanjolia
  • Patent number: 8507389
    Abstract: Methods for forming a dielectric layer on a substrate are provided herein. In some embodiments a method for forming a dielectric layer on a substrate may include exposing the substrate to a first source gas comprising a silicon precursor and an oxidizer for a first period of time to form a first layer comprising silicon and oxygen; and exposing the substrate to a second source gas comprising a metal precursor and the silicon precursor for a second period of time to form a second layer comprising silicon and a metal, where in the first layer and the second layer form the dielectric layer.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: August 13, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Lucien Date, Paul William Turnbull
  • Publication number: 20130203266
    Abstract: Disclosed herein are various methods of forming metal nitride layers on various types of semiconductor devices. In one example, the method includes forming a layer of insulating material above a semiconducting substrate, performing a physical vapor deposition process to form a metal nitride layer above the layer of insulating material, wherein the metal nitride layer has an intrinsic as-deposited stress level, and performing at least one process operation on the metal nitride layer to reduce a magnitude of the intrinsic as-deposited stress level in the metal nitride layer.
    Type: Application
    Filed: February 2, 2012
    Publication date: August 8, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Bernd Hintze, Frank Koschinsky
  • Patent number: 8501633
    Abstract: A substrate structure is produced by forming a first material layer on a substrate having a recess, removing the first material layer from the portion of the substrate except for the recess using a second material that reacts with the first material, and forming a deposition film from the first material layer using a third material that reacts with the first material. A method of manufacturing a device may include the method of forming a substrate structure.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: August 6, 2013
    Assignee: Synos Technology, Inc.
    Inventor: Sang In Lee
  • Patent number: 8502355
    Abstract: An overlay vernier mask pattern of a semiconductor device includes a first overlay vernier mask pattern having a first opening for exposing a first area of a layer to be etched on a substrate and a second opening for exposing a second area spaced apart from the first area, and a second overlay vernier mask pattern aligned on the first overlay vernier mask pattern and the layer to be etched, and having an opening for exposing the second opening while exposing a portion of the layer to be etched in the first area.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: August 6, 2013
    Assignee: SK Hynix Inc.
    Inventor: Joon Seuk Lee
  • Publication number: 20130193565
    Abstract: Provided is a method for creating a mask blank that include a stop layer. The stop layer is optically compatible and process compatible with other layers included as part of the mask blanks. Such blanks may include EUV, phase-shifting, or OMOG masks. The stop layer includes molybdenum, silicon, and nitride in a proportion that allows for compatibility and aids in detection by a residual gas analyzer. Provided is also a method for the patterning of mask blanks with a stop layer, particularly the method for removing semi-transparent residue defects that may occur due to problems in prior mask creation steps. The method involves the detect of included materials with a residual gas analyzer. Provided is also a mask blank structure which incorporates the compatible stop layer.
    Type: Application
    Filed: January 31, 2012
    Publication date: August 1, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen, Boming Hsu, Tran-Hui Shen
  • Publication number: 20130189851
    Abstract: The present disclosure relates to a guiding element for guiding gas flow within a chamber. The guiding element includes a structure, one or more inlets, an outlet, and a transportation region. The one or more inlets are formed on a first side of the structure. The inlets have inlet sizes selected according to a removal rate and to mitigate gas flow variations within the chamber. The outlet is on a second side of the structure, opposite the first side of the structure. The outlet has an outlet size selected according to the removal rate. The transportation region is within the structure and couples or connects the inlets to the outlet.
    Type: Application
    Filed: January 20, 2012
    Publication date: July 25, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: You-Hua Chou, Chih-Tsung Lee, Chia-Ho Chen, Chin-Hsiang Lin
  • Publication number: 20130183832
    Abstract: Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections (OPCs) for semiconductor applications is provided. A method for the near-neighbor trimming includes adding one or more hole shapes onto a semiconductor design layout comprising a plurality of design shapes. The method further includes trimming adjacent ones of the plurality of which are covered by the one or more hole shapes.
    Type: Application
    Filed: January 18, 2012
    Publication date: July 18, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Howard S. Landis
  • Patent number: 8486791
    Abstract: Technology is described herein for manufacturing a three-dimensional 3D stacked memory structure having multiple layers of single crystal silicon or other semiconductor. The multiple layers of single crystal semiconductor are suitable for implementing multiple levels of high performance memory cells.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: July 16, 2013
    Assignee: Macronix International Co., Ltd.
    Inventor: Hang-Ting Lue
  • Patent number: 8486840
    Abstract: A method includes making a target feature of an integrated circuit by providing a main layer over a substrate, depositing a first mask layer over the main layer, patterning the first mask layer, forming sidewall spacers with a width (w) in adjoining sidewalls of the patterned first mask layer and exposing a top area of the patterned first mask layer, selectively removing the first mask layer and exposing a portion of the main layer between the sidewall spacers, depositing a second mask layer over the main layer between the sidewall spacers, selectively removing the sidewall spacers to form an opening and exposing another portion of the main layer in the opening, etching the main layer through the opening to form the target feature.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: July 16, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 8486831
    Abstract: A miniaturized semiconductor device is provided by reducing the design thickness of a wiring line protecting film covering the surface of a wiring layer, and reducing the distance between the wiring layer and via plugs formed by a self-aligning process. Dummy mask layers extending in the same layout pattern as the wiring layer is formed above the wiring layer covered with a protecting film composed of a cap layer and side wall layers. In the self-aligning process for forming via plugs in a self-aligned manner with the wiring layer and its protecting film, the thickness of the cap layer is reduced and the design interval between the via plugs is reduced, whereby the miniaturization of the semiconductor device is achieved.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: July 16, 2013
    Assignee: Elpida Memory, Inc
    Inventor: Hirotaka Kobayashi
  • Publication number: 20130175697
    Abstract: A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.
    Type: Application
    Filed: January 5, 2012
    Publication date: July 11, 2013
    Applicant: International Business Machines Corporation
    Inventors: Son Van Nguyen, Griselda Bonilla, Alfred Grill, Thomas J. Haigh, JR., Satyanarayana V. Nitta
  • Publication number: 20130175665
    Abstract: A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %.
    Type: Application
    Filed: January 6, 2012
    Publication date: July 11, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael P. Chudzik, Bachir Dirahoui, Rishikesh Krishnan, Siddarth A. Krishnan, Oh-jung Kwon, Paul C. Parries, Hongwen Yan
  • Patent number: 8481429
    Abstract: A method of manufacturing a semiconductor device is provided. According to an embodiment, the method includes forming a layer to be etched on a semiconductor substrate, and forming a photoresist pattern on the layer to be etched. A block copolymer including a hydrophobic radical and a hydrophilic radical is formed in the photoresist pattern, and the block copolymer is assembled to allow a polymer having the hydrophobic radical to be formed in a pillar pattern within a polymer having the hydrophilic radical. The polymer having the hydrophobic radical is then selectively removed.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: July 9, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae Heon Kim, Cheol Kyu Bok
  • Publication number: 20130171797
    Abstract: A method of forming a multi-component dielectric layer on the surface of a substrate by atomic layer deposition includes injecting a cocktail source of a plurality of sources at least having a cyclopentadienyl ligand, wherein the cocktail source is adsorbed on a surface of a substrate by injecting the cocktail source, performing a first purge process to remove a non-adsorbed portion of the cocktail source, injecting a reactant to react with the adsorbed cocktail source, wherein a multi-component layer is formed by the reaction between the reactant and the absorbed cocktail source, and performing a second purge process to remove reaction byproducts and an unreacted portion of the reactant.
    Type: Application
    Filed: May 3, 2012
    Publication date: July 4, 2013
    Inventors: Kyung-Woong PARK, Kee-Jeung LEE, Jae-Hyoung KOO, Kwan-Woo DO, Ji-Hoon AHN, Woo-Young PARK
  • Patent number: 8476739
    Abstract: A graphene-on-oxide substrate according to the present invention includes: a substrate having a metal oxide layer formed on its surface; and, formed on the metal oxide layer, a graphene layer including at least one atomic layer of the graphene. The graphene layer is grown generally parallel to the surface of the metal oxide layer, and the inter-atomic-layer distance between the graphene atomic layer adjacent to the surface of the metal oxide layer and the surface atomic layer of the metal oxide layer is 0.34 nm or less. Preferably, the arithmetic mean surface roughness Ra of the metal oxide layer is 1 nm or less.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: July 2, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Okai, Motoyuki Hirooka, Takashi Kyotani, Hironori Orikasa
  • Patent number: 8476170
    Abstract: According to one embodiment, a pattern formation method includes, before forming a circuit pattern on a substrate using imprinting, a wall pattern with a predetermined height is formed to surround the periphery of an area serving as imprint shots on the substrate in each imprint shot and to allow the imprint shots to be separated from one another. The circuit pattern is formed in the imprint shots surrounded by the wall pattern through imprinting.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: July 2, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomoko Ojima
  • Publication number: 20130164919
    Abstract: A method of fabricating a semiconductor device may include forming active and field regions in a substrate; forming a gate trench in which the active and field regions are exposed; forming a gate insulating layer on a surface of the exposed active region, wherein forming the gate insulating layer includes forming a first gate oxide layer by primarily oxidizing the surface of the active region, and forming a second gate oxide layer between the surface of the active region and the first gate oxide layer by secondarily oxidizing the surface of the active region; conformally forming a gate barrier layer on the gate insulating layer and the exposed field region; forming a gate electrode layer on the gate barrier layer; and forming a gate capping layer in contact with the gate insulating layer, the gate barrier layer, and the gate electrode layer in the gate trench.
    Type: Application
    Filed: September 6, 2012
    Publication date: June 27, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tai-Su PARK, Gun-Joong LEE, Young-Dong LEE, Sang-Chul HAN, Joo-Byoung YOON
  • Publication number: 20130161798
    Abstract: Methods and structure are provided for utilizing a dielectric mask layer having a gradated density structure. The density of the dielectric mask layer is greatest at the interface of the dielectric mask layer and an underlying dielectric layer. The density of the dielectric mask layer is lowest at the interface of the dielectric mask layer and an overlaying hard mask. The lower density dielectric mask layer is more susceptible to removal than the higher density dielectric mask layer. The lower density dielectric mask layer is removed during at least one of an RIE etch or a post-RIE etch wet clean. Selective removal of the lower density dielectric mask layer creates a dielectric mask layer having a rounded profile. The dielectric mask layer comprises tetraethyl orthosilicate.
    Type: Application
    Filed: December 22, 2011
    Publication date: June 27, 2013
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventor: Hideyuki Tomizawa
  • Patent number: 8471267
    Abstract: A semiconductor device of the present invention has a semiconductor element region 17 that is provided in part of a silicon carbide layer 3 and a guard-ring region 18 that is provided in another part of the silicon carbide layer 3 surrounding the semiconductor element region 17 when seen in a direction perpendicular to a principal surface of the silicon carbide layer 3.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: June 25, 2013
    Assignee: Panasonic Corporation
    Inventors: Masashi Hayashi, Koichi Hashimoto, Kazuhiro Adachi
  • Publication number: 20130146973
    Abstract: A customized shield plate field effect transistor (FET) includes a semiconductor layer, a gate dielectric, a gate electrode, and at least one customized shield plate. The shield plate includes a conductive layer overlying a portion of the gate electrode, one of the gate electrode sidewalls, and a portion of the substrate adjacent to the sidewall. The shield plate defines a customized shield plate edge at its lateral boundary. A distance between the customized shield plate edge and the sidewall of the gate electrode varies along a length of the sidewall. The customized shield plate edge may form triangular, curved, and other shaped shield plate elements. The configuration of the customized shield plate edge may reduce the area of the resulting capacitor and thereby achieve lower parasitic capacitance associated with the FET. The FET may be implemented as a lateral diffused MOS (LDMOS) transistor suitable for high power radio frequency applications.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 13, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Agni Mitra, David C. Burdeaux
  • Publication number: 20130149870
    Abstract: A substrate carrier for performing a deposition process comprises a supporting element and a cover element. The supporting element having a through hole is used to carry a substrate. The cover element is removably engaged with the supporting element, so as to secure the substrate therebetween and expose a deposition surface of the substrate from the through hole.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 13, 2013
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chun-Hsing Tung, Fei-Tzu Lin
  • Publication number: 20130146949
    Abstract: The embodiments of processes and structures described above provide mechanisms for improving mobility of carriers. The dislocations in the source and drain regions and the strain created by the doped epitaxial materials next to the channel region of a transistor both contribute to the strain in the channel region. As a result, the device performance is improved.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 13, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hsiung TSAI, Tsan-Chun WANG, Su-Hao LIU, Tsz-Mei KWOK, Chii-Meng WU
  • Publication number: 20130143415
    Abstract: Provided are atomic layer deposition apparatus and methods including a gas distribution plate comprising a plurality of elongate gas ports including at least one first reactive gas port in fluid communication with a first reactive gas and at least one second reactive gas port in fluid communication with a gas manifold. The gas manifold is in fluid communication with at least a second reactive gas different from the first reactive gas and a purge gas. Also provided are atomic layer deposition apparatus and methods including linear energy sources in one or more of region before the gas distribution plate and a region after the gas distribution plate.
    Type: Application
    Filed: December 1, 2011
    Publication date: June 6, 2013
    Applicant: Applied Materials, Inc.
    Inventors: Joseph Yudovsky, Mei Chang, Steven D. Marcus, Garry K. Kwong
  • Patent number: 8455371
    Abstract: Disclosed is a sputtering target having a good appearance, which is free from white spots on the surface. The sputtering target is characterized by being composed of an oxide sintered body containing two or more kinds of homologous crystal structures.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: June 4, 2013
    Assignee: Idemitsu Kosan Co., Ltd.
    Inventors: Koki Yano, Hirokazu Kawashima, Kazuyoshi Inoue
  • Publication number: 20130134530
    Abstract: Embodiments related to semiconductor manufacturing and semiconductor devices with semiconductor structure are described and depicted.
    Type: Application
    Filed: November 24, 2011
    Publication date: May 30, 2013
    Inventors: Thoralf KAUTZSCH, Boris BINDER, Torsten HELM, Stefan KOLB, Marc PROBST, Uwe RUDOLPH
  • Publication number: 20130126870
    Abstract: The present invention discloses a TFT, an array substrate, a device and a manufacturing method. The TFT comprises a conductive metal layer; an insulting oxidizing layer is formed on the surface of the metal layer. In the present invention, because the oxidation treatment is conducted on the surface of the metal layer, the insulating oxidizing layer is formed and can substitute for the silicon nitride as a TFT barrier layer; compared with the preparation of a silicon nitride barrier layer needing the drilling crew and the material cost, the preparation of the oxidizing layer needs cheap equipment without increasing further materials so that the cost is saved; in addition, the oxidizing layer only exists on the surface of the metal layer, and has small obstruction for light and low requirement for the penetration rate; thus, the process control is relatively simple and the cost can be further reduced.
    Type: Application
    Filed: December 2, 2011
    Publication date: May 23, 2013
    Inventor: Hao Kou
  • Publication number: 20130122707
    Abstract: Methods of polymer deposition for forming reduced critical dimensions are described. In one embodiment, a substrate is provided into a chamber, the substrate having a patterned layer disposed on an underlying layer formed thereon. The patterned layer includes a plurality of openings, each opening having a sidewall, a bottom, and a critical dimension. A gas mixture is provided into the chamber, the gas mixture having an etching gas and a polymer control gas. The polymer control gas includes a polymerizing fluorocarbon CxFy gas and a C—H bond containing gas. A plasma is formed with the gas mixture and a conformal polymer layer is deposited in the presence of the plasma on the patterned layer to form a reduced critical dimension in each opening. The reduced critical dimension is smaller than the corresponding critical dimension of the opening.
    Type: Application
    Filed: October 19, 2012
    Publication date: May 16, 2013
    Inventors: Daisuke Shimizu, Jong Mun Kim
  • Publication number: 20130119496
    Abstract: The present disclosure describes a semiconductor MRAM device and a manufacturing method. The device reduces magnetic field induction “interference” (disturbance) phenomenon between adjacent magnetic tunnel junctions when data is written and read. This semiconductor MRAM device comprises a magnetic tunnel junction unit and a magnetic shielding material layer covering the sidewalls of the magnetic tunnel junction unit. The method for manufacturing a semiconductor device comprises: forming a magnetic tunnel junction unit, depositing an isolation dielectric layer to cover the top and the sidewall of the magnetic tunnel junction unit, and depositing a magnetic shielding material layer on the isolation dielectric layer.
    Type: Application
    Filed: October 17, 2012
    Publication date: May 16, 2013
    Applicants: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (BEIJING), SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (SHANGHAI)
    Inventors: SEMICONDUCTOR MANUFACTURING INTERNA, SEMICONDUCTOR MANUFACTURING INTERNA
  • Publication number: 20130113086
    Abstract: Planarization methods and microelectronic structures formed therefrom are disclosed. The methods and structures use planarization materials comprising fluorinated compounds or acetoacetylated compounds. The materials are self-leveling and achieve planarization over topography without the use of etching, contact planarization, chemical mechanical polishing, or other conventional planarization techniques.
    Type: Application
    Filed: November 8, 2012
    Publication date: May 9, 2013
    Applicant: BREWER SCIENCE INC.
    Inventor: Brewer Science Inc.
  • Publication number: 20130115763
    Abstract: The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursor and dopant precursor adsorb on the substrate surface. Oxygen plasma is used to convert the adsorbed silicon precursor and dopant precursor to doped silicon oxide.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 9, 2013
    Applicant: ASM INTERNATIONAL. N.V.
    Inventor: ASM International. N.V.
  • Patent number: 8435882
    Abstract: The present invention may be a semiconductor device including of a fluorinated insulating film and a SiCN film deposited on the fluorinated insulating film directly, wherein a density of nitrogen in the SiCN film decreases from interface between the fluorinated insulating film and the SiCN film. In the present invention, the SiCN film that is highly fluorine-resistant near the interface with the CFx film and has a low dielectric constant as a whole can be formed as a hard mask.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: May 7, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Takaaki Matsuoka, Kohei Kawamura
  • Patent number: 8435856
    Abstract: A method for forming a split gate flash cell memory device provides for establishing a floating gate region then using spacers or other hard mask materials that cover opposed edges of a gate electrode material in the gate region, to serve as hard masks during an etching operation that partially etches the gate electrode material which may be polysilicon. The gate electrode so produced serves as a floating gate electrode and includes a recessed central portion flanked by a pair of opposed upwardly extending fins which may terminate upwardly at an apex. A floating gate oxide is then formed by thermal oxidation and/or oxide deposition techniques.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: May 7, 2013
    Assignee: Wafertech, LLC
    Inventors: Yimin Wang, Raymond Li
  • Publication number: 20130109198
    Abstract: The disclosure relates to a method of depositing amorphous carbon on a substrate using at least one carbon containing molecule having at least one carbon atom the method comprising the steps of supplying the carbon containing molecule and carrying out the deposition to thereby form a deposited amorphous carbon on the substrate, wherein a carbon to hydrogen ratio of the molecule is equal to or more than 0.7.
    Type: Application
    Filed: October 26, 2011
    Publication date: May 2, 2013
    Applicant: AMERICAN AIR LIQUIDE, INC.
    Inventors: Christian DUSSARRAT, Vincent M. OMARJEE
  • Publication number: 20130109196
    Abstract: A method of operating a film forming apparatus includes forming a carbon film on each of surfaces of a plurality of objects held by a holding unit in a processing container and performing a cleaning process with a cleaning gas to remove an unnecessary carbon film adhered on a inside of the processing container, wherein the method further includes, before the forming of the carbon film, forming, on a surface of a member contacting a processing space in the processing container, a tolerant pre-coating film which has a tolerance to the cleaning gas and improves adhesion of the carbon film to the surface of the member. Accordingly, the adhesion of the carbon film is improved, and further, the tolerant pre-coating film remains even when the cleaning process of removing the unnecessary carbon film is performed.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 2, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: TOKYO ELECTRON LIMITED
  • Publication number: 20130109195
    Abstract: Provided is a method of operating a film forming apparatus capable of suppressing generation of particles by improving an adhesion of a carbon film to surfaces of members which are formed of a quartz material and contact a processing space in a processing container. The method includes forming a carbon film on each of surfaces of a plurality of objects held by a holding unit in a processing container formed of a quartz material, wherein the method further includes forming an adhesion film to improve the adhesion of the carbon film, on surfaces of members which are formed of a quartz material and contact a processing space in the processing container. Accordingly, the adhesion of the carbon film to the surface of the member formed of a quartz material contacting the processing space in the processing container is improved, thereby suppressing generation of particles.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 2, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: TOKYO ELECTRON LIMITED
  • Publication number: 20130099194
    Abstract: There is provided a method for forming a graphene layer. The method includes forming an article that comprises a carbon-containing self-assembled monolayer (SAM). A layer of nickel is deposited on the SAM. The article is heated in a reducing atmosphere and coolded. The heating and cooling steps are carried out so as to convert the SAM to a graphene layer.
    Type: Application
    Filed: October 21, 2011
    Publication date: April 25, 2013
    Inventor: Ashok J. Maliakal
  • Publication number: 20130099349
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface and a second surface, and having a LSI on the first surface of the semiconductor substrate, a first insulating layer with an opening, the first insulating layer provided on the first surface of the semiconductor substrate, a conductive layer on the opening, the conductive layer being connected to the LSI, and a via extending from a second surface of the semiconductor substrate to the conductive layer through the opening, the via having a size larger than a size of the opening in a range from the second surface to a first interface between the semiconductor substrate and the first insulating layer, and having a size equal to the size of the opening in the opening.
    Type: Application
    Filed: August 24, 2012
    Publication date: April 25, 2013
    Inventor: Akiko Nomachi
  • Publication number: 20130095664
    Abstract: Antimony oxide thin films are deposited by atomic layer deposition using an antimony reactant and an oxygen source. Antimony reactants may include antimony halides, such as SbCl3, antimony alkylamines, and antimony alkoxides, such as Sb(OEt)3. The oxygen source may be, for example, ozone. In some embodiments the antimony oxide thin films are deposited in a batch reactor. The antimony oxide thin films may serve, for example, as etch stop layers or sacrificial layers.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 18, 2013
    Applicant: ASM International. N.V.
    Inventor: ASM International. N.V.
  • Publication number: 20130093064
    Abstract: A semiconductor process includes the following steps. A substrate is provided. A dielectric layer having a high dielectric constant is formed on the substrate, wherein the steps of forming the dielectric layer include: (a) a metallic oxide layer is formed; (b) an annealing process is performed to the metallic oxide layer; and the steps (a) and (b) are performed repeatedly. Otherwise, the present invention further provides a semiconductor structure formed by said semiconductor process.
    Type: Application
    Filed: October 12, 2011
    Publication date: April 18, 2013
    Inventors: Chien-Liang Lin, Shao-Wei Wang, Yu-Ren Wang, Ying-Wei Yen
  • Patent number: 8420541
    Abstract: A method for increasing adhesion between polysilazane and silicon nitride is disclosed, comprising, providing a substrate comprising a trench, forming a silicon nitride liner layer on a bottom surface and a sidewall of the trench, performing a treating process to the silicon nitride liner layer for producing a hydrophilic surface with OH groups that can increase adhesion between the silicon nitride liner layer and a subsequently formed polysilazane coating layer, and forming a polysilazane coating layer into the trench and on the silicon nitride liner layer.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: April 16, 2013
    Assignee: Nanya Technology Corporation
    Inventors: Shing-Yih Shih, Yi-Nan Chen, Hsien-Wen Liu
  • Publication number: 20130089985
    Abstract: When forming strain-inducing dielectric material layers above transistors of different conductivity type, the patterning of at least one strain-inducing dielectric material may be accomplished on the basis of a process sequence in which a negative influence of a fluorine species in an oxygen plasma upon removing the resist mask is avoided or at least significantly suppressed. For example, a substantially oxygen-free plasma process may be applied for removing the resist material.
    Type: Application
    Filed: October 5, 2011
    Publication date: April 11, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ronald NAUMANN, Volker GRIMM, Andrey ZAKHAROV, Ralf RICHTER
  • Publication number: 20130087883
    Abstract: A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500° C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800° C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches.
    Type: Application
    Filed: October 7, 2011
    Publication date: April 11, 2013
    Inventors: James Mathew, Brett D. Lowe, Yunjun Ho, H. Jim Fulford, Jie Sun, Zhaoli Sun
  • Patent number: 8415259
    Abstract: A method of forming a film on a semiconductor substrate by plasma enhanced atomic layer deposition (PEALD), includes: introducing a nitrogen- and hydrogen-containing reactive gas and a rare gas into a reaction space inside which the semiconductor substrate is placed; introducing a precursor in pulses of less than 1.0-second duration into the reaction space wherein the reactive gas and the rare gas are introduced; exiting a plasma in pulses of less than 1.0-second duration immediately after the precursor is shut off; and maintaining the reactive gas and the rare gas as a purge of less than 2.0-second duration.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: April 9, 2013
    Assignee: ASM Japan K.K.
    Inventors: Woo Jin Lee, Kuo-Wei Hong, Akira Shimizu, Daekyun Jeong