Abstract: A method of fabricating a semiconductor device having a different gate structure in each of a plurality of device regions is described. The method may include a replacement gate process. The method includes forming a hard mask layer on oxide layers formed on one or more regions of the substrate. A high-k gate dielectric layer is formed on each of the first, second and third device regions. The high-k gate dielectric layer may be formed directly on the hard mask layer in a first and second device regions and directly on an interfacial layer formed in a third device region. A semiconductor device including a plurality of devices (e.g., transistors) having different gate dielectrics formed on the same substrate is also described.

Abstract: A structure making up a part of a semiconductor device, such as a fin structure of a finFET device, is formed on and electrically isolated from a semiconductor substrate. The structure is comprised of the semiconductor substrate material and is electrically isolated from a remaining portion of the semiconductor substrate by an insulating barrier. The insulating barrier is formed by an isotropic oxidation process that oxidizes portions of the semiconductor substrate that are not protected by an oxidation barrier.

Abstract: In accordance with an embodiment, a semiconductor device includes a substrate, a line-and-space structure, a first film and a second film. The line-and-space structure includes line patterns arranged on the substrate parallel to one another at a predetermined distance. The first film is formed on side surfaces and bottom surfaces of the line patterns by an insulating film material. The second film is formed on the line-and-space structure across a space between the line patterns by a material showing low wettability to the first film. Space between the line patterns includes an air gap in which at least a bottom surface of the first film is totally exposed.

Abstract: A method for doubling the frequency of a lithographic process using a photo-resist template mask is described. A device layer having a photo-resist layer formed thereon is first provided. The photo-resist layer is patterned to form a photo-resist template mask. A spacer-forming material layer is deposited over the photo-resist template mask. The spacer-forming material layer is etched to form a spacer mask and to expose the photo-resist template mask. The photo-resist template mask is then removed and an image of the spacer mask is finally transferred to the device layer.

Abstract: A method of forming an isolation structure includes the steps of forming an insulating spacer on the side surfaces of a trench in a substrate, exposing a portion of the substrate, growing an epitaxial silicon layer above a bottom surface of the trench, oxidizing the epitaxial silicon layer to form a thermal oxide layer, and filling a portion of the trench above the thermal oxide layer with a dielectric material.

Abstract: A moisture barrier, device or product having a moisture barrier or a method of fabricating a moisture barrier having at least a polymer layer, and interfacial layer, and a barrier layer. The polymer layer may be fabricated from any suitable polymer including, but not limited to, fluoropolymers such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), or ethylene-tetrafluoroethylene (ETFE). The interfacial layer may be formed by atomic layer deposition (ALD). In embodiments featuring an ALD interfacial layer, the deposited interfacial substance may be, but is not limited to, Al2O3, AlSiOx, TiO2, and an Al2O3/TiO2 laminate. The barrier layer associated with the interfacial layer may be deposited by plasma enhanced chemical vapor deposition (PECVD). The barrier layer may be a SiOxNy film.

Abstract: An apparatus and methods for depositing amorphous and microcrystalline silicon films during the formation of solar cells are provided. In one embodiment, a method and apparatus is provided for generating and introducing hydrogen radicals directly into a processing region of a processing chamber for reaction with a silicon-containing precursor for film deposition on a substrate. In one embodiment, the hydrogen radicals are generated by a remote plasma source and directly introduced into the processing region via a line of sight path to minimize the loss of energy by the hydrogen radicals prior to reaching the processing region.

Abstract: Method for depositing a layer on a surface of a substrate. The method comprises injecting a precursor gas from a precursor supply into a deposition cavity for contacting the substrate surface, draining part of the injected precursor gas from the deposition cavity, and positioning the deposition cavity and the substrate relative to each other along a plane of the substrate surface. The method further comprising providing a first electrode and a second electrode, positioning the first electrode and the substrate relative to each other, and generating a plasma discharge near the substrate for contacting the substrate by generating a high-voltage difference between the first electrode and the second electrode. The method comprises generating the plasma discharge selectively, for patterning the surface by means of the plasma. A portion of the substrate contacted by the precursor gas selectively overlaps with a portion of the substrate contacted by the plasma.

Abstract: A structure of the plasma treatment apparatus is employed in which an upper electrode has projected portions provided with first introduction holes and recessed portions provided with second introduction holes, the first introduction hole of the upper electrode is connected to a first cylinder filled with a gas which is not likely to be dissociated, the second introduction hole is connected to a second cylinder filled with a gas which is likely to be dissociated, the gas which is not likely to be dissociated is introduced into a reaction chamber from an introduction port of the first introduction hole provided on a surface of the projected portion of the upper electrode, and the gas which is likely to be dissociated is introduced into the reaction chamber from an introduction port of the second introduction hole provided on a surface of the recessed portion.

Abstract: A fabricating method of a MOS transistor includes the following steps. A substrate is provided. A gate dielectric layer is formed on the substrate. A nitridation process containing nitrogen plasma and helium gas is performed to nitride the gate dielectric layer. A fin field-effect transistor and fabrication method thereof are also provided.

Abstract: In a sophisticated metallization system, self-aligned air gaps may be provided in a locally selective manner by using a radiation sensitive material for filling recesses or for forming therein the metal regions. Consequently, upon selectively exposing the radiation sensitive material, a selective removal of exposed or non-exposed portions may be accomplished, thereby resulting in a highly efficient overall manufacturing flow.

Abstract: A silicon dioxide layer is deposited onto a substrate using a process gas comprising BDEAS and an oxygen-containing gas such as ozone. The silicon dioxide layer can be part of an etch-resistant stack that includes a resist layer. In another version, the silicon dioxide layer is deposited into through holes to form an oxide liner for through-silicon vias.

Abstract: Atomic layer deposition (ALD) processes for forming Group VA element containing thin films, such as Sb, Sb—Te, Ge—Sb and Ge—Sb—Te thin films are provided, along with related compositions and structures. Sb precursors of the formula Sb(SiR1R2R3)3 are preferably used, wherein R1, R2, and R3 are alkyl groups. As, Bi and P precursors are also described. Methods are also provided for synthesizing these Sb precursors. Methods are also provided for using the Sb thin films in phase change memory devices.

Abstract: A method of fabricating a silicon-containing oxide layer that includes providing a chemical oxide layer on a surface of a semiconductor substrate, removing the chemical oxide layer in an oxygen-free environment at a temperature of 1000° C. or greater to provide a bare surface of the semiconductor substrate, and introducing an oxygen-containing gas at a flow rate to the bare surface of the semiconductor substrate for a first time period at the temperature of 1000° C. The temperature is then reduced to room temperature during a second time period while maintaining the flow rate of the oxygen containing gas to provide a silicon-containing oxide layer having a thickness ranging from 0.5 ? to 10 ?.

Abstract: The invention relates to a process for fabricating a semiconductor that comprises providing a handle substrate comprising a seed substrate and a weakened sacrificial layer covering the seed substrate; joining the handle substrate with a carrier substrate; optionally treating the carrier substrate; detaching the handle substrate at the sacrificial layer to form the semiconductor structure; and removing any residue of the sacrificial layer present on the seed substrate.

Abstract: Different gases are separately exposed to RF energy in different zones in inlets to a processing chamber. Plasma is activated in the gases in each of the zones separately and the activated gases are then introduced into the plasma processing chamber where they may undergo mutual interaction within a processing zone. Control of the active species distribution within the processing chamber is provided by control of the energizing of the gases in the separate inlet zones before they are combined in the processing zone. An ICP source energizes gas in each zone through an antenna having one or more conductors, each of which is coupled to a plurality of the zones. This allows gases to be brought together in their active states, rather than being combined and then activated, and allows the same or different parameters to be applied in different inlet zones.

Abstract: Systems and methods of the present invention can be used to charge a charge-holding layer (such as a passivation layer and/or antireflective layer) of a solar cell with a positive or negative charge as desired. The charge-holding layer(s) of such a cell can include any suitable dielectric material capable of holding either a negative or a positive charge, and can be charged at any suitable point during manufacture of the cell, including during or after deposition of the passivation layer(s). A method according to one aspect of the invention includes disposing a solar cell in electrical communication with an electrode inside a chamber. The solar cell includes an emitter, a base, a first passivation layer adjacent the emitter, and a second passivation layer adjacent the base. Gas is injected into the chamber and a plasma (with photons having an energy level of at least about 3.1 eV) is generated using the gas.

Abstract: A semiconductor wafer includes multiple dies and a die identification region adjacent to or on each die. The die identification region can include a wafer indicator and a pattern of die locations representing die locations on the wafer. A die identification marker is provided in each pattern of die locations in the die identification region specifying a location of a respective die on the wafer.

Abstract: In one embodiment, a method includes forming a base region for a transistor using a base mask and forming a contact region to the base region. The contact region is formed in an area that is at least partially outside of the base mask. The method then forms an emitter region in a diffused base region. The base region diffuses outwardly to be formed under the contact region.

Abstract: An asymmetric slotted waveguide and method for fabricating the same. The slotted waveguide is constructed in silicon-on-insulator using a Complementary metal-oxide-semiconductor (CMOS) process. One or more wafers can be coated with a photo resist material using a photolithographic process in order to thereby bake the wafers via a post apply bake (PAB) process. An anti-reflective coating (TARC) can be further applied on the wafers and the wafers can be exposed on a scanner for the illumination conditions. After a post exposure bake (PEB), the wafers can be developed in a developer using a puddle develop process. Finally, the printed wafers can be processed using a shrink process to reduce the critical dimension (CD) of the slot and thereby achieve an enhanced asymmetric slotted waveguide that is capable of guiding the optical radiation in a wide range of optical modulation applications using an electro-optic polymer cladding.

Abstract: A substrate with a vent for a semiconductor device where the vent is integrated within the substrate itself. The integrated air vent forms a passageway or relief path for gas or air within a mold cavity to escape during a transfer molding packaging process. The vents integrated in the substrate reduce trapped gas and mold voids and limit vent flash to improve yield.

Abstract: A coating film forming method according to an embodiment, includes rotating a substrate, supplying a chemical solution for forming a coating film onto the rotating substrate, and supplying a liquid having a lower temperature than an atmosphere of the substrate to an edge of the substrate from a back side of the substrate while a film is formed by supplying the chemical solution onto the rotating substrate.

Abstract: A first single crystal substrate has a first side surface and it is composed of silicon carbide. A second single crystal substrate has a second side surface opposed to the first side surface and it is composed of silicon carbide. A bonding portion connects the first and second side surfaces to each other between the first and second side surfaces. At least a part of the bonding portion is made of particles composed of silicon carbide and having a maximum length not greater than 1 ?m.

Abstract: A stress film forming method is used in a fabrication process of a semiconductor device. Firstly, a substrate is provided, wherein a first-polarity-channel MOSFET and a second-polarity-channel MOSFET are formed on the substrate. Then, at least one deposition-curing cycle process is performed to form a cured stress film over the first-polarity-channel MOSFET and the second-polarity-channel MOSFET. Afterwards, an additional deposition process is performed form a non-cured stress film on the cured stress film, wherein the cured stress film and the non-cured stress film are collectively formed as a seamless stress film.

Abstract: A method of manufacturing a semiconductor device by using a substrate processing apparatus comprises a reaction chamber configured to process a plurality of substrates stacked at predetermined intervals, wherein a first gas flow from a first gas supply inlet and a second gas flow from a second gas supply inlet are crossed with each other before these gas flows reach the substrates. The method of manufacturing a semiconductor device comprises: loading the plurality of substrates into the reaction chamber; supplying a silicon-containing gas and a chlorine-containing gas from the first gas supply inlet into the reaction chamber, supplying a carbon-containing gas and a reducing gas from the second gas supply inlet into the reaction chamber and supplying a dopant-containing gas into the reaction chamber from the first gas supply inlet or the second gas supply inlet; and unloading the substrates from the reaction chamber.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate having a gate structure, a source region, and a drain region formed thereon, and the gate structure includes a gate insulating layer and a gate electrode. The method also includes forming a first stress layer on the substrate, removing the first stress layer, and forming a second stress layer on the substrate.

Abstract: A method of manufacturing a semiconductor device according to the invention includes the step S1 of cleaning the silicon carbide substrate 1 surface, the step S2 of bringing a material gas into a plasma and irradiating the atoms contained in the material gas to silicon carbide substrate 1 for growing silicon nitride film 2 on silicon carbide substrate 1, the step S3 of depositing silicon oxide film 3 on silicon nitride film 2 by the ECR plasma CVD method, and the step S4 of annealing silicon carbide substrate 1 including silicon nitride film 2 and silicon oxide film 3 formed thereon in a nitrogen atmosphere. By the method of manufacturing a semiconductor device according to the invention, a semiconductor device that exhibits excellent interface properties including an interface state density and a flat band voltage is obtained.

Abstract: A method for forming a hydrogen barrier layer that overlies ferroelectric capacitors and a buffer region but is removed from a portion of the logic region.

Abstract: A process for forming a shallow trench isolation structure is provided. Firstly, a semiconductor substrate is provided. Then, a hard mask is formed over the semiconductor substrate, wherein the hard mask includes a pad oxide layer, a silicon nitride layer and an opening. Then, a trench is formed in the semiconductor substrate according to the opening Then, a pull-back process is performed to treat the silicon nitride layer at a sidewall of the opening, wherein the pull-back process is a wet etching process carried out in a phosphoric acid solution. After the pull-back process is performed, an insulating material is filled in the trench, thereby forming the shallow trench isolation structure.

Abstract: A disclosed fabrication method of a semiconductor device includes steps of depositing a dielectric film on a semiconductor substrate; thermally treating the dielectric film; and irradiating an ionized gas cluster onto the thermally treated dielectric film.

Abstract: A thin film transistor display panel includes gate wiring formed on an insulation substrate and including gate lines, and gate electrodes and gate pads connected to the gate lines; a gate insulation layer covering the gate wiring; a semiconductor pattern formed over the gate insulation layer; data wiring formed over the gate insulation layer or the semiconductor pattern and including source electrodes, drain electrodes, and data pads; a protection layer including a Nega-PR type of organic insulating layer formed all over the semiconductor pattern and the data wiring, wherein the thickness of the Nega-PR type of organic insulating layer in both the gate and data pad regions is smaller than in the other regions; and a pixel electrode connected to the drain electrode. When exposing the Nega-PR type of passivation layer in the pad region during a photolithography process, a photomask having a lattice pattern made of a metal such as Cr that has a line width of less than the resolution of a light exposer is used.

Abstract: A substrate structure is produced by forming a first material layer on a substrate having a recess, removing the first material layer from the portion of the substrate except for the recess using a second material that reacts with the first material, and forming a deposition film from the first material layer using a third material that reacts with the first material. A method of manufacturing a device may include the method of forming a substrate structure.

Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes providing a substrate having a charge-trapping layer disposed thereon. A portion of the charge-trapping layer is then oxidized to form a blocking dielectric layer above the charge-trapping layer by exposing the charge-trapping layer to a radical oxidation process.

Abstract: Two plates, each comprising a thin layer of silicon or silicon oxide at a surface thereof, are bonded by subjecting the thin layer of at least one of the plates to a surface treatment step forming a silicon oxynitride superficial thin film with a thickness of less than 5nm. The thin film is performed with a nitrogen-based plasma generated by an inductively coupled plasma source. Furthermore, a potential difference applied between the plasma and a substrate holder supporting said plate during the surface treatment step is less than 50 V, advantageously less than 15 V and preferably zero. This enables a defect-free bonding interface to be obtained irrespective of a temperature of any heat treatment carried out after a contacting step between the respective thin layers of the two plates.

Abstract: Apparatus and related fabrication methods are provided for semiconductor device structures having encapsulated isolation regions. An exemplary method for fabricating a semiconductor device structure involves the steps of forming an isolation region of a first dielectric material in the semiconductor substrate adjacent to a first region of the semiconductor material, forming a first layer of a second dielectric material overlying the isolation region and the first region, and removing the second dielectric material overlying the first region leaving portions of the second dielectric material overlying the isolation region intact. The isolation region is recessed relative to the first region, and the second dielectric material is more resistant to an etchant than the first dielectric material.

Abstract: Various embodiments provide a device having a multi-scale superoleophobic surface and methods for forming and using the device, wherein a particulate composite layer including metal-containing particulates is formed on a textured micron-/sub-micron surface of a semiconductor layer to provide device with multi-scale rough surface.

Abstract: Methods of fabricating three-dimensional semiconductor memory devices including forming a plate stack structure with insulating layers and sacrificial layers stacked alternatingly on a substrate, forming first and second trenches separating the plate stack structure into a plurality of mold structures, the first trench being between the second trenches, forming first vertical insulating separators in the first and second trenches, forming semiconductor patterns penetrating the mold structure and being spaced apart from the first and second trenches, removing the first vertical insulating separator from the second trench to expose the sacrificial layers, removing the sacrificial layers exposed by the second trench to form recess regions partially exposing the semiconductor patterns and the first vertical insulating separator, and forming conductive patterns in the recess regions.

Abstract: Techniques related to nanocomposite dielectric materials are generally described herein. These techniques may be embodied in apparatuses, systems, methods and/or processes for making and using such material. An example process may include: providing a film having a plurality of nanoparticles and an organic medium; comminuting the film to form a particulate; and applying the particulate to a substrate. The example process may also include providing a nanoparticle film having nanoparticles and voids located between the nanoparticles; contacting the film with a vapor containing an organic material; and curing the organic material to form the nanocomposite dielectric film. Various described techniques may provide nanocomposite dielectric materials with superior nanoparticle dispersion which may result in improved dielectric properties.

Abstract: Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs on ICs. FET locations are defined on a layered semiconductor wafer, preferably a Silicon On Insulator (SOI) wafer. One or more FET locations are defined as silicon gate locations and remaining as Replacement Metal Gate (RMG) FET locations with at least one of each on the IC. Polysilicon gates are formed in all FET locations. Gates in silicon gate locations are tailored, e.g., doped and silicided. Remaining polysilicon gates are replaced with metal in RMG FET locations. FETs are connected together into circuits with RMG FETs being connected to silicon gate FETs.

Abstract: The threshold voltage of parasitic transistors formed at corners of shallow trench isolation regions is increased and mobility decreased by employing a high-K dielectric material. Embodiments include STI regions comprising a liner of a high-K dielectric material extending proximate trench corners. Embodiments also include STI regions having a recess formed in the trench, wherein the recess contains a high-K dielectric material, in the form of a layer or spacer, extending proximate trench corners.

Abstract: A method of manufacturing a semiconductor device is provided. According to an embodiment, the method includes forming a layer to be etched on a semiconductor substrate, and forming a photoresist pattern on the layer to be etched. A block copolymer including a hydrophobic radical and a hydrophilic radical is formed in the photoresist pattern, and the block copolymer is assembled to allow a polymer having the hydrophobic radical to be formed in a pillar pattern within a polymer having the hydrophilic radical. The polymer having the hydrophobic radical is then selectively removed.

Abstract: A hybrid deposition process of CVD and ALD, called NanoLayer Deposition (NLD) is provided. The NLD process is a cyclic sequential deposition process, including introducing a first plurality of precursors to deposit a thin film and introducing a second plurality of precursors to modify the deposited thin film. The deposition using the first set of precursors is not self limiting and is a function of substrate temperature and process time. The second set of precursors modifies the already deposited film characteristics. The second set of precursors can treat the deposited film, including treatments such as modification of film composition and doping or removal of impurities from the deposited film. The second set of precursors can also deposit another layer on the deposited film. The additional layer can react with the existing layer to form a compound layer, or can have minimum reaction to form a nanolaminate film.

Abstract: Acetylene is treated to remove some residual storage solvent that may be present with the acetylene in a source of acetylene such as a container. Such treatment may be performed prior to supplying the acetylene to a deposition chamber or other reactor where acetylene is a reactant. After treatment, the acetylene gas stream has a relatively constant concentration of storage solvent, regardless of how much acetylene has been released from the acetylene source. The treatment may involve condensing the storage solvent from the gas stream at a certain temperature and separating the storage solvent from the gas stream.

Abstract: A method for increasing adhesion between polysilazane and silicon nitride is disclosed, comprising, providing a substrate comprising a trench, forming a silicon nitride liner layer on a bottom surface and a sidewall of the trench, performing a treating process to the silicon nitride liner layer for producing a hydrophilic surface with OH groups that can increase adhesion between the silicon nitride liner layer and a subsequently formed polysilazane coating layer, and forming a polysilazane coating layer into the trench and on the silicon nitride liner layer.

Abstract: A method of forming a dielectric stack devoid of an interfacial layer includes subjecting an exposed interfacial layer provided on a semiconductor material to a low pressure thermal anneal process for a predetermined time period at a temperature of about 900° C. to about 1000° C. with an inert gas purge. A semiconductor structure is also disclosed, with a dielectric stack devoid of an interfacial layer.

Abstract: The present invention relates to a method for producing an electronic component, in particular a field-effect transistor (FET), comprising at least one substrate, at least one dielectric, and at least one semiconducting metal oxide, wherein the dielectric or a precursor compound thereof based on organically modified silicon oxide compounds, in particular based on silsequioxanes and/or siloxanes, can be processed out of solution, and is thermally treated at a low temperature from room temperature to 350° C., and the semiconductive metal oxide, in particular ZnO or a precursor compound thereof, can also be processed from solution at a low temperature from room temperature to 350° C.

Abstract: A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.

Abstract: A method of oxidizing polysilazane is disclosed, comprising providing a substrate, comprising a trench, forming a polysilazane layer in the trench, and treating the polysilazane layer in an acid containing solution applied with mega-sonic waves to oxidize the polysilazane layer, wherein the acid containing solution comprises phosphoric acid, sulfuric acid, H2SO4 added with O3 (SOM), H2SO4 added with H2O2 (SPM), H3PO4 added with O3, or H3PO4 added with H2O2, and removing the silicon oxide layer outside of the trench.

Abstract: A coating treatment apparatus supplying a coating solution to a front surface of a rotated substrate and diffusing the supplied coating solution to an outer periphery side of the substrate to thereby apply the coating solution on the front surface of the substrate includes: a substrate holding part holding a substrate; a rotation part rotating the substrate held on the substrate holding part; a supply part supplying a coating solution to a front surface of the substrate held on the substrate holding part; and an airflow control plate provided at a predetermined position above the substrate held on the substrate holding part for locally changing an airflow above the substrate rotated by the rotation part at an arbitrary position.

Abstract: A method for forming a trench isolation is disclosed, comprising, providing a substrate comprising a trench, forming a polysilicon layer in the trench, and subjecting the substrate to a treating process to convert the polysilicon layer to an isolating layer, wherein the treating process is fine tuned for the isolating layer on opposite sidewalls of the trench to expand to contact with each other so that the isolating layer fills the trench.