Abstract: A customized shield plate field effect transistor (FET) includes a semiconductor layer, a gate dielectric, a gate electrode, and at least one customized shield plate. The shield plate includes a conductive layer overlying a portion of the gate electrode, one of the gate electrode sidewalls, and a portion of the substrate adjacent to the sidewall. The shield plate defines a customized shield plate edge at its lateral boundary. A distance between the customized shield plate edge and the sidewall of the gate electrode varies along a length of the sidewall. The customized shield plate edge may form triangular, curved, and other shaped shield plate elements. The configuration of the customized shield plate edge may reduce the area of the resulting capacitor and thereby achieve lower parasitic capacitance associated with the FET. The FET may be implemented as a lateral diffused MOS (LDMOS) transistor suitable for high power radio frequency applications.

Abstract: Provided are atomic layer deposition apparatus and methods including a gas distribution plate comprising a plurality of elongate gas ports including at least one first reactive gas port in fluid communication with a first reactive gas and at least one second reactive gas port in fluid communication with a gas manifold. The gas manifold is in fluid communication with at least a second reactive gas different from the first reactive gas and a purge gas. Also provided are atomic layer deposition apparatus and methods including linear energy sources in one or more of region before the gas distribution plate and a region after the gas distribution plate.

Abstract: Disclosed is a sputtering target having a good appearance, which is free from white spots on the surface. The sputtering target is characterized by being composed of an oxide sintered body containing two or more kinds of homologous crystal structures.

Abstract: Embodiments related to semiconductor manufacturing and semiconductor devices with semiconductor structure are described and depicted.

Abstract: The present invention discloses a TFT, an array substrate, a device and a manufacturing method. The TFT comprises a conductive metal layer; an insulting oxidizing layer is formed on the surface of the metal layer. In the present invention, because the oxidation treatment is conducted on the surface of the metal layer, the insulating oxidizing layer is formed and can substitute for the silicon nitride as a TFT barrier layer; compared with the preparation of a silicon nitride barrier layer needing the drilling crew and the material cost, the preparation of the oxidizing layer needs cheap equipment without increasing further materials so that the cost is saved; in addition, the oxidizing layer only exists on the surface of the metal layer, and has small obstruction for light and low requirement for the penetration rate; thus, the process control is relatively simple and the cost can be further reduced.

Abstract: The present disclosure describes a semiconductor MRAM device and a manufacturing method. The device reduces magnetic field induction “interference” (disturbance) phenomenon between adjacent magnetic tunnel junctions when data is written and read. This semiconductor MRAM device comprises a magnetic tunnel junction unit and a magnetic shielding material layer covering the sidewalls of the magnetic tunnel junction unit. The method for manufacturing a semiconductor device comprises: forming a magnetic tunnel junction unit, depositing an isolation dielectric layer to cover the top and the sidewall of the magnetic tunnel junction unit, and depositing a magnetic shielding material layer on the isolation dielectric layer.

Abstract: Methods of polymer deposition for forming reduced critical dimensions are described. In one embodiment, a substrate is provided into a chamber, the substrate having a patterned layer disposed on an underlying layer formed thereon. The patterned layer includes a plurality of openings, each opening having a sidewall, a bottom, and a critical dimension. A gas mixture is provided into the chamber, the gas mixture having an etching gas and a polymer control gas. The polymer control gas includes a polymerizing fluorocarbon CxFy gas and a C—H bond containing gas. A plasma is formed with the gas mixture and a conformal polymer layer is deposited in the presence of the plasma on the patterned layer to form a reduced critical dimension in each opening. The reduced critical dimension is smaller than the corresponding critical dimension of the opening.

Abstract: Planarization methods and microelectronic structures formed therefrom are disclosed. The methods and structures use planarization materials comprising fluorinated compounds or acetoacetylated compounds. The materials are self-leveling and achieve planarization over topography without the use of etching, contact planarization, chemical mechanical polishing, or other conventional planarization techniques.

Abstract: The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursor and dopant precursor adsorb on the substrate surface. Oxygen plasma is used to convert the adsorbed silicon precursor and dopant precursor to doped silicon oxide.

Abstract: A method for forming a split gate flash cell memory device provides for establishing a floating gate region then using spacers or other hard mask materials that cover opposed edges of a gate electrode material in the gate region, to serve as hard masks during an etching operation that partially etches the gate electrode material which may be polysilicon. The gate electrode so produced serves as a floating gate electrode and includes a recessed central portion flanked by a pair of opposed upwardly extending fins which may terminate upwardly at an apex. A floating gate oxide is then formed by thermal oxidation and/or oxide deposition techniques.

Abstract: The present invention may be a semiconductor device including of a fluorinated insulating film and a SiCN film deposited on the fluorinated insulating film directly, wherein a density of nitrogen in the SiCN film decreases from interface between the fluorinated insulating film and the SiCN film. In the present invention, the SiCN film that is highly fluorine-resistant near the interface with the CFx film and has a low dielectric constant as a whole can be formed as a hard mask.

Abstract: Provided is a method of operating a film forming apparatus capable of suppressing generation of particles by improving an adhesion of a carbon film to surfaces of members which are formed of a quartz material and contact a processing space in a processing container. The method includes forming a carbon film on each of surfaces of a plurality of objects held by a holding unit in a processing container formed of a quartz material, wherein the method further includes forming an adhesion film to improve the adhesion of the carbon film, on surfaces of members which are formed of a quartz material and contact a processing space in the processing container. Accordingly, the adhesion of the carbon film to the surface of the member formed of a quartz material contacting the processing space in the processing container is improved, thereby suppressing generation of particles.

Abstract: A method of operating a film forming apparatus includes forming a carbon film on each of surfaces of a plurality of objects held by a holding unit in a processing container and performing a cleaning process with a cleaning gas to remove an unnecessary carbon film adhered on a inside of the processing container, wherein the method further includes, before the forming of the carbon film, forming, on a surface of a member contacting a processing space in the processing container, a tolerant pre-coating film which has a tolerance to the cleaning gas and improves adhesion of the carbon film to the surface of the member. Accordingly, the adhesion of the carbon film is improved, and further, the tolerant pre-coating film remains even when the cleaning process of removing the unnecessary carbon film is performed.

Abstract: The disclosure relates to a method of depositing amorphous carbon on a substrate using at least one carbon containing molecule having at least one carbon atom the method comprising the steps of supplying the carbon containing molecule and carrying out the deposition to thereby form a deposited amorphous carbon on the substrate, wherein a carbon to hydrogen ratio of the molecule is equal to or more than 0.7.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface and a second surface, and having a LSI on the first surface of the semiconductor substrate, a first insulating layer with an opening, the first insulating layer provided on the first surface of the semiconductor substrate, a conductive layer on the opening, the conductive layer being connected to the LSI, and a via extending from a second surface of the semiconductor substrate to the conductive layer through the opening, the via having a size larger than a size of the opening in a range from the second surface to a first interface between the semiconductor substrate and the first insulating layer, and having a size equal to the size of the opening in the opening.

Abstract: There is provided a method for forming a graphene layer. The method includes forming an article that comprises a carbon-containing self-assembled monolayer (SAM). A layer of nickel is deposited on the SAM. The article is heated in a reducing atmosphere and coolded. The heating and cooling steps are carried out so as to convert the SAM to a graphene layer.

Abstract: A semiconductor process includes the following steps. A substrate is provided. A dielectric layer having a high dielectric constant is formed on the substrate, wherein the steps of forming the dielectric layer include: (a) a metallic oxide layer is formed; (b) an annealing process is performed to the metallic oxide layer; and the steps (a) and (b) are performed repeatedly. Otherwise, the present invention further provides a semiconductor structure formed by said semiconductor process.

Abstract: Antimony oxide thin films are deposited by atomic layer deposition using an antimony reactant and an oxygen source. Antimony reactants may include antimony halides, such as SbCl3, antimony alkylamines, and antimony alkoxides, such as Sb(OEt)3. The oxygen source may be, for example, ozone. In some embodiments the antimony oxide thin films are deposited in a batch reactor. The antimony oxide thin films may serve, for example, as etch stop layers or sacrificial layers.

Abstract: A method for increasing adhesion between polysilazane and silicon nitride is disclosed, comprising, providing a substrate comprising a trench, forming a silicon nitride liner layer on a bottom surface and a sidewall of the trench, performing a treating process to the silicon nitride liner layer for producing a hydrophilic surface with OH groups that can increase adhesion between the silicon nitride liner layer and a subsequently formed polysilazane coating layer, and forming a polysilazane coating layer into the trench and on the silicon nitride liner layer.

Abstract: When forming strain-inducing dielectric material layers above transistors of different conductivity type, the patterning of at least one strain-inducing dielectric material may be accomplished on the basis of a process sequence in which a negative influence of a fluorine species in an oxygen plasma upon removing the resist mask is avoided or at least significantly suppressed. For example, a substantially oxygen-free plasma process may be applied for removing the resist material.

Abstract: A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500° C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800° C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches.

Abstract: A method of forming a film on a semiconductor substrate by plasma enhanced atomic layer deposition (PEALD), includes: introducing a nitrogen- and hydrogen-containing reactive gas and a rare gas into a reaction space inside which the semiconductor substrate is placed; introducing a precursor in pulses of less than 1.0-second duration into the reaction space wherein the reactive gas and the rare gas are introduced; exiting a plasma in pulses of less than 1.0-second duration immediately after the precursor is shut off; and maintaining the reactive gas and the rare gas as a purge of less than 2.0-second duration.

Abstract: An Al2O3 thin film layer is fabricated. Atmospheric pressure chemical vapor deposition (APCVD) is processed in a normal atmospheric pressure and a low temperature. On a surface of a p-type or n-type silicon crystal wafer having a purity between 5N (99.999%) and 9N (99.9999999%), the Al2O3 thin film layer is deposited and fabricated. The deposition and fabrication are done to obtain chemical passivation and field effect passivation. In this way, the present invention can be applied in solar cells and other photoelectric devices with reduced leakage of surface currents and improved photoelectric conversion.

Abstract: A method for producing semiconductor device includes: performing first, second and third exposures of a photoresist film formed on a semiconductor wafer via a mask; wherein: first, second and third shot regions respectively defined by the first, second and third exposures are aligned in a first direction; the mask has a shot region including a peripheral scribe region having a first and second side crossing the first direction; the photoresist film is of positive type, a first pattern is formed as a light shielding pattern disposed on the first side, and a second pattern is formed as a light transmitting region disposed on the second side; the first and second exposures are performed in such a manner that the first and second patterns do not overlap each other; and the second and third exposures are performed in such a manner that the first and second patterns overlap each other.

Abstract: A curable adhesive composition is disclosed comprising: at least one free radically polymerizable oligomer component; optionally at least one diluent monomer; at least one perfluorinated ether monomer; and a photoinitiator. The curable liquid adhesive is easily removable with low force and low adhesive transfer.

Abstract: A method for forming a single-phase multi-element film on a substrate in a reaction zone by PEALD repeating a single deposition cycle. The single deposition cycle includes: adsorbing a precursor on the substrate in the absence of reactant and plasma; decomposing the precursor adsorbed on the substrate by an inert gas plasma; and reacting the decomposed precursor with a reactant gas plasma in the presence of the inert gas plasma. The multi-element film contains silicon and at least two non-metal elements constituting a matrix of the film, the precursor contains silicon and optionally at least one non-metal element to be incorporated in the matrix, and the reactant gas contains at least one non-metal element to be incorporated in the matrix.

Abstract: Methods of treating the interior of a plasma region are described. The methods include a preventative maintenance procedure or the start-up of a new substrate processing chamber having a remote plasma system. A new interior surface is exposed within the remote plasma system. The (new) interior surfaces are then treated by sequential steps of (1) forming a remote plasma from hydrogen-containing precursor within the remote plasma system and then (2) exposing the interior surfaces to water vapor. Steps (1)-(2) are repeated at least ten times to complete the burn-in process. Following the treatment of the interior surfaces, a substrate may be transferred into a substrate processing chamber. A dielectric film may then be formed on the substrate by flowing one precursor through the remote plasma source and combining the plasma effluents with a second precursor flowing directly to the substrate processing region.

Abstract: A semiconductor device and its manufacturing method, wherein the NMOS device is covered by a layer of silicon nitride film having a high ultraviolet light absorption coefficient through PECVD, said silicon nitride film can well absorb ultraviolet light when being subject to the stimulated laser surface anneal so as to achieve a good dehydrogenization effect, and after dehydrogenization, the silicon nitride film will have a high tensile stress; since the silicon nitride film has a high ultraviolet light absorption coefficient, there is no need to heat the substrate, thus avoiding the adverse influences to the device caused by heating the substrate to dehydrogenize, and maintaining the heat budget brought about by the PECVD process.

Abstract: An excellent type of a film is realized by modifying conventional types of films.

Abstract: A semiconductor structure includes a substrate, an oxide layer, a metallic oxynitride layer and a metallic oxide layer. The oxide layer is located on the substrate. The metallic oxynitride layer is located on the oxide layer. The metallic oxide layer is located on the metallic oxynitride layer. In addition, the present invention also provides a semiconductor process for forming the semiconductor structure.

Abstract: In an imprint method according to embodiments, light that hardens a resist is irradiated to a light irradiation region near an alignment mark in order to prevent the resist from being filled in the alignment mark of a template, when the alignment process between the template and a substrate is performed. After the alignment process is completed, the resist is filled in the template pattern and the alignment mark, and then, light that hardens the resist is irradiated onto the template.

Abstract: A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate and an oxide layer is formed on the substrate without the fin-shaped structure forming thereon. A thermal treatment process is performed to form a melting layer on at least a part of the sidewall of the fin-shaped structure.

Abstract: A method for depositing a silicon oxide layer on a substrate including a silicon region and a silicon-germanium region, including the steps of: forming a very thin silicon layer having a thickness ranging from 0.1 to 1 nm above silicon-germanium; and depositing a silicon oxide layer on the substrate.

Abstract: A galvanic isolation system provides galvanic isolation in digital transfer integrated circuits by using conductivity modulation of the semiconductor substrate. Modulation of the conductivity of the substrate affects eddy current losses of a (differential) RF inductor that is isolated from the substrate by a sufficient amount of dielectric material, which provides a basis for signal transfer from the modulated substrate to the inductor across the isolation barrier.

Abstract: A carbon-rich carbon boron nitride dielectric film having a dielectric constant of equal to, or less than 3.6 is provided that can be used as a component in various electronic devices. The carbon-rich carbon boron nitride dielectric film has a formula of CxByNz wherein x is 35 atomic percent or greater, y is from 6 atomic percent to 32 atomic percent and z is from 8 atomic percent to 33 atomic percent.

Abstract: A film deposition method includes the steps of: coating a solution containing a polysilane compound on a substrate to form a coating film and then carrying out a first thermal treatment in an inert atmosphere, thereby forming the coating film into a silicon film; forming a coating film containing a polysilane compound on the silicon film and then carrying out a second thermal treatment in an inert atmosphere or a reducing atmosphere, thereby forming the coating film into a silicon oxide precursor film; and carrying out a third thermal treatment in an oxidizing atmosphere, thereby forming the silicon oxide precursor film into a silicon oxide film and simultaneously densifying the silicon film.

Abstract: A method of forming a silicon oxide film on silicon exposed on a surface of a workpiece includes mounting the workpiece on a mounting table in a processing chamber; generating plasma of a process gas containing oxygen by supplying the process gas into the processing chamber; applying a bias to the workpiece by supplying high-frequency power to the mounting table; and forming the silicon oxide film by applying the plasma to the biased workpiece and oxidizing the silicon. A ratio of oxygen in the process gas is set to be in the range of 0.1% to 10%. A pressure in the processing chamber is set to be in the range of 1.3 Pa to 266.6 Pa upon forming the silicon oxide film. An output of the high-frequency power is set to be in the range of 0.14 W/cm2 to 2.13 W/cm2 per unit area of the workpiece.

Abstract: A method of manufacturing a semiconductor device, includes a wafer grinding step of, by means of a revolving grinding stone, forming a thinned portion in a wafer while at the same time forming a slope surrounding said thinned portion, wherein during said formation of said slope, said grinding stone is positioned so that there is always a space between said slope and the facing side of said grinding stone, wherein said thinned portion is thinner than a peripheral portion of said wafer, and wherein said slope extends along and defines an inner circumferential side of said peripheral portion and forms an angle of 75° or more but less than 90° with respect to a main surface of said wafer. The method of manufacturing a semiconductor device further includes a step of forming a semiconductor device in said thinned portion.

Abstract: Semiconductor devices and methods for manufacturing the semiconductor devices are disclosed. A semiconductor device includes a substrate, a fin formed above the substrate with a semiconductor layer formed between the substrate and the fin, and a gate stack crossing over the fin. The fin and the semiconductor layer may include different materials and have etching selectivity with respect to each other. A patterning of the fin can be stopped reliably on the semiconductor layer. Therefore, it is possible to better control the height of the fin and thus the channel width of the final device.

Abstract: A wafer holder and temperature controlling arrangement has a metal circular wafer carrier plate, which covers a heater compartment. In the heater compartment a multitude of heater lamp tubes is arranged, which directly acts upon the circular wafer carrier plate. Latter is drivingly rotatable about the central axis. A wafer is held on the circular wafer carrier plate by means of a weight-ring residing upon the periphery of a wafer deposited on the wafer carrier plate.

Abstract: There is provided a method for manufacturing a semiconductor device, including forming an insulating film having a prescribed composition and a prescribed film thickness on a substrate by alternately performing the following steps prescribed number of times: supplying one of the sources of a chlorosilane-based source and an aminosilane-based source to a substrate in a processing chamber, and thereafter supplying the other source, to form a first layer containing silicon, nitrogen, and carbon on the substrate; and supplying a reactive gas different from each of the sources, to the substrate in the processing chamber, to modify the first layer and form a second layer.

Abstract: A semiconductor device manufacturing method includes forming a transistor over a semiconductor substrate; forming a first silicon nitride film covering the transistor over the semiconductor substrate; supplying a NH4F radical to the first silicon nitride film; making thermal processing on the first silicon nitride film after the supplying the NH4F radical; and forming a second silicon nitride film over the first silicon nitride film after the thermal processing.

Abstract: A semiconductor process is described as follows. A material layer is provided on a substrate. A low-temperature oxidation treatment is performed to the material layer. A photoresist layer is formed on the material layer after the low-temperature oxidation treatment. The photoresist layer is patterned.

Abstract: Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.

Abstract: A multiphase ultra low k dielectric process incorporating an organo-silicon precursor including an organic porogen, high frequency radio frequency power just above plasma initiation in a PECVD chamber and energy post treatment. A porous SiCOH dielectric material having a k less than 2.7 and a modulus of elasticity greater than 7 GPa. A graded carbon adhesion layer of SiO2 and porous SiCOH.

Abstract: A microfabricated device is fabricated by depositing a first metal layer on a substrate to provide a first electrode of an electrostatic actuator, depositing a first structural polymer layer over the first metal layer, depositing a second metal layer over said first structural polymer layer to form a second electrode of the electrostatic actuator, depositing an insulating layer over said first structural polymer layer, planarizing the insulating layer, etching the first structural polymer layer through the insulating layer and the second metal layer to undercut the second metal layer, providing additional pre-formed structural polymer layers, at least one of which has been previously patterned, and finally bonding the additional structural layers in the form of a stack over the planarized second insulating layer to one or more microfluidic channels. The technique can also be used to make cross over channels in devices without electrostatic actuators, in which case the metal layers can be omitted.

Abstract: A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The porogen comprises an organic ring structure with fewer than fifteen carbons and a large percentage of single bonds. Additionally, the porogen may have a viscosity greater than 1.3 and a Reynolds numbers less than 0.5.

Abstract: Methods of forming a semiconductor structure include providing an insulation layer on a semiconductor layer and diffusing cesium ions into the insulation layer from a cesium ion source outside the insulation layer. A MOSFET including an insulation layer treated with cesium ions may exhibit increased inversion layer mobility.

Abstract: Lithography methods and devices are shown that include a semiconductor structure such as a mask. Methods and devices are shown that include a pattern of mask features and a composite feature. Selected mask features include doubled mask features. Methods and devices shown may provide varied feature sizes (including sub-resolution) with a small number of processing steps.

Abstract: Embodiments of the invention provide methods for forming dielectric materials on a substrate. In one embodiment, a method includes exposing a substrate surface to a first oxidizing gas during a pretreatment process, wherein the first oxidizing gas contains a mixture of ozone and oxygen having an ozone concentration within a range from about 1 atomic percent to about 50 atomic percent and forming a hafnium-containing material on the substrate surface by exposing the substrate surface sequentially to a deposition gas and a second oxidizing gas during an atomic layer deposition (ALD) process, wherein the deposition gas contains a hafnium precursor, the second oxidizing gas contains water, and the hafnium-containing material has a thickness within a range from about 5 ? to about 300 ?. In one example, the hafnium-containing material contains hafnium oxide having the chemical formula of HfOx, whereas x is less than 2, such as about 1.8.