Abstract: One illustrative example of a transistor device disclosed herein includes, among other things, a gate structure, first and second spacers positioned adjacent opposite sides of the gate structure, and a multi-layer gate cap structure positioned above the gate structure and the upper surface of the spacers. The multi-layer gate cap structure includes a first gate cap material layer positioned on an upper surface of the gate structure and on the upper surfaces of the first and second spacers, a first high-k protection layer positioned on an upper surface of the first gate cap material layer and a second gate cap material layer positioned on an upper surface of the high-k protection layer. The first and second gate cap layers comprise different materials than the first high-k protection layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a fin-type pattern formed on a substrate and including first and second sidewalls, which are defined by a trench, a field insulating film placed in contact with the first and second sidewalls and filling the trench, and an epitaxial pattern formed on the fin-type pattern and including a first epitaxial layer and a second epitaxial layer, which is formed on the first epitaxial layer.

Abstract: A dual layer shallow isolation trench region for semiconductor structures including field effect transistors (FETs) and methods for making the same. The first layer of the shallow trench isolation region includes a dielectric material disposed between adjacent FETs. The second layer is an etch resistant material disposed on the dielectric material and has an increased etch resistance relative to the dielectric material. The etch resistant material overlays the shallow trench region to provide the dual layer shallow trench isolation region, which permits self-alignment of contacts to the source and/or drain of FETs.

Abstract: Semiconductor devices may include a plurality of active fins each extending in a first direction on a substrate, a gate structure extending on the active fins in a second direction, and a first source/drain layer on first active fins of the active fins adjacent the gate structure. At least one of two opposing sidewalls of a cross-section of the first source/drain layer taken along the second direction may include a curved portion having a slope with respect to an upper surface of the substrate. The slope may decrease from a bottom toward a top thereof.

Abstract: Representative embodiments provide an InAlN/GaN MISHFET having a predetermined breakdown voltage, calibrated to a permittivity-thickness parameter and selectable before or during transistor fabrication, which can be greater than 700 V for a normally-off InAlN/GaN MISHFET. Representative embodiments include a first dielectric layer coupled to a gate and to an InAlN barrier layer, a second dielectric layer, and an optional third dielectric layer. The first dielectric layer comprises a first dielectric material having a first predetermined thickness and a first relative permittivity.

Abstract: A method is presented for forming a semiconductor structure. The method includes forming a plurality of vertical fins over a semiconductor layer formed over a substrate, depositing an oxide over the plurality of fins, and applying a cutting mask over a portion of the plurality of fins. The method further includes removing the oxide from the exposed portion of the plurality of fins, depositing a replacement gate stack, and etching portions of the replacement gate stack to remove exposed fins, the exposed fins forming recesses within the semiconductor layer. The method further includes depositing a spacer over the exposed fins and the recesses formed by the removed fins. A portion of the plurality of fins are cut during etching of the replacement gate stack and a portion of the oxide is removed before deposition of the replacement gate stack.

Abstract: The present disclosure relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor. The semiconductor device includes a substrate; two fins located on the substrate and extending along a first direction; an isolation material layer surrounding the fins, comprising a first isolation regions located at an end region between the two fins along the first direction, and a second isolation region located at sides of the fins along a second direction that is different from the first direction, wherein an upper surface of the first isolation region substantially align with an upper surfaces of the fins, and an upper surface of the second isolation region is lower than the upper surface of the fins; and a first insulating layer on the first isolation region.

Abstract: A method of making a semiconductor device includes forming a fin in a substrate; depositing a first spacer material to form a first spacer around the fin; depositing a second spacer material to form a second spacer over the first spacer; recessing the first spacer and the second spacer; removing the first spacer; and performing an epitaxial growth process to form epitaxial growth on an end of the fin, along a sidewall of the fin, and adjacent to the fin.

Abstract: A method of manufacturing a semiconductor device, includes forming a fin structure on a main surface of semiconductor substrate, the fin structure including a silicon material; forming a first gate electrode over the fin structure via a first insulating film, and forming a second gate electrode over the fin structure via a second insulating film having a charge accumulating part, such that the second gate electrode is disposed along a sidewall of the first gate electrode in a plan view; forming source and drain regions over a surface of the fin structure at both sides of a structure defined by the first and second gate electrodes; performing a first heat treatment to the semiconductor substrate to keep the semiconductor substrate at a first predetermined temperature; and forming a first metal film on the fin structure by sputtering in condition that the semiconductor substrate is at the first predetermined temperature.

Abstract: To provide a novel light-emitting element or a novel light-emitting device with high emission efficiency and low power consumption, a light-emitting element having a plurality of light-emitting layers between a pair of electrodes includes a lower electrode, a first light-emitting layer over the lower electrode, a charge-generation layer over the first light-emitting layer, a second light-emitting layer over the charge-generation layer, and an upper electrode over the second light-emitting layer. An emission spectrum of the first light-emitting layer peaks at a longer wavelength than an emission spectrum of the second light-emitting layer. A distance of between a bottom surface of the upper electrode and a bottom surface of the first light-emitting layer is less than or equal to 130 nm.

Abstract: A method of forming a fin field effect transistor (finFET), including forming a temporary gate structure having a sacrificial gate layer and a dummy gate layer on the sacrificial gate layer, forming a gate spacer layer on each sidewall of the temporary gate structure, forming a source/drain spacer layer on the outward-facing sidewall of each gate spacer layer, removing the dummy gate layer to expose the sacrificial gate layer, removing the sacrificial gate layer to form a plurality of recessed cavities, and forming a gate structure, where the gate structure occupies at least a portion of the plurality of recessed cavities.

Abstract: A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.

Abstract: A semiconductor structure includes a substrate, and a replacement metal gate (RMG) structure is attached to the substrate. The RMG structure includes a lower portion and an upper tapered portion. A source junction is disposed on the substrate and attached to a first low-k spacer portion. A drain junction is disposed on the substrate and attached to a second low-k spacer portion. A first oxide layer is disposed on the source junction, and attached to the first low-k spacer portion. A second oxide layer is disposed on the drain junction, and attached to the second low-k spacer portion. A cap layer is disposed on a top surface layer of the RMG structure and attached to the first oxide layer and the second oxide layer.

Abstract: Systems and methods in accordance with embodiments of the invention implement select devices constructed from 2D materials. In one embodiment, a crossbar memory system includes: a first set of connection lines; a second set of connection lines; and an array of memory cells, each memory cell including: a select device; and a memory device; where each memory cell is coupled to a unique combination of: at least one connection line from the first set of connection lines, and at least one connection line from the second set of connection lines; and where at least one select device includes a 2D material.

Abstract: Fabricating a transistor includes receiving a semiconductor structure including a source/drain, a gate, and a spacer disposed between the source/drain and the gate, a trench contact disposed on the source/drain, a self-aligned cap disposed on the gate, and an interlevel dielectric layer disposed on the spacer, self-aligned cap, and trench contact. A source/drain contact is formed within the interlevel dielectric layer in contact with the trench contact and forming a gate contact in contact with the gate. The interlevel dielectric layer is removed from the spacer, self-aligned cap, and source/drain contact. The self-aligned cap and the spacer is selectively etched. A dielectric liner of a first dielectric material is deposited upon a top of the gate, the trench contact and the S/D contact. The first dielectric material of the dielectric liner pinches off a gap between the gate and the trench contact to form an air spacer therebetween.

Abstract: A control system is presented for use in measuring one or more parameters of a sample. The control system comprises an input utility and a processor utility. The input utility is configured for receiving input data including first data comprising X-ray Diffraction or High-Resolution X-ray Diffraction (XRD) response data of the sample indicative of a material distribution in the sample, and second data comprising optical response data of the sample to incident light indicative of at least a geometry of the sample. The processor utility is configured and operable for processing and analyzing one of the first and second data for optimizing the other one of the first and second data, and utilizing the optimized data for determining said one or more parameters of the sample including a strain distribution in the sample.

Abstract: An infrared detector includes a substrate, a light blocking layer on the substrate, a lower electrode on the light blocking layer, the lower electrode electrically connected to the light blocking layer, a lower insulating layer on the light blocking layer, a first semiconductor layer on the lower insulating layer, a first source electrode and a first drain electrode on the first semiconductor layer, an upper insulating layer on the first semiconductor layer, and a first gate electrode on the upper insulating layer, the first gate electrode electrically connected to the lower electrode, where the first semiconductor layer includes a zinc and a nitrogen, and the first semiconductor layer is configured to generate electric charges by reacting with an infrared ray.

Abstract: A semiconductor device is provided. The provided semiconductor device may have enhanced reliability and operating characteristics. The semiconductor device includes a substrate, a device isolation film formed within the substrate, a first gate structure formed within the substrate, a recess formed on at least one side of the first gate structure and within the substrate and the device isolation film, the recess comprising an upper portion and a lower portion wherein the lower portion of the recess is formed within the substrate and the upper portion of the recess is formed across the substrate and the device isolation film, a buried contact filling the recess and an information storage electrically connected to the buried contact.

Abstract: A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.

Abstract: The present invention discloses an OPC method for a shallow ion implanting layer, comprising the following steps of: selecting a valid device region in an implanting active region in a shallow ion implanting original layout; selecting a region in the valid device region which is contacted with a poly-silicon pattern in a poly-silicon layer, as a poly-silicon contacting region; extending the length and width of the poly-silicon contacting region and the non poly-silicon contacting region, to form a new poly-silicon contacting region and a new non poly-silicon contacting region; combining a gap portion which an interval between any two new poly-silicon contacting regions and/or new non poly-silicon contacting regions after extending is smaller than or equal to G and completely fallen in the STI region, with the poly-silicon contacting regions and non poly-silicon contacting regions after extending, to form a correction target layer; performing a model-based OPC routine on the correction target layer, to obtain

Abstract: An electronic part mounting heat-dissipating substrate which includes: a conductor plate which is formed on lead frames of wiring pattern shapes; and an insulating member which is provided between the lead frames of the wiring pattern shapes on the conductor plate; wherein a plate surface of a part arrangement surface of the conductor plate and a top surface of the insulating member at a side of the part arrangement surface form one continuous surface, wherein a plate surface of a back surface of the part arrangement surface of the conductor plate and a top surface of the insulating member at a side of the back surface at the part arrangement surface-side are formed in an identical plane, wherein the substrate is formed in a circular shape.

Abstract: An apparatus for detecting difference in operating characteristics of a main circuit by using a replica circuit is presented. In one exemplary case, a sensed difference in operating characteristics of the two circuits is used to drive a tuning control loop to minimize the sensed difference. In another exemplary case, several replica circuits of the main circuit are used, where each is isolated from one or more operating variables that affect the operating characteristic of the main circuit. Each replica circuit can be used for sensing a different operating characteristic, or, two replica circuits can be combined to sense a same operating characteristic.

Abstract: A method of manufacturing a semiconductor device is provided. A stacked structure including one or more sacrificial layers and one or more semiconductor layers are stacked on a substrate is formed. A dummy gate structure including a dummy gate and a dummy spacer on the stacked structure is formed. The stacked structure is etched using the dummy gate structure to form a first recess. The one or more sacrificial layers are etched. The dummy spacer is removed. A spacer film is formed on the dummy gate, the one or more semiconductor layer and the one or more sacrificial layers. The semiconductor layer and spacer film are etched to form a second recess using the dummy gate and spacer film. An external spacer formed on the dummy gate and an internal spacer formed on the one or more sacrificial layers are formed. A source/drain region is formed in the second recess.

Abstract: After forming an interlevel dielectric (ILD) layer over a semiconductor material portion located on a substrate, a gate trench is formed extending through the ILD layer to expose a channel region of the semiconductor material portion. A gate structure is then formed within the gate trench. Epitaxial semiconductor regions are subsequently formed within source/drain contact openings formed on opposite sides of the gate structure, followed by forming source/drain contact structures on the epitaxial semiconductor regions.

Abstract: A technique relates to forming a semiconductor device. A starting semiconductor device having a fin structure patterned in a substrate, and a gate formed over the fin structure, the gate having a mid-region and an end-region is first provided. A trench is then patterned over the mid-region of the gate and a trench is patterned over the end-region of the gate. The patterned trenches are then etched over the mid-region of the gate and the end-region of the gate to form the trenches. A conformal low-k dielectric layer can then be deposited over the structure to fill the trenches and pinch off the trench formed in the mid-region and the trench formed in the end-region.

Abstract: A method for manufacturing a semiconductor device comprises forming a first diffusion stop layer on a bulk semiconductor substrate, forming a doped semiconductor layer on the first diffusion stop layer, forming a second diffusion stop layer on the doped semiconductor layer, forming a fin layer on the doped semiconductor layer, patterning the first and second diffusion stop layers, the doped semiconductor layer, the fin layer and a portion of the bulk substrate, oxidizing the doped semiconductor layer to form an oxide layer, and forming a dielectric on the bulk substrate adjacent the patterned portion of the bulk substrate, the patterned first diffusion stop layer and the oxide layer.

Abstract: A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides of the channel region. The semiconductor device may further include a composite gate sidewall spacer present on a sidewall of the gate structure. The composite gate sidewall spacer may include a first composition portion having an air gap encapsulated therein, and a second composition portion that is entirely solid and present atop the first composition portion.

Abstract: Described herein is a technique capable of suppressing the deviation in the characteristic of the semiconductor device. A method of manufacturing a semiconductor device may include: (a) receiving a data obtained by measuring a width of a first pillar between first grooves in a center region of a substrate and a width of a second pillar between second grooves in a peripheral region of the substrate; and (b) forming a width adjusting film on surfaces of the first grooves and the second grooves such that a sum of the width of the first pillar and a thickness of a first portion of the width adjusting film in the center region and a sum of the width of the second pillar and a thickness of a second portion of the width adjusting film in the peripheral region are within a predetermined range.

Abstract: A semiconductor device includes a substrate, a first insulating structure, a second insulating structure, at least one first active semiconductor fin, and at least one second active semiconductor fin. The first insulating structure and the second insulating structure are disposed on the substrate. The first active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the first insulating structure. The second active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the second insulating structure. The protruding portion of the first active semiconductor fin and the protruding portion of the second active semiconductor fin have different heights.

Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a first portion of the isolation region being between the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a gate seal spacer on sidewalls of the gate structure, a first portion of the gate seal spacer being on the first portion of the isolation region between the first fin and the second fin, and a source/drain region on the first fin and the second fin adjacent the gate structure.

Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, and a conductive plug. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure while leaving a gap between the conductive plug and the spacer.

Abstract: A circuit can include a field-effect transistor having a body, a drain, a gate, and a source. In an embodiment, the circuit can further include a bipolar transistor having a base and a collector, wherein the collector of the bipolar transistor is coupled to the body of the field-effect transistor; and the drain of the field-effect transistor is coupled to the base of the bipolar transistor. In another embodiment, the circuit can include a diode having an anode and a cathode, wherein the source of the field-effect transistor is coupled to the anode of the diode, and the gate of the field effect transistor is coupled to the cathode of the diode. In another aspect, an electronic device can include one or more physical structures that correspond to components within the circuits.

Abstract: A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a gate structure and a source drain structure. A recess is formed at least partially in the first dielectric layer. A protection layer is formed at least on a sidewall of the recess. The recess is deepened to expose the source drain structure. A bottom conductor is formed in the recess and is electrically connected to the source drain structure. The protection layer is removed to form a gap between the bottom conductor and the sidewall of the recess.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistors with improved channel mobility and methods of manufacture. A structure includes: a curved beam structure formed from at least one stressed material; a cavity below the curved beam structure; and at least one semiconductor device on a top portion or a bottom portion of the curved beam structure whose carrier mobility is increased or decreased by a curvature of the curved beam structure.

Abstract: A semiconductor device includes a semiconductor substrate having a plurality of semiconductor fins formed on an upper surface thereof. An epitaxial material is formed on the upper surface of the semiconductor substrate and on an outer surface of the semiconductor fins. The epitaxial material includes an epi upper surface having a lower region that contacts the semiconductor fins and an upper region formed above the lower region. The upper region extends parallel with an upper surface of the semiconductor fins.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first gate stack over a substrate. The first gate stack includes a gate electrode, a first hard mask (HM) disposed over the gate electrode, and sidewall spacers along sidewalls of the first gate stack. The method also includes forming a first dielectric layer over the first gate stack, forming a second HM over the first HM and top surfaces of sidewall spacers, forming a second dielectric layer over the second HM and the first dielectric layer and removing the second and first dielectric layers to form a trench to expose a portion of the substrate while the second HM is disposed over the first gate stack.

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on the sidewall of the gate stack structure, and the gate spacers include a top portion and a bottom portion adjoined to the top portion, and the bottom portion slopes to a top surface of the substrate. The semiconductor device structure further includes an epitaxial structure formed adjacent to the gate spacers, and the epitaxial structure is formed below the gate spacers.

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element formed in or on the semiconductor substrate, a metal layer connected to the semiconductor element, and a passivation film that protects the semiconductor element. The passivation film is formed by alternately stacking a first insulation film that has larger tensile stress and a second insulation film that has smaller tensile stress. Each of the first insulation film and the second insulation film is one of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film. The passivation film as a whole generates tensile stress.

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a first semiconductor layer, a second dielectric layer and a second semiconductor layer. The first dielectric layer is disposed on the substrate and includes at least one first trench formed in the first dielectric layer. The first semiconductor layer is disposed on the first dielectric layer and within the at least one first trench. The second dielectric layer is disposed on the first semiconductor layer and includes at least one second trench formed in the second dielectric layer, wherein in a planar view, the at least one first trench and the at least one second trench are not overlapped with each other. The second semiconductor layer is disposed on the second dielectric layer and within the at least one second trench.

Abstract: A semiconductor device and a method of forming the semiconductor device is disclosed. A sacrificial film is used to pattern a contact to a semiconductor structure, such as a contact to a source/drain region of a transistor. The contact may include a tapered profile along an axis parallel to the gate electrode such that an outermost width of the contact decreases as the contact extends away from the source/drain region.

Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material.

Abstract: Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.

Abstract: A method of making a semiconductor device includes forming a fin in a substrate; depositing a first spacer material to form a first spacer around the fin; depositing a second spacer material to form a second spacer over the first spacer; recessing the first spacer and the second spacer; removing the first spacer; and performing an epitaxial growth process to form epitaxial growth on an end of the fin, along a sidewall of the fin, and adjacent to the fin.

Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided. The method includes providing a semiconductor substrate including a first region and a second region, and forming a plurality of fins on the semiconductor substrate in the first region and the second region. The method also includes forming a first barrier layer on surfaces of the fins in the first region, and forming an isolation fluid layer on the semiconductor substrate to cover the first barrier layer in the first region and to cover the fins in the second region. Further, the method includes forming an isolation film and a by-product layer by an oxygen-containing annealing process respectively from the isolation fluid layer and sidewalls of the fins in the second region.

Abstract: A trench gate type MOS gate structure is provided in an active region on a substrate front surface side, and a floating p-type region is provided in a mesa region between trenches. A groove is provided distanced from the trench in a surface layer on the substrate front surface side of the floating p-type region. A second gate electrode is provided across an insulation layer in the interior portion of the groove. The second gate electrode covers the surface on the substrate front surface side of the floating p-type region. Thus, the second gate electrode is embedded in a surface layer on the substrate front surface side of the floating p-type region between the floating p-type region and an interlayer dielectric, whereby the substrate front surface is flattened. Controllability of turn-on di/dt is high, mirror capacitance is low, and an element structure having an intricate pattern can be formed.

Abstract: Semiconductor devices, FinFET devices and methods of forming the same are provided. In accordance with some embodiments, a semiconductor device includes a substrate, a first gate stack, a spacer, a first dielectric layer, a shielding layer and a connector. The first gate stack is over the substrate. The spacer is disposed on and contacted to at least one sidewall of the first gate stack. The first dielectric layer is aside the spacer. The shielding layer covers a top surface of the spacer and a top surface of the first dielectric layer. The connector contacts a portion of a top surface of the first gate stack.

Abstract: An embodiment is a semiconductor device comprising a first gate structure over a semiconductor substrate, a first etch stop layer (ESL) over the semiconductor substrate and the first gate, the first ESL having a curved top surface, and a first inter-layer dielectric (ILD) on the first ESL, the first ILD having a curved top surface. The semiconductor device further comprises a second ESL on the first ILD, the second ESL having a curved top surface, and a second ILD on the second ESL.

Abstract: A finFET device and a method of forming are provided. The device includes a transistor comprising a gate electrode and a first source/drain region next to the gate electrode, the gate electrode being disposed over a first substrate. The device also includes a first dielectric layer extending along the first source/drain region, and a second dielectric layer overlying the first dielectric layer. The device also includes a contact disposed in the first dielectric layer and in the second dielectric layer, the contact contacting the gate electrode and the first source/drain region. A first portion of the first dielectric layer extends between the contact and the gate electrode. The contact extends along a sidewall of the first portion of the first dielectric layer and a first surface of the first portion of the first dielectric layer, the first surface of the first portion being farthest from the first substrate.

Abstract: A transistor device includes a substrate; a source region and a drain region formed over the substrate; and a source/drain contact formed in contact with at least one of the source region and the drain region, the source/drain contact including a conductive metal and a bilayer disposed between the conductive metal and the at least one of the source and drain region, the bilayer including a metal oxide layer in contact with the conductive metal, and a silicon dioxide layer in contact with the at least one of the source and drain region.

Abstract: A method of forming a semiconductor structure includes forming a silicon-germanium layer on a semiconductor region of a substrate having a specific concentration of germanium atoms. The semiconductor region and the silicon-germanium layer are annealed to induce a non-homogenous thermal diffusion of germanium atoms from the silicon-germanium layer into the semiconductor region to form a graded silicon-germanium region. Another method of forming a semiconductor structure includes etching a semiconductor region of the substrate to form a thinned semiconductor region. A silicon-germanium layer is formed on the thinned semiconductor region having a graded germanium concentration profile.