Having Insulated Electrode (e.g., Mosfet, Mos Diode) Patents (Class 257/288)
- With means for preventing charge leakage due to minority carrier generation (e.g., alpha generated soft error protection or "dark current" leakage protection) (Class 257/297)
- Capacitor for signal storage in combination with non-volatile storage means (Class 257/298)
- Structure configured for voltage converter (e.g., charge pump, substrate bias generator) (Class 257/299)
- Capacitor coupled to, or forms gate of, insulated gate field effect transistor (e.g., non-destructive readout dynamic memory cell structure) (Class 257/300)
- Capacitor in trench (Class 257/301)
- Stacked capacitor (Class 257/306)
- With high dielectric constant insulator (e.g., Ta 2 O 5 ) (Class 257/310)
- Storage Node isolated by dielectric from semiconductor substrate (Class 257/311)
- Voltage variable capacitor (i. e., capacitance varies with applied voltage) (Class 257/312)
- Inversion layer capacitor (Class 257/313)
- Vertical channel or double diffused insulated gate field effect device provided with means to protect against excess voltage (e.g., gate protection diode) (Class 257/328)
- Gate controls vertical charge flow portion of channel (e.g., VMOS device) (Class 257/329)
- Active channel region has a graded dopant concentration decreasing with distance from source region (e.g., double diffused device, DMOS transistor) (Class 257/335)
- With lightly doped portion of drain region adjacent channel (e.g., LDD structure) (Class 257/344)
- With means to prevent sub-surface currents, or with non-uniform channel doping (Class 257/345)
- Gate electrode overlaps the source or drain by no more than depth of source or drain (e.g., self-aligned gate) (Class 257/346)
- Depletion mode field effect transistor (Class 257/348)
- With means (e.g., a buried channel stop layer) to prevent leakage current along the interface of the semiconductor layer and the insulating substrate (Class 257/349)
- Insulated electrode device is combined with diverse type device (e.g., complementary MOSFETs, FET with resistor, etc.) (Class 257/350)
- Substrate is single crystal insulator (e.g., sapphire or spinel) (Class 257/352)
- Complementary insulated gate field effect transistors (Class 257/369)
- Combined with bipolar transistor (Class 257/378)
- Combined with passive components (e.g., resistors) (Class 257/379)
- With contact to source or drain region of refractory material (e.g., polysilicon, tungsten, or silicide) (Class 257/382)
- With means to reduce parasitic capacitance (Class 257/386)
- Matrix or array of field effect transistors (e.g., array of FETs only some of which are completed, or structure for mask programmed read-only memory (ROM)) (Class 257/390)
- Insulated gate field effect transistors of different threshold voltages in same integrated circuit (e.g., enhancement and depletion mode) (Class 257/392)
- Insulated gate field effect transistor adapted to function as load element for switching insulated gate field effect transistor (Class 257/393)
- With means to prevent parasitic conduction channels (Class 257/394)
- With specified physical layout (e.g., ring gate, source/drain regions shared between plural FETs, plural sections connected in parallel to form power MOSFET) (Class 257/401)