Device Having Semiconductor Body Comprising Group Iv Elements Or Group Iii-v Compounds With Or Without Impurities, E.g., Doping Materials (epo) Patents (Class 257/E21.085)

  • Publication number: 20130049177
    Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Applicant: Aeroflex Colorado Springs Inc.
    Inventors: David B. Kerwin, Joseph M. Benedetto
  • Publication number: 20130049178
    Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Applicant: Aeroflex Colorado Springs Inc.
    Inventors: David B. Kerwin, Joseph Benedetto
  • Publication number: 20130044782
    Abstract: Optical devices having a structured active region configured for selected wavelengths of light emissions are disclosed.
    Type: Application
    Filed: July 13, 2012
    Publication date: February 21, 2013
    Applicant: SORAA, Inc.
    Inventor: James W. Raring
  • Patent number: 8361885
    Abstract: A method of fabricating group-III nitride semiconductor laser device includes: preparing a substrate comprising a hexagonal group-III nitride semiconductor and having a semipolar principal surface; forming a substrate product having a laser structure, an anode electrode, and a cathode electrode, where the laser structure includes a semiconductor region and the substrate, where the semiconductor region is formed on the semipolar principal surface; scribing a first surface of the substrate product in a direction of an a-axis of the hexagonal group-III nitride semiconductor to form first and second scribed grooves; and carrying out breakup of the substrate product by press against a second surface of the substrate product, to form another substrate product and a laser bar.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: January 29, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yusuke Yoshizumi, Shimpei Takagi, Takatoshi Ikegami, Masaki Ueno, Koji Katayama
  • Publication number: 20130003769
    Abstract: A gallium nitride-based semiconductor laser device with reduced threshold current. The gallium nitride-based semiconductor laser device is provided with an n-type cladding layer, an n-side light guide layer, an active layer, a p-side light guide layer, and a p-type cladding layer. The n-side light guide layer and the p-side light guide layer both contain indium. Each of indium compositions of the n-side light guide layer and the p-side light guide layer is not less than 2% and not more than 6%. A film thickness of the n-type cladding layer is in the range of not less than 65% and not more than 85% of a total of the film thickness of the n-type cladding layer and a film thickness of the p-type cladding layer 23.
    Type: Application
    Filed: March 27, 2012
    Publication date: January 3, 2013
    Applicants: SONY CORPORATION, SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Tetsuya Kumano, Masaki Ueno, Takashi Kyono, Yohei Enya, Katsunori Yanashima, Kunihiko Tasai, Hiroshi Nakajima
  • Patent number: 8314422
    Abstract: A light emitting device is provided. The light emitting device includes a light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, a first dielectric layer over a cavity where a part of the light emitting structure is removed, a second electrode layer over the first dielectric layer, a second dielectric layer over the light emitting structure above the cavity, and a first electrode over the second dielectric layer.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: November 20, 2012
    Assignee: LG Innotek Co., Ltd.
    Inventor: Sung Min Hwang
  • Patent number: 8299565
    Abstract: Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Lidija Sekaric, Tymon Barwicz, Dureseti Chidambarrao
  • Patent number: 8294245
    Abstract: Affords a GaN single-crystal mass, a method of its manufacture, and a semiconductor device and method of its manufacture, whereby when the GaN single-crystal mass is being grown, and when the grown GaN single-crystal mass is being processed into a substrate or like form, as well as when an at least single-lamina semiconductor layer is being formed onto a single-crystal GaN mass in substrate form to manufacture semiconductor devices, cracking is controlled to a minimum. The GaN single-crystal mass 10 has a wurtzitic crystalline structure and, at 30° C., its elastic constant C11 is from 348 GPa to 365 GPa and its elastic constant C13 is from 90 GPa to 98 GPa; alternatively its elastic constant C11 is from 352 GPa to 362 GPa.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: October 23, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideaki Nakahata, Shinsuke Fujiwara, Takashi Sakurada, Yoshiyuki Yamamoto, Seiji Nakahata, Tomoki Uemura
  • Publication number: 20120261776
    Abstract: A method and system provide a magnetic junction usable in a magnetic device. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, a free layer, and at least one damping reduction layer. The free layer has an intrinsic damping constant. The nonmagnetic spacer layer is between the pinned layer and the free layer. The at least one damping reduction layer is adjacent to at least a portion of the free layer and configured to reduce the intrinsic damping constant of the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.
    Type: Application
    Filed: December 20, 2011
    Publication date: October 18, 2012
    Applicant: Samsung Electronics Co., LTD.
    Inventors: Xueti Tang, Vladimir Nikitin, Dmytro Apalkov, Kiseok Moon, Steven M. Watts
  • Patent number: 8258056
    Abstract: A method of lithography patterning includes forming a first material layer on a substrate; forming a first patterned resist layer including at least one opening therein on the first material layer; forming a second material layer on the first patterned resist layer and the first material layer; forming a second patterned resist layer including at least one opening therein on the second material layer; and etching the first and second material layers uncovered by the first and second patterned resist layers.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: September 4, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ching-Yu Chang
  • Patent number: 8257993
    Abstract: Provided are a light emitting device and a method of fabricating the same. The light emitting device comprises: a first conductive semiconductor layer; an active layer comprising an InGaN well layer and a GaN barrier layer on the first conductive semiconductor layer; and a second conductive semiconductor layer on the active layer. The GaN barrier layer comprises an AlGaN layer.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: September 4, 2012
    Assignee: LG Innotek Co., Ltd.
    Inventors: Dae Sung Kang, Hyo Kun Son
  • Patent number: 8241972
    Abstract: A method for making a flexible semiconductor device includes the following steps. A rigid substrate is provided. A flexible substrate is provided, and placed on the rigid substrate. A semiconductor device is directly formed on the flexible substrate using a semiconductor process. After the rigid substrate is removed, the flexible semiconductor device is formed.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: August 14, 2012
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Xue-Shen Wang, Qun-Qing Li
  • Publication number: 20120193731
    Abstract: Sensor packages and methods for making a sensor device package for side mounting on a circuit board. A sensor device(s) in a mechanical layer of silicon is sandwiched between first and second layers of glass to create a wafer. A first via(s) is created in the first or second layers to expose a predefined area of the mechanical layer of silicon. A second via(s) is created in the first or second layers. The least one second via has a depth dimension that is less than a depth dimension of the first via. A metallic trace is applied between the exposed area on the mechanical layer and a portion of the second via. The wafer is sliced such that the second via is separated into two sections, thereby creating a sensor die. The sensor die is then electrically and mechanically bonded to a circuit board at the sliced second via.
    Type: Application
    Filed: February 1, 2011
    Publication date: August 2, 2012
    Applicant: Honeywell International Inc.
    Inventor: Michael Foster
  • Publication number: 20120195338
    Abstract: A semiconductor laser device includes a p-type clad layer and an n-type clad layer, a p-side guide layer and an n-side guide layer interposed between the p-type clad layer and the n-type clad layer, and an active layer interposed between the p-side guide layer and the n-side guide layer. The active layer includes at least two quantum well layers and a barrier layer interposed between the quantum well layers adjoining to each other. Each of the p-type clad layer and the n-type clad layer is formed of a (Alx1Ga(1-x1))0.51In0.49P layer (0?x1?1). Each of the p-side guide layer, the n-side guide layer and the barrier layer is formed of a Alx2Ga(1-x2)As layer (0?x2?1). Each of the quantum well layers is formed of a GaAs(1-x3)Px3 layer (0?x3?1). The (Alx1Ga(1-x1))0.51In0.49P layer has a composition satisfying an inequality, x1>0.7. The Alx2Ga(1-x2)As layer has a composition satisfying an inequality, 0.4?x2?0.8.
    Type: Application
    Filed: January 26, 2012
    Publication date: August 2, 2012
    Applicant: ROHM CO., LTD.
    Inventors: Yoshito NISHIOKA, Yoichi MUGINO, Tsuguki NOMA
  • Publication number: 20120195339
    Abstract: A semiconductor laser device includes an n-type clad layer, a first p-type clad layer and a ridge stripe. The device also includes an active layer interposed between the n-type clad layer and the first p-type clad layer, and a current-blocking layer formed on side surfaces of the ridge stripe. The ridge stripe of the device includes a second p-type clad layer formed into a ridge stripe shape on the opposite surface of the first p-type clad layer from the n-type clad layer. The ridge stripe is formed such that a first ridge width as the width of a surface of the second p-type clad layer exists on the same side as the first p-type clad layer and a second ridge width as the width of a surface of the second p-type clad layer exists on the opposite side from the first p-type clad layer.
    Type: Application
    Filed: January 26, 2012
    Publication date: August 2, 2012
    Applicant: ROHM CO., LTD.
    Inventors: Yoshito NISHIOKA, Yoichi MUGINO, Tsuguki NOMA
  • Patent number: 8232566
    Abstract: A light emitting device includes a first semiconductor layer of a first conductivity type, an active layer adjacent to the first semiconductor layer, a second semiconductor layer of a second conductivity type and provided adjacent to the active layer, and a passivation layer provided on a side surface of the active layer. The passivation layer may be a semiconductor layer of one of the first conductivity type, the second conductivity type or a first undoped semiconductor layer. A first electrode may be coupled to the first semiconductor layer and a second electrode may be coupled to the second semiconductor layer.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: July 31, 2012
    Assignee: LG Innotek Co., Ltd.
    Inventors: Hyun Kyong Cho, Chang Hee Hong, Hyung Gu Kim
  • Patent number: 8227277
    Abstract: A method of fabricating a group-III nitride semiconductor laser device includes: preparing a substrate of a hexagonal group-III nitride semiconductor, where the substrate has a semipolar primary surface; forming a substrate product having a laser structure, an anode electrode and a cathode electrode, where the laser structure includes the substrate and a semiconductor region, and where the semiconductor region is formed on the semipolar primary surface; scribing a first surface of the substrate product in part in a direction of the a-axis of the hexagonal group-III nitride semiconductor; and carrying out breakup of the substrate product by press against a second surface of the substrate product, to form another substrate product and a laser bar.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: July 24, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yusuke Yoshizumi, Yohei Enya, Takashi Kyono, Masahiro Adachi, Katsushi Akita, Masaki Ueno, Takamichi Sumitomo, Shinji Tokuyama, Koji Katayama, Takao Nakamura, Takatoshi Ikegami
  • Patent number: 8222063
    Abstract: One embodiment of the present invention provides a method for fabricating light-emitting diodes (LEDs). The method includes fabricating an InGaAlN-based multilayer LED structure on a conductive substrate. The method further includes etching grooves of a predetermined pattern through the active region of the multilayer LED structure. The grooves separate a light-emitting region from non-light-emitting regions. In addition, the method includes depositing electrode material on the light-emitting and non-light-emitting regions, thereby creating an electrode. Furthermore, the method includes depositing a passivation layer covering the light-emitting and non-light-emitting regions. Moreover, the method includes removing the passivation layer on the electrode to allow the non-light-emitting regions which are covered with the electrode material and the passivation layer to be higher than the light-emitting region and the electrode, thereby protecting the light-emitting region from contact with test equipment.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: July 17, 2012
    Assignee: Lattice Power (Jiangxi) Corporation
    Inventors: Li Wang, Fengyi Jiang
  • Publication number: 20120145997
    Abstract: A hot filament chemical vapor deposition method has been developed to grow at least one vertical single-walled carbon nanotube (SWNT). In general, various embodiments of the present invention disclose novel processes for growing and/or producing enhanced nanotube carpets with decreased diameters as compared to the prior art.
    Type: Application
    Filed: February 6, 2007
    Publication date: June 14, 2012
    Applicant: William Marsh Rice University
    Inventors: Robert H. Hauge, Ya-Qiong Xu
  • Patent number: 8198707
    Abstract: A method and semiconductor device for forming a uniformly thin dielectric layer on graphene. A metal or semiconductor layer is deposited on graphene which is located on the surface of a dielectric layer or on the surface of a substrate. The metal or semiconductor layer may act as a nucleation layer for graphene. The metal or semiconductor layer may be subjected to an oxidation process. A thin dielectric layer may then be formed on the graphene layer after the metal or semiconductor layer is oxidized. As a result of synthesizing a metal-oxide layer on graphene, which acts as a nucleation layer for the gate dielectric and buffer to graphene, a uniformly thin dielectric layer may be established on graphene without affecting the underlying characteristics of graphene.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: June 12, 2012
    Assignee: Board of Regents, The University of Texas System
    Inventors: Luigi Colombo, Sanjay Banerjee, Seyoung Kim, Emanuel Tutuc
  • Patent number: 8193016
    Abstract: A semiconductor laser device includes a substrate and a semiconductor layer formed on a surface of the substrate and having a waveguide extending in a first direction parallel to the surface, wherein the waveguide is formed on a region approaching a first side from a center of the semiconductor laser device in a second direction parallel to the surface and intersecting with the first direction, a first region separated from the waveguide on a side opposite to the first side of the waveguide and extending parallel to the first direction and a first recess portion separated from the waveguide on an extension of a facet of the waveguide, intersecting with the first region and extending in the second direction are formed on an upper surface of the semiconductor laser device, and a thickness of the semiconductor layer on the first region is smaller than a thickness of the semiconductor layer on a region other than the first region.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: June 5, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryoji Hiroyama, Daijiro Inoue, Yasuyuki Bessho, Masayuki Hata
  • Publication number: 20120135554
    Abstract: A method of fabricating a group-III nitride semiconductor laser device includes: preparing a substrate of a hexagonal group-III nitride semiconductor, where the substrate has a semipolar primary surface; forming a substrate product having a laser structure, an anode electrode and a cathode electrode, where the laser structure includes the substrate and a semiconductor region, and where the semiconductor region is formed on the semipolar primary surface; scribing a first surface of the substrate product in part in a direction of the a-axis of the hexagonal group-III nitride semiconductor; and carrying out breakup of the substrate product by press against a second surface of the substrate product, to form another substrate product and a laser bar.
    Type: Application
    Filed: February 7, 2012
    Publication date: May 31, 2012
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Yusuke YOSHIZUMI, Shimpei TAKAGI, Takatoshi IKEGAMI, Masaki UENO, Koji KATAYAMA
  • Publication number: 20120134381
    Abstract: A method of forming an optoelectronic device comprising growing a first multi-layer 2 representing a reflector on a first substrate and a second multilayer 4 representing an active region on a second substrate, the first and second substrates being lattice mismatched, fusing the first multi-layer 2 to a third substrate 3, wherein the material of the third substrate 3 is lattice matched with respect to the material of the second multi-layer 4, removing the first substrate to expose the first multi-layer 2, and fusing the first multi-layer to the second multi-layer 4.
    Type: Application
    Filed: July 1, 2010
    Publication date: May 31, 2012
    Applicant: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE
    Inventors: Alexei Sirbu, Alexandru Mereuta, Andre Caliman
  • Publication number: 20120132263
    Abstract: Substrates may be bonded according to a method comprising contacting a first bonding surface of a first substrate with a second bonding surface of a second substrate to form an assembly; and compressing the assembly in the presence of an oxidizing atmosphere under suitable conditions to form a bonding layer between the first and second surfaces, wherein the first bonding surface comprises a polarized surface layer; the second bonding surface comprises a hydrophilic surface layer; the first and second bonding surfaces are different.
    Type: Application
    Filed: April 30, 2010
    Publication date: May 31, 2012
    Applicant: Arizona Board of Regents, a body Corporate acting for and on behalf of Arizona State University
    Inventors: Nicole Herbots, Robert J. Culbertson, James Bradley, Murdock Allen Hart, David Alexander Sell, Shawn David Whaley
  • Publication number: 20120132922
    Abstract: A structure and a method can provide a crystalline seed layer material, such as GaN, on a crystalline carrier material, such as sapphire, aligned such that a common crystal plane exists between the two materials. The common crystal plane may provide for a fracture surface along a cleavage plane that may be oriented to be perpendicular to the top surface of an optoelectronic device as well as perpendicular to a light emission direction.
    Type: Application
    Filed: July 8, 2009
    Publication date: May 31, 2012
    Applicant: SOITEC
    Inventors: Chantal Arena, Christiaan Werkhoven
  • Publication number: 20120126338
    Abstract: Systems and methods are disclosed for manufacturing grounded gate cross-hair cells and standard cross-hair cells of fin field-effect transistors (finFETs). In one embodiment, a process may include forming gate trenches and gates on and parallel to row trenches in a substrate, wherein the gate trenches and gates are pitch-doubled such that four gate trenches are formed for every two row trenches. In another embodiment, a process may include forming gate trenches, gates, and grounded gates in a substrate, wherein the gate trenches and gates are formed such that three gate trenches are formed for every two row trenches.
    Type: Application
    Filed: November 19, 2010
    Publication date: May 24, 2012
    Applicant: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 8183669
    Abstract: A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 ?m-10 ?m thick edge process-induced degradation layer.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: May 22, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Hidenori Mikami, Naoki Matsumoto
  • Patent number: 8178400
    Abstract: A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy gate layer, depositing a semiconductor material into the recess, removing the hardmask layer, depositing replacement spacers onto the dummy gate layer, performing an oxide deposition over the dummy gate layer and replacement spacers, removing the dummy gate and replacement spacers, thereby forming a gate recess in the oxide and depositing a gate stack into the recess.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: May 15, 2012
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Amlan Majumdar
  • Publication number: 20120114005
    Abstract: Provided is a method of manufacturing a surface-emitting laser capable of preventing characteristics fluctuations within the plane and among wafers and oscillating in a single fundamental transverse mode. The method includes after performing selective oxidation: exposing a bottom face of a surface relief structure by etching a second semiconductor layer with a first semiconductor layer where a pattern of the surface relief structure has been formed as an etching mask and a third semiconductor layer as an etching stop layer; and exposing a top face of the surface relief structure by etching the first semiconductor layer where the pattern of the surface relief structure has been formed, with the second semiconductor layer and the third semiconductor layer as etching stop layer.
    Type: Application
    Filed: November 1, 2011
    Publication date: May 10, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yasuhisa Inao, Tatsuro Uchida, Takeshi Uchida
  • Patent number: 8173469
    Abstract: Provided is a method for fabricating a light emitting device. The method for fabricating the light emitting device includes forming a buffer layer including a compound semiconductor in which a rare-earth element is doped on a substrate, forming a light emitting structure including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, which are successively stacked on the buffer layer, forming a first electrode layer on the light emitting structure, removing the substrate, and forming a second electrode layer under the light emitting structure.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: May 8, 2012
    Assignee: LG Innotek Co., Ltd.
    Inventors: Kyung Wook Park, Myung Hoon Jung
  • Publication number: 20120107991
    Abstract: A III-nitride-based light emitting device having a multiple quantum well (MQW) structure and a method for fabricating the device, wherein at least one barrier in the MQW structure is doped with magnesium (Mg). The Mg doping of the barrier is accomplished by introducing a bis(cyclopentadienyl)magnesium (Cp2Mg) flow during growth of the barrier using metalorganic chemical vapor deposition (MOCVD). The barriers of the MQW structure may be undoped, fully Mg-doped or partially Mg-doped. When the barrier is partially Mg-doped, only portions of the barrier are Mg-doped to prevent Mg diffusion into quantum wells of the MQW structure. The Mg-doped barriers preferably are high Al composition AlGaN barriers in nonpolar or semipolar devices.
    Type: Application
    Filed: October 21, 2011
    Publication date: May 3, 2012
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Chia-Yen Huang, Shuji Nakamura, Steven P. DenBaars, James S. Speck
  • Publication number: 20120100702
    Abstract: A method for forming a semiconductor device includes the following processes. A first well including a memory cell region of a semiconductor substrate is formed. A second well including a first peripheral circuit region of the semiconductor substrate is formed after forming the first well.
    Type: Application
    Filed: April 26, 2011
    Publication date: April 26, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Toshiya NAKAMORI
  • Patent number: 8163633
    Abstract: A method for the production of a robust, chemically stable, crystalline, passivated nanoparticle and composition containing the same, that emit light with high efficiencies and size-tunable and excitation energy tunable color. The methods include the thermal degradation of a precursor molecule in the presence of a capping agent at high temperature and elevated pressure. A particular composition prepared by the methods is a passivated silicon nanoparticle composition displaying discrete optical transitions.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: April 24, 2012
    Assignee: Merck Patent GmbH
    Inventors: Brian A. Korgel, Keith P. Johnston
  • Patent number: 8153515
    Abstract: A nitride based heterojunction transistor includes a substrate and a first Group III nitride layer, such as an AlGaN based layer, on the substrate. The first Group III-nitride based layer has an associated first strain. A second Group III-nitride based layer, such as a GaN based layer, is on the first Group III-nitride based layer. The second Group III-nitride based layer has a bandgap that is less than a bandgap of the first Group III-nitride based layer and has an associated second strain. The second strain has a magnitude that is greater than a magnitude of the first strain. A third Group III-nitride based layer, such as an AlGaN or AlN layer, is on the GaN layer. The third Group III-nitride based layer has a bandgap that is greater than the bandgap of the second Group III-nitride based layer and has an associated third strain. The third strain is of opposite strain type to the second strain. A source contact, a drain contact and a gate contact may be provided on the third Group III-nitride based layer.
    Type: Grant
    Filed: January 5, 2006
    Date of Patent: April 10, 2012
    Assignee: Cree, Inc.
    Inventor: Adam William Saxler
  • Publication number: 20120080762
    Abstract: A method for forming through features in a substrate uses a seed layer deposited over a first substrate, and a second substrate bonded to the seed layer. The features may be formed in the first substrate, by plating a conductive filler material onto the seed layer. The first substrate and the second substrate may then be bonded to a third substrate, and the second substrate is removed, leaving through features and first substrate adhered to the third substrate. The through features may provide at least one of electrical access and motion to a plurality of devices formed on the third substrate, or may impart movement to a moveable feature on the first substrate, wherein the third substrate supports the first substrate after removal of the second substrate.
    Type: Application
    Filed: October 5, 2010
    Publication date: April 5, 2012
    Applicant: Innovative Micro Technology
    Inventors: John S. Foster, John C. Harley, Jeffery F. Summers
  • Patent number: 8139619
    Abstract: Provided are a group-III nitride semiconductor laser device with a laser cavity to enable a low threshold current on a semipolar surface of a hexagonal group-III nitride, and a method for fabricating the group-III nitride semiconductor laser device on a stable basis. Notches, e.g., notch 113a and others, are formed at four respective corners of a first surface 13a located on the anode side of a group-III nitride semiconductor laser device 11. The notch 113a or the like is a part of a scribed groove provided for separation of the device 11. The scribed grooves are formed with a laser scriber and the shape of the scribed grooves is adjusted by controlling the laser scriber. For example, a ratio of the depth of the notch 113a or the like to the thickness of the group-III nitride semiconductor laser device 11 is not less than 0.05 and not more than 0.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: March 20, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shimpei Takagi, Yusuke Yoshizumi, Koji Katayama, Masaki Ueno, Takatoshi Ikegami
  • Patent number: 8133768
    Abstract: The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: March 13, 2012
    Assignees: NthDegree Technologies Worldwide Inc, The United States of America as represented by the Unites States National Aeronautics and Space Administration
    Inventors: William Johnstone Ray, Mark D. Lowenthal, Neil O. Shotton, Richard A. Blanchard, Mark Allan Lewandowski, Kirk A. Fuller, Donald Odell Frazier
  • Publication number: 20120056219
    Abstract: Solid state lights (SSLs) including a back-to-back solid state emitters (SSEs) and associated methods are disclosed herein. In various embodiments, an SSL can include a carrier substrate having a first surface and a second surface different from the first surface. First and second through substrate interconnects (TSIs) can extend from the first surface of the carrier substrate to the second surface. The SSL can further include a first and a second SSE, each having a front side and a back side opposite the front side. The back side of the first SSE faces the first surface of the carrier substrate and the first SSE is electrically coupled to the first and second TSIs. The back side of the second SSE faces the second surface of the carrier substrate and the second SSE is electrically coupled to the first and second TSIs.
    Type: Application
    Filed: September 2, 2010
    Publication date: March 8, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Cem Basceri, Casey Kurth, Kevin Tetz
  • Publication number: 20120049151
    Abstract: The present invention discloses a light-emitting device with a two-dimensional composition-fluctuation active-region obtained via two-dimensional thermal conductivity modulation of the material lying below the active-region. The thermal conductivity modulation is achieved via formation of high-density pores in the material below the active-region. The fabrication method of the light-emitting device and material with the high-density pores are also disclosed.
    Type: Application
    Filed: August 30, 2010
    Publication date: March 1, 2012
    Applicant: INVENLUX CORPORATION
    Inventors: JIANPING ZHANG, CHUNHUI YAN
  • Patent number: 8110889
    Abstract: In one embodiment a method for fabricating a compound nitride semiconductor device comprising positioning one or more substrates on a susceptor in a processing region of a metal organic chemical vapor deposition (MOCVD) chamber comprising a showerhead, depositing a gallium nitride layer over the substrate with a thermal chemical-vapor-deposition process within the MOCVD chamber by flowing a first gallium containing precursor and a first nitrogen containing precursor through the showerhead into the MOCVD chamber, removing the one or more substrates from the MOCVD chamber without exposing the one or more substrates to atmosphere, flowing a chlorine gas into the processing chamber to remove contaminants from the showerhead, transferring the one or more substrates into the MOCVD chamber after removing contaminants from the showerhead, and depositing an InGaN layer over the GaN layer with a thermal chemical-vapor-deposition process within the MOCVD chamber is provided.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: February 7, 2012
    Assignee: Applied Materials, Inc.
    Inventor: Olga Kryliouk
  • Patent number: 8076167
    Abstract: Provided are a group-III nitride semiconductor laser device with a laser cavity to enable a low threshold current on a semipolar surface of a hexagonal group-III nitride, and a method for fabricating the group-III nitride semiconductor laser device on a stable basis. Notches, e.g., notch 113a and others, are formed at four respective corners of a first surface 13a located on the anode side of a group-III nitride semiconductor laser device 11. The notch 113a or the like is a part of a scribed groove provided for separation of the device 11. The scribed grooves are formed with a laser scriber and the shape of the scribed grooves is adjusted by controlling the laser scriber. For example, a ratio of the depth of the notch 113a or the like to the thickness of the group-III nitride semiconductor laser device 11 is not less than 0.05 and not more than 0.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: December 13, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shimpei Takagi, Yusuke Yoshizumi, Koji Katayama, Masaki Ueno, Takatoshi Ikegami
  • Patent number: 8072043
    Abstract: A semiconductor component and a method for manufacturing such a semiconductor component which has a resistance behavior which depends heavily on the temperature. This resistance behavior is obtained by a special multi-layer structure of the semiconductor component, one layer being designed in such a way that, for example, multiple p-doped regions are present in an n-doped region, said regions being short-circuited on one side via a metal-plated layer. For example, the semiconductor component may be used for reducing current peaks, by being integrated into a conductor. In the cold state, the semiconductor component has a high resistance which becomes significantly lower when the semiconductor component is heated as a result of the flowing current.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: December 6, 2011
    Assignee: Robert Bosch GmbH
    Inventors: Peter Flohrs, Alfred Goerlach, Peter Urbach, Wolfgang Feiler, Ning Qu, Klaus Heyers
  • Patent number: 8071405
    Abstract: Provided is a group-III nitride semiconductor laser device with a laser cavity enabling a low threshold current, on a semipolar surface of a support base the c-axis of a hexagonal group-III nitride of which tilts toward the m-axis. In a laser structure 13, a first surface 13a is a surface opposite to a second surface 13b and first and second fractured faces 27, 29 extend each from an edge 13c of the first surface 13a to an edge 13d of the second surface 13b. A scribed mark SM1 extending from the edge 13c to the edge 13d is made, for example, at one end of the first fractured face 27, and the scribed mark SM1 or the like has a depressed shape extending from the edge 13c to the edge 13d. The fractured faces 27, 29 are not formed by dry etching and thus are different from the conventional cleaved facets such as c-planes, m-planes, or a-planes. It is feasible to use emission of a band transition enabling a low threshold current.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: December 6, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shimpei Takagi, Yusuke Yoshizumi, Koji Katayama, Masaki Ueno, Takatoshi Ikegami
  • Patent number: 8058085
    Abstract: N-V centers in diamond are created in a controlled manner. In one embodiment, a single crystal diamond is formed using a CVD process, and then annealed to remove N-V centers. A thin layer of single crystal diamond is then formed with a controlled number of N-V centers. The N-V centers form Qubits for use in electronic circuits. Masked and controlled ion implants, coupled with annealing are used in CVD formed diamond to create structures for both optical applications and nanoelectromechanical device formation. Waveguides may be formed optically coupled to the N-V centers and further coupled to sources and detectors of light to interact with the N-V centers.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: November 15, 2011
    Assignee: Apollo Diamond, Inc
    Inventors: Robert C. Linares, Patrick J. Doering, William W. Dromeshauser, Bryant Linares, Alfred R. Genis
  • Publication number: 20110269315
    Abstract: A thin film formation method to form a silicon film containing an impurity on a surface of an object to be processed in a process chamber that allows vacuum exhaust includes alternately and repeatedly performing a first gas supply process in which a silane-based gas composed of silicon and hydrogen is supplied into the process chamber in a state that the silane-based gas is adsorbed onto the surface of the object to be processed and a second gas supply process in which an impurity-containing gas is supplied into the process chamber, to form an amorphous silicon film containing an impurity. Accordingly, an amorphous silicon film containing an impurity having good filling characteristics can be formed even at a relatively low temperature.
    Type: Application
    Filed: April 27, 2011
    Publication date: November 3, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Kazuhide Hasebe, Akinobu Kakimoto
  • Patent number: 8039880
    Abstract: A switching circuit. The novel switching circuit includes an active device and a first circuit for providing a reactive inductive load in shunt with the active device. In an illustrative embodiment, the first circuit is implemented using a transmission line coupled between an output of the active device and ground, in parallel with the device, to minimize the parasitic effects of the device drain to source capacitance. In a preferred embodiment, the active device includes a silicon-germanium NFET optimized for operation at high frequencies (e.g. up to 20 GHz). The optimization process includes coupling a compact, low-parasitic polysilicon resistor to a gate of the NFET to provide gate RF isolation, and designing the gate manifold, drain manifold, and drain to source spacing of the NFET for optimal high frequency operation.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: October 18, 2011
    Assignee: Raytheon Company
    Inventors: Reza Tayrani, Mary A. Teshiba
  • Publication number: 20110248281
    Abstract: A nitride semiconductor substrate includes two principal surfaces including an upper surface that is a growth face and a lower surface on its opposite side. An FWHM in a surface layer region at depths of from 0 to 250 nm from the upper surface is narrower than an FWHM in an inner region at depths exceeding 5 ?m from the upper surface, where the FWHMs are obtained by X-ray rocking curve measurement using diffraction off a particular asymmetric plane inclined relative to the upper surface.
    Type: Application
    Filed: August 2, 2010
    Publication date: October 13, 2011
    Applicant: Hitachi Cable, Ltd.
    Inventors: Yuichi Oshima, Takehiro Yoshida
  • Patent number: 8035131
    Abstract: A method for forming a nitride semiconductor laminated structure includes forming a first layer that is an n-type or i-type first layer composed of a group III nitride semiconductor using an H2 carrier gas; forming a second layer by laminating a p-type second layer composed of a group III nitride semiconductor and containing Mg on the first layer using an H2 carrier gas; and forming a third layer that is an n-type or i-type third layer composed of a group III nitride semiconductor on the second layer using an H2 carrier gas after forming the second layer. A method for manufacturing a nitride semiconductor device includes the method steps for forming the nitride semiconductor laminated structure.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: October 11, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Hirotaka Otake, Hiroaki Ohta, Shin Egami
  • Patent number: 8030188
    Abstract: Provided is a method of forming a compound semiconductor device. In the method, a dopant element layer is formed on an undoped compound semiconductor layer. An annealing process is performed to diffuse dopants in the dopant element layer into the undoped compound semiconductor layer, thereby forming a dopant diffusion region. A rapid cooling process is performed using liquid nitrogen with respect to the substrate having the dopant diffusion region.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: October 4, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Mi-Ran Park, Jae-Sik Sim, Yong-Hwan Kwon, Bongki Mheen, Dae Kon Oh
  • Publication number: 20110237088
    Abstract: In the present invention, the position of a substrate on a thermal plate is detected when baking after exposure is performed in a first round of patterning. In a second round of patterning, the setting position of the substrate is adjusted based on a detection result of the position before the substrate is mounted on the thermal plate in the baking after exposure. In the baking after exposure in the second round of patterning, the substrate is mounted at the same position with respect to the thermal plate as that in the baking after exposure in the first round of patterning. In performing a plurality of rounds of patterning on a film to be processed, a pattern with a desired dimension is finally formed above the substrate, and the uniformity of the pattern dimension within the substrate is ensured.
    Type: Application
    Filed: June 13, 2011
    Publication date: September 29, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Takahisa OTSUKA