Abstract: A circuit and method for accelerating function evaluation. In one embodiment, a processor includes a function accelerator unit configured to evaluate a mathematical function. The function accelerator unit includes a coefficient generator and a polynomial evaluator. The coefficient generator is configured to generate coefficients for a polynomial evaluated to produce a solution to the function. The coefficient generator varies values of the coefficients based on an input value at which the function is to be evaluated. The polynomial evaluator configured to apply the coefficients provided by the coefficient generator to evaluate the polynomial at the input value.

Abstract: Operators such as unitary operators common in quantum mechanical applications may be approximated by a Trotter-like approximation. An operator may be decomposed and terms of the operator may be grouped, or assigned into levels. The levels may be scaled and applied at unique intervals of calculational steps. A quantum device may have circuitry for applying levels of the operator at the unique intervals.

Abstract: Certain aspects of the present disclosure relate to a method for quantizing signals and reconstructing signals, and/or encoding or decoding data for storage or transmission. Points of a signal may be determined as local extrema or points where an absolute rise of the signal is greater than a threshold. The tread and value of the points may be quantized, and certain of the quantizations may be discarded before the quantizations are transmitted. After being received, the signal may be reconstructed from the quantizations using an iterative process.

Abstract: Methods and systems for decompressing data are described. The relative magnitudes of a first value and a second value are compared. The first value and the second value represent respective endpoints of a range of values. The first value and the second value each have N bits of precision. Either the first or second value is selected, based on the result of the comparison. The selected value is scaled to produce a third value having N+1 bits of precision. A specified bit value is appended as the least significant bit of the other (non-selected) value to produce a fourth value having N+1 bits of precision.

Abstract: An FFT/IFFT operating core capable of minimizing a required memory depth during operation is disclosed. The FFT/IFFT operating core includes an inputting buffer, a first multiplexer, an operating module, and a controlling module. The inputting buffer stores and outputs a first FFT input sequence. The first multiplexer is utilized to multiplex the first FFT input sequence and a third input sequence. The controlling module generates a process indicating signal and a bypass indicating signal. The operating module has a plurality of operating stages in series. The operating module transforms the first and third FFT input sequences into a first and third FFT output sequences, respectively, and it transforms a second IFFT input sequence into a second IFFT output sequence.

Abstract: The present invention includes a guided microwave spectroscopy system (1) that eliminates the need for an automatic gain control feature by providing multiple signal processing paths having differing fixed voltage gains. An emitted signal which exits a test chamber (2) containing a material under test is simultaneously amplified by at least a first fixed gain amplifier (4) and a second fixed gain amplifier (7). The output signal of each amplifier is separately digitized and then normalized for further digital signal processing by a computer (13) in order to determine parameters of the material under test which may have variable microwave radiation characteristics that are a function of the frequency of the signal emitted into the test chamber. During the signal processing step a system clock (121) causes the computer to sample only an integral number of complete output signal cycles.

Abstract: A global image adjustment, such as dynamic range adjustment is established based on image characteristics. The image adjustment is based more heavily on pixel values in image areas identified as being important by one or more saliency mapping algorithms. In one application to dynamic range adjustment, a saliency map is applied to create a weighed histogram and a transformation is determined from the weighted histogram. Artifacts typical of local adjustment schemes may be avoided.

Abstract: An arithmetic circuit for quantizing pre-quantized data includes a first input register to store first-format pre-quantized data that includes a mantissa and an exponent, a second input register to store a quantization target exponent, an exponent-correction-value indicating unit to indicate an exponent correction value, an exponent generating unit to generate a quantized exponent obtained by subtracting the exponent correction value from the quantization target exponent, a shift amount generating unit to generate a shift amount obtained by subtracting the exponent of the pre-quantized data and the exponent correction value from the quantization target exponent, a shift unit to generate a quantized mantissa obtained by shifting the mantissa of the pre-quantized data by the shift amount generated by the shift amount generating unit, and an output register to store quantized data that includes the quantized exponent generated by the exponent generating unit and the quantized mantissa generated by the shift unit

Abstract: Sensor data is received from one or more sensors. The sensor data is organized within a hierarchy. The sensor data is organized within a hierarchy that is non-dyadic. A processor of a computing device generates a discrete wavelet transform, based on the sensor data and based on the hierarchy of the sensor data, to compress the sensor data. The sensor data, as has been compressed via generation of the discrete wavelet transform, is processed.

Abstract: For determining a minimum/maximum of a plurality of binary values a bit position in the plurality of binary values is determined subsequent to which all bit values are the same. From the plurality of binary values those binary values are selected the bit values of which at the bit position determined in the preceding step and all subsequent positions, if any, has a predetermined value. The preceding steps are then repeated until only one binary value remains which is provided as the minimum or maximum.

Abstract: This primality testing is based on Infinite, Symmetric, Convergent, Continuous, Convolution Ring Group. The computational complexity of any primality testing depends in the factor less than ?{square root over (N)} and becomes increasingly complex for large numbers as the lesser factor approaches ??N?. But in the present algorithm the Infinite, Symmetry, Convergent, Continuous, Convolution Ring Group causes the numerator (i.e. the left side of the modulus) to converge smoothly towards ??N? as the testing factor approaches ??N?. The normal operation for primality testing has computational complexity of O(n2), while the present algorithm has computational complexity of O(n·(ln(n)). By using the non-abelian group e.g. Matrix (A). Matrix (B)?Matrix (B). Matrix (A) the security is buttressed to the highest level.

Abstract: A pipelined circuit for performing a divide operation on small operand sizes. The circuit includes a plurality of stages connected together in a series to perform a subtractive divide algorithm based on iterative subtractions and shifts. Each stage computes two quotient bits and outputs a partial remainder value to the next stage in the series. The first and last stages utilize a radix-4 serial architecture with edge modifications to increase efficiency. The intermediate stages utilize a radix-4 parallel architecture. The divide architecture is pipelined such that input operands can be applied to the divider on each clock cycle.

Abstract: It is disclosed to estimate a state vector of an object, wherein the state vector comprises a state variable related to a position or an orientation of the object, based on at least one of a probability density function of the state vector truncated under consideration of a constraint for the state variable, wherein the constraint is derived from a map, and properties of the truncated probability density function.

Abstract: Systems and methods of identifying electrical sources of audible acoustic noise may involve identifying first frequency content of a circuit board, wherein the first frequency content is associated with at least one of acoustic noise and a vibration of the circuit board. Second frequency content of an electrical signal associated with the circuit board may also be identified. In addition, a coherence between the first frequency content and the second frequency content may be determined.

Abstract: Adaptive filtering is used to substantially cancel distortion in radio frequency (RF) signals. Such adaptive filtering can be used in an RF transmitting module to pre-compensate an RF signal with compensation (inverse) distortion to cancel inherent transmission path distortion from the RF signal. Adaptive filtering can also be used in a multi-carrier RF receiving module to cancel from a given carrier signal distortion due to cross talk from adjacent carrier signals. Adaptive filtering in an RF transceiver can be used to cancel from a received RF signal distortion arising from leakage of a transmit signal into the receive path.

Abstract: The document relates to modulated sub-sampled digital filter banks, as well as to methods and systems for the design of such filter banks. In particular, the present document proposes a method and apparatus for the improvement of low delay modulated digital filter banks. The method employs modulation of an asymmetric low-pass prototype filter and a new method for optimizing the coefficients of this filter. Further, a specific design for a (64) channel filter bank using a prototype filter length of (640) coefficients and a system delay of (319) samples is given. The method substantially reduces artifacts due to aliasing emerging from independent modifications of subband signals, for example when using a filter bank as a spectral equalizer. The method is preferably implemented in software, running on a standard PC or a digital signal processor (DSP), but can also be hardcoded on a custom chip.

Abstract: One or more continuous mappings are defined at a digital media encoder to convert input digital media data in a first high dynamic range format to a second format with a smaller dynamic range than the first format. The encoder converts the input digital media data to the second format with the smaller dynamic range using the continuous mapping and one or more conversion parameters relating to the continuous mapping. The encoder encodes the converted digital media data in a bitstream along with the conversion parameter(s). The conversion parameter(s) enable a digital media decoder to convert the converted digital media data back to the first high dynamic range format from the second format with the smaller dynamic range. Techniques for converting different input formats with different dynamic ranges are described.

Abstract: Systems and methods formulate problems for solving by a quantum processor using hardware graph decomposition. A decomposition of a primal graph may be built in a first stage based on a hardware specific graph, and refined in a second stage by, for example, removing vertices from the decomposition. The hardware specific graph may be a graph that is specific to a piece of hardware, for instance a quantum processor comprising a plurality of qubits and couplers operable to communicatively couple pairs of qubits.

Abstract: A system for measurement of spatial coordinates and/or orientation of a probe, comprising a first spatial direction sensor associated with a pattern of targets with known positions relative to each other and to the first spatial direction sensor, a second spatial direction sensor, and processing means for the computation of the orientation and/or spatial coordinates of the pattern of targets relative to the second spatial direction sensor based on the known positions of the targets relative to each other and a determination of the spatial directions of the targets with respect to the second spatial direction sensor, wherein at least three of the targets are in the field of view (FOV2) of the second spatial direction sensor irrespective of the orientation of the pattern of targets and wherein the first spatial direction sensor determines the spatial coordinates and/or orientation of the probe.

Abstract: A system and a method of generating an external parameter value for a separately excited motor controller are disclosed, the system including: a digital signal processor to convert a received analog electrical signal into a digital signal and to scale the digital signal, so as to generate a parameter value in conformity with a data format of the system; an external parameter generating module to adjust the parameter value with a calibration coefficient to obtain the external parameter value; the calibration coefficient being generated by a calibration coefficient generating module and being pre-stored in a calibration coefficient storing module; and a calibration coefficient generating module to read the parameter value generated by the digital signal processor and obtain an actual measuring value as a reference parameter value, to calculate a difference value between the parameter value from the digital signal processor and the reference parameter value, and to generate the calibration coefficient from a rat

Abstract: Provided is a semiconductor integrated circuit and an exponent calculation method that, when normalizing a plurality of data by a common exponent, speed up exponent calculation and reduce circuit scale and power consumption. When normalizing a plurality of data by a common exponent, a semiconductor integrated circuit calculates the exponent of the plurality of data. Included is a bit string generator that generates a second bit string containing bits having a transition value indicating that values of adjacent bits are different or a non-transition value indicating that values of adjacent bits are not different for each pair of adjacent bits of a first bit string constituting the data, and an exponent calculator that calculates the exponent of the plurality of data based on bit position of the transition value of a plurality of second bit strings generated from a plurality of first bit strings respectively constituting the plurality of data.

Abstract: Circuitry for computing a tangent function of an input value includes first look-up table circuitry that stores pre-calculated tangent values of a limited number of sample values, circuitry for inputting bits of the input value of most significance as inputs to the first look-up table circuitry to look up one of the pre-calculated tangent values as a first intermediate tangent value, circuitry for calculating a second intermediate tangent value from one or more ranges of remaining bits of the input value, and circuitry for combining the first intermediate tangent value and the second intermediate tangent value to yield the tangent function of the input value.

Abstract: A system for measurement of spatial coordinates and/or orientation of a probe, comprising a first spatial direction sensor associated with a pattern of targets with known positions relative to each other and to the first spatial direction sensor, a second spatial direction sensor, and processing means for the computation of the orientation and/or spatial coordinates of the pattern of targets relative to the second spatial direction sensor based on the known positions of the targets relative to each other and a determination of the spatial directions of the targets with respect to the second spatial direction sensor, wherein at least three of the targets are in the field of view (FOV2) of the second spatial direction sensor irrespective of the orientation of the pattern of targets and wherein the first spatial direction sensor determines the spatial coordinates and/or orientation of the probe.

Abstract: A logic circuit computes various modal interval arithmetic values using a plurality of arithmetic function units. A multiplexer gates the desired arithmetic values to a storage register.

Abstract: A modulator can be configured to sense a change in current flow in a circuit and to generate an oversampled, noise-shaped signal. A first decimation filter is coupled to the modulator and is configured to generate instantaneous current data at a first data rate. The instantaneous current data can be input into a multiplier circuit. The output of the multiplier circuit (the instantaneous current data squared) can be input to a second decimation filter. The second decimation filter can be configured to generate a sum of the squared current data at a second data rate. The sum of the squared current data can be used by an application (e.g., battery power management) to compute power measurements or for other purposes.

Abstract: An information processing device includes: plural input registers including a first input register and a second input register; an added value register; a first adding unit that performs addition processing for stored data of the first input register and stored data of the second input register; a second adding unit that performs addition processing for connected data, which is obtained by connecting the stored data of the first input register and the stored data of the second input register, and stored data of the added value register; and plural output registers in which a processing result of the first adding unit or the second adding unit is stored, wherein in each of given execution cycles, the first adding unit stores a processing result of the first adding unit in any one of the plural output registers and the second adding unit stores a processing result of the second adding unit in any one of the plural output registers.

Abstract: The current application is directed to methods and quantum circuits that prepare qubits in specified non-stabilizer quantum states that can, in turn, be used for a variety of different purposes, including in a quantum-circuit implementation of an arbitrary single-qubit unitary quantum gate that imparts a specified, arbitrary rotation to the state-vector representation of the state of an input qubit. In certain implementations, the methods and systems consume multiple magic-state qubits in order to carry out probabilistic rotation operators to prepare qubits with state vectors having specified rotation angles with respect to a rotation axis. These qubits are used as resources input to various quantum circuits, including the quantum-circuit implementation of an arbitrary single-qubit unitary quantum gate.

Abstract: A target quantum circuit expressed in a first quantum gate basis may be transformed into a corresponding quantum circuit expressed in a second quantum gate basis, which may be a universal set of gates such as a V gate basis set. The target quantum circuit may be expressed as a linear combination of quantum gates. The linear combination of quantum gates may be mapped to a quaternion. The quaternion may be factorized, based at least in part on an amount of precision between the target quantum circuit and the corresponding quantum circuit expressed in the second quantum gate basis, into a sequence of quaternion factors. The sequence of quaternion factors may be mapped into a sequence of quantum gates of the second quantum gate basis, where the sequence of sequence of quantum gates is the corresponding quantum circuit.

Abstract: A computer-implemented method includes receiving instructions to execute an analytic, wherein the instructions comprise one or more analytic inputs and a corresponding one or more uncertainty values, and wherein the analytic defines a continuous, monotonic mathematical function. The method includes executing the analytic using the one or more analytic inputs to determine one or more analytic outputs. The method also includes executing an uncertainty calculation to estimate one or more uncertainty outputs corresponding to the one or more analytic outputs, based, at least in part, on the one or more analytic inputs and the corresponding one or more uncertainty values. The method further includes providing the one or more analytic outputs as well as the corresponding one or more uncertainty outputs.

Abstract: A floating point value can represent a number or something that is not a number (NaN). A floating point value that is a NaN having data field that stores information, such as a propagation count that indicates the number of times a NaN value has been propagated through instructions. A NaN evaluation instruction can determine whether one or more operands is a NaN operand of a particular type, and if so can generate a result that is a NaN of a different type.

Abstract: A computer system includes a deterministic computer that provides a non-recursive functional to a quantum system encoder. The quantum system encoder encodes the non-recursive functional into a first quantum system. The first quantum state is transformed to a second quantum state by an operator that includes a Topological Order Processing Element (TOPE). A quantum allegory generator provides an oracle to the operator.

Abstract: Systems and methods are disclosed for quantum verification and validation of cyber-physical systems that include a quantum allegory generator that maps a specification for the system undergoing verification and validation testing to a thermodynamical allegory. A hybrid classical-quantum processing system in which a quantum processing system serves as the oracle of the classical processing system and uses the thermodynamical allegory to determine whether there is a set of variable settings that satisfy the thermodynamical allegory. The presence and location of faults can be determined based on characteristics of the set of variables that satisfy the thermodynamical allegory, if the variables exist.

Abstract: A computer-executable ratiometric analysis method determines integer components of a rational number ratio or a close approximation of an irrational number ratio. In one embodiment the method uses a ratio of rotational speeds of two rotating assets in a machine or process, generates a new rational number based on the ratio of speeds, and calculates the integer components of the new rational number. The result is the integer ratio relationship between the initial two rational numbers. The method may be used in machinery analysis applications to determine whether a low-order integer ratio relationship exists between two machinery rotating components. Low-order integer ratio relationships in machinery are generally harmful in related machinery rotating components, and detection of such relationships is an important tool in preventing damage to machinery components.

Abstract: A data processing system, method and computer program product to receive general-purpose code for iterative summation of an aggregate number of addends, wherein each addend has a precision. The data processing system operates an arithmetic hardware unit to set a first set of input registers to be a target of memory mapped registers and uses a broad-based adder to generate an adder result, wherein the broad-based adder has a broad-based adder size of inputs, and the broad-based adder size is less than the aggregate number of addends and greater than two, wherein each input register of the first set of input registers is connected to each input. Further, the data processing system may write the adder result to a storage array in memory, wherein the adder result is the sum of the inputs, and the adder result is placed in the storage array as indexed by a storage array index.

Abstract: Provided is a method for processing data samples from a plurality of data channels. The method may include obtaining a plurality of data samples from the plurality of data channels. Obtaining the plurality of data samples may involve successively obtaining a data sample from each data channel of the plurality of data channels. Successively obtaining a data sample from each data channel may be performed a plurality of times during a specified time period. Each data sample of the plurality of data samples may be associated with a respective sample time, and each respective sample time may be relative to a single specified reference point in time. The method may further include, for each data sample of the plurality of data samples, determining a time-dependent coefficient value that may correspond to the sample time associated with the data sample, and applying the determined time-dependent coefficient value to the data sample.

Abstract: Provided are a system and method for identifying planned markers while drilling a borehole. In one example, the method includes obtaining a plan containing planned markers that each corresponds to a baseline marker from an existing well. Each of the baseline markers corresponds to a waveform from a log file obtained from the existing well and is associated with a waveform representation of the corresponding waveform. Each of the planned markers is associated with an estimated true vertical depth (TVD) value. A second log file corresponding to the borehole is obtained that contains waveforms representing formation information detected within the borehole. The second log file is scanned for a planned marker based on the estimated TVD value and the waveform representation of the baseline marker corresponding to the planned marker. At least one match may be identified and reported for the planned marker.

Abstract: An apparatus for performing a Fast Fourier Transform (FFT) is provided. The apparatus comprises a reorder matrix, symmetrical butterflies, and a memory. The reorder matrix is configured to have a constant geometry, and the butterflies are coupled in parallel to the reorder matrix. The memory is also coupled to the reorder matrix and each butterfly. The reorder matrix, the butterflies, and the memory can then execute a split radix algorithm.

Abstract: A digital signal processor is provided in a wireless communication device, wherein the processor comprises a vector unit, first and second registers coupled to and accessible by the vector unit; and an instruction set configured to perform matrix inversion of a matrix of channel values by coordinate rotation digital computer instructions using the vector unit and the first and second registers.

Abstract: A method, system, and processor-readable storage medium are directed towards calculating approximate order statistics on a collection of real numbers. In one embodiment, the collection of real numbers is processed to create a digest comprising hierarchy of buckets. Each bucket is assigned a real number N having P digits of precision and ordinality O. The hierarchy is defined by grouping buckets into levels, where each level contains all buckets of a given ordinality. Each individual bucket in the hierarchy defines a range of numbers—all numbers that, after being truncated to that bucket's P digits of precision, are equal to that bucket's N. Each bucket additionally maintains a count of how many numbers have fallen within that bucket's range. Approximate order statistics may then be calculated by traversing the hierarchy and performing an operation on some or all of the ranges and counts associated with each bucket.

Abstract: A Symbol vector for RF transmission after multiplexing onto a subset of a set of subcarriers using OFDM is transformed to the time domain. A first time domain cancellation vector is generated from a basis vector that has the same dimensionality as the symbol vector. In the frequency domain the basis vector has a substantially zero value in each of a first subset of sub-carriers of the symbol vector and in the time domain the difference between a first element of the basis vector having the highest value and a second element of the basis vector having the next highest value is maximized. The first cancellation vector is subtracted from the symbol vector to produce modified symbol vector having reduced Peak-to-Average Power Ratio (PAPR). A second cancellation vector is generated using the modified symbol vector and is used to produce a second modified symbol vector having reduced PAPR.

Abstract: The present invention is a device for and method of measuring similarity between sets using a union block, three function blocks, an adder, a subtractor, and a divider. The first set is fed into the first function block and the first input of the union block. The second set is fed into the second function block and the second input of the union block. The output of the union block is fed into the input of the third function block. The outputs of the first and second function block feed into the adder. The output of the adder and the output of the third function block feed into the subtractor. The output of the subtractor feeds into the input of the divider.

Abstract: A second derivative of a second-order differential equation is calculated at a reference variable value. The second derivative is multiplied by an analytical small variable value, the first derivative at the reference variable value is added, and a result is output as a first derivative after an increment of the analytical small variable value. The first derivative after an increment of the analytical small variable value is multiplied by the analytical small variable value, a physical value at the reference variable value is added, and a result is output as a physical value after an increment of the analytical small variable value.

Abstract: Techniques are generally described for generating an identification number for an integrated circuit (IC). In some examples, methods for generating an identification for an IC may comprise selecting circuit elements of the IC, evaluating measurements of an attribute of the IC for the selected circuit elements, wherein individual measurements are associated with corresponding input vectors previously applied to the IC, solving a plurality of equations formulated based at least in part on the measurements taken of the attribute of the IC for the selected circuit elements to determine scaling factors for the selected circuit elements, and transforming the determined scaling factors for the selected circuit elements to generate an identification number of the IC. Additional variants and embodiments may also be disclosed.

Abstract: A method of operating a data-processing unit to produce a transform comprises calculating first and second output data values based at least on first and second input data values. The method comprises reading the first and second input data values from locations of a first buffer, the locations being determined by first and second read addresses based on first and second read indices. The method also comprises writing the first and second output data values to adjacent memory locations of a second buffer during a single write cycle. Furthermore, the method comprises reading third and fourth input data values from locations of the second buffer, the locations being determined by third and fourth read addresses determined by swapping at least two of the bits of the first and second read indices respectively. A data-processing unit for producing a transform, a transform-computation unit and an electronic apparatus are also described.

Abstract: An implementation of SVM functionality improves efficiency, time consumption, and data security, reduces the parameter tuning challenges presented to the inexperienced user, and reduces the computational costs of building SVM models. A system for support vector machine processing comprises data stored in the system, a client application programming interface operable to provide an interface to client software, a build unit operable to build a support vector machine model on at least a portion of the data stored in the system, the portion of the data selected using a stratified sampling method with respect to a target distribution, an apply unit operable to apply the support vector machine model using the data stored in the system.

Abstract: An algorithm and architecture are disclosed for performing multi-argument associative operations. The algorithm and architecture can be used to schedule operations on multiple facilities for computations or can be used in the development of a model in a modeling environment. The algorithm and architecture resulting from the algorithm use the latency of the components that are used to process the associative operations. The algorithm minimizes the number of components necessary to produce an output of multi-argument associative operations and also can minimize the number of inputs each component receives.

Abstract: In a method of generating a digital signature of a message m, a signature component s of the digital signature is calculated by first masking the long-term private key d using a single additive operation to combine the key d with a first value. The masked value is then multiplied by a second value to obtain component s. The first value is calculated using the message m and another component of the digital signature, and the second value is derived using the inverse of a component of the first value. In this way, the signature component s is generated using a method that counters the effectiveness of side channel attacks, such as differential side channel analysis, by avoiding a direct multiplication using long-term private key d.

Abstract: Surface measurement data just provides the coordinates of an object surface without giving various parameters like the radius of curvature, conic constant, and deformation coefficients. In this paper, we propose a novel method for extracting the important parameters for the determination of unknown aspheric surface equations from the measurement of aspheric surfaces. The largest error between the original surface and the reconstructed surface in the theoretical case is shown to be about 8.6 nm. This fact implies that the new method is well suited for the reconstruction of unknown surface equations.

Abstract: A processor-implemented method, system, and/or computer program product defines multiple dimensional data gravity wells on a conformed dimensional data gravity wells membrane. Non-dimensional data objects are associated with dimension objects to define conformed dimensional objects. The conformed dimensional objects are parsed into an n-tuple that includes a pointer to one of the non-dimensional data objects, a probability that a non-dimensional data object has been associated with a correct dimension object, and a weighting factor of importance of the conformed dimensional object. A virtual mass of each parsed conformed dimensional object is calculated, in order to define a shape of multiple dimensional data gravity wells that are created when conformed dimensional objects are pulled into each of the dimensional data gravity well frameworks on a conformed dimensional data gravity wells membrane.

Abstract: In an embodiment a method of vectorizing a collapsed multi-nested loop includes executing, in a vector unit of a processor, the collapsed loop to obtain a vector of offsets, including for each of a plurality of iterations, calculating a scalar offset into a multi-dimensional data structure, storing the scalar offset in a data element of a first vector register, and updating a loop counter value of a multi-dimensional loop counter vector. In turn, a plurality of data elements are loaded from the multi-dimensional data structure using a base value and indexes from the vector of offsets, at least one computation is performed on the loaded plurality of data elements to obtain a plurality of results, and the plurality of results are stored into the multi-dimensional data structure using the base value and the indexes from the vector of offsets. Other embodiments are described and claimed.