Abstract: A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

Abstract: A variable resistance memory device includes a substrate, a plurality of active lines formed on the substrate, are uniformly separated, and extend in a first direction, a plurality of switching devices formed on the active lines and are separated from one another, a plurality of variable resistance devices respectively formed on and connected to the switching devices, a plurality of local bit lines formed on the variable resistance devices, are uniformly separated, extend in a second direction, and are connected to the variable resistance devices, a plurality of local word lines formed on the local bit lines, are uniformly separated, and extend in the first direction, a plurality of global bit lines formed on the local word lines, are uniformly separated, and extend in the second direction, and a plurality of global word lines formed on the global bit lines, are uniformly separated, and extend in the first direction.

Abstract: Scribe-line structures and methods of forming such scribe-line structures on a face of a semiconductor substrate are provided. By means of the scribe-line structures and the methods of this invention, physical shock and cracking tendencies along a semiconductor substrate can be minimized during performance of a cutting process on the semiconductor substrate as part of post-fabrication processing. A representative method according to this invention comprises the sequential steps of: forming a lower layer on a semiconductor substrate; forming a molding layer on the lower layer such that the molding layer includes at least one protective contact hole; subsequently forming a dielectric layer and an upper layer on the molding layer so as to fill the protective contact hole, such dielectric layer being formed of a material having a greater mechanical intensity than that of the molding layer; and then forming protective layer patterns on the upper layer.

Abstract: A junction board cutting method includes, upon cutting a junction board formed by bonding a second main surface of a first substrate having a first main surface provided with chip areas and scribe areas demarcating the chip areas from one another and the second main surface, and a fourth main surface of a second substrate having a third main surface and the fourth main surface along the scribe areas and separating the same every chip, (1) a step for performing wet etching on areas given by orthogonal projection of the scribe areas to the third main surface to expose the second main surface, thereby defining concave groove, and (2) a step for performing dicing along the scribe areas until the exposed second main surface is reached, thereby to cut the junction board.

Abstract: A bit-line equalizer, a semiconductor memory device including the bit-line equalizer, and a method for manufacturing the bit-line equalizer, in which the bit-line equalizer includes: first and second polysilicon gates formed in a first direction in proximity to each other, the first and second polysilicon gates having a predetermined distance between them; and a plurality of equalizing transistors formed in a second direction along the first and second polysilicon gates, the equalizing transistors equalizing bit-line pairs, with the equalizing transistors being alternately formed in proximity to the first and second polysilicon gates. The bit-line equalizer can vary the widths of the equalizing transistors irrespective of a memory cell pitch in order to improve an equalizing time.

Abstract: A method of providing a memory cell includes providing a body of a semiconductor material having a first conductivity type, arranging a filter of a conductor-filter system in contact with a first conductor of the conductor-filter system, arranging at least portion of a second conductor of a conductor-insulator system in contact with the filter, arranging a first insulator of the conductor-insulator system in contact with the second conductor at an interface, arranging a first region spaced from the second conductor, arranging a channel of the body between the first region and the second conductor, arranging a second insulator adjacent to the first region, arranging a charge storage region between the first and the second insulators, arranging a first portion of a word-line adjacent to and insulated from the charge storage region, and arranging a second portion of the word-line adjacent to and insulated from the body.

Abstract: The present invention provides a method of manufacturing semiconductor device. The method includes providing a semiconductor wafer having a main surface; defining a chip forming region which includes chip regions defined by scribe lines, and a peripheral region which surrounds the chip forming region, on the main surface; forming circuit elements and electrode pads connected to the circuit elements on the chip areas; forming an insulating film, which exposes respective portions of the electrode pads, on the main surface; forming protruded electrodes on the insulating film provided in the chip areas so that the protruded electrodes are arranged at predetermined intervals in the chip area; forming an encapsulating material, which exposes top faces of the protruded electrodes, on the insulating film; and cutting the semiconductor wafer along the scribe lines.

Abstract: An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide has a thick gate oxide portion and a thin gate oxide portion, where the thing gate oxide portion has at least one dimension less than a minimum feature size of a process technology. The thin gate oxide can be rectangular in shape or triangular in shape. The anti-fuse transistor can be used in a two-transistor memory cell having an access transistor with a gate oxide substantially identical in thickness to the thick gate oxide of the variable thickness gate oxide of the anti-fuse transistor.

Abstract: In a memory device and a method of forming the same, in one embodiment, the memory device comprises a first word line structure on a substrate, the first word line structure extending in a first direction. A bit line is provided over the first word line structure and spaced apart from the first word line by a first gap, the bit line extending in a second direction transverse to the first direction. A second word line structure is provided over the bit line and spaced apart from the bit line by a second gap, the second word line structure extending in the first direction.

Abstract: A method of fabricating an electrical contact through a through hole in a substrate, wherein the through hole is at least in part filled with a liquid conductive material and the solidified liquid conductive material provides an electrical contact through the through hole.

Abstract: This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.

Abstract: A nonvolatile memory cell according to the present invention comprises a bottom conductor, a semiconductor pillar, and a top conductor. The semiconductor pillar comprises a junction diode, including a bottom heavily doped region, a middle intrinsic or lightly doped region, and a top heavily doped region, wherein the conductivity types of the top and bottom heavily doped region are opposite. The junction diode is vertically oriented and is of reduced height, between about 500 angstroms and about 3500 angstroms. A monolithic three dimensional memory array of such cells can be formed comprising multiple memory levels, the levels monolithically formed above one another.

Abstract: A wiring structure of a semiconductor device may include an insulation interlayer on a substrate, the insulation interlayer having a linear first trench having a first width and a linear second trench having a second width, the linear second trench being in communication with a lower portion of the linear first trench, the first width being wider than the second width, and a conductive layer pattern in the linear first and second trenches.

Abstract: An array substrate for an in-plane switching mode liquid crystal display device includes: a gate line on a substrate; a data line crossing the gate line to define a pixel region on the substrate; a common line parallel to and spaced apart from the gate line; a gate electrode connected to the gate line; a semiconductor layer disposed over the gate electrode, wherein an area of the semiconductor layer is less than an area of the gate electrode; a source electrode connected to the data line, and a drain electrode spaced apart from the source electrode, the source and drain electrodes disposed on the semiconductor layer; a plurality of pixel electrodes integrated with the drain electrode and extending from the drain electrode in the pixel region; and a plurality of common electrodes connected to the common line and alternately arranged with the plurality of pixel electrodes, wherein each of the source electrode, the drain electrode, the data line and the plurality of pixel electrodes are comprised from a first co

Abstract: The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).

Abstract: A method of manufacturing self-aligned contact openings is provided. A substrate having a number of device structures is provided and the top of the device structures is higher than the surface of the substrate. A first dielectric layer and a conductive layer are sequentially formed on the surfaces of the substrate and the device structures. Next, a part of the conductive layers on the top and the sidewalls of the device structures is removed and a number of first spacers is formed on the exposed sidewalls of the device structures. The exposed conductive layer and the first dielectric layer are removed by using the first spacer as the mask to expose the substrate. Then, a number of conductive spacers is formed. A number of second spacers is formed on the sidewalls of the conductive spacers.

Abstract: Methods are provided for fabricating packaged chips, each packaged chip having a protective layer, e.g., a transparent lid, metallic enclosure layer, shield layer, etc., and methods are provided for manufacturing such protective layer to be incorporated into a packaged chip. Lidded chip structures, and assemblies are also provided which include lidded chips.

Abstract: An object is to provide an electronic device of a multilayer structure with high density and high reliability that can be reduced in size while incorporating an electronic component therein, and further provide a production method for easily producing such an electronic device. An electronic device of the present invention includes wiring layers and electrically insulating layers stacked on a core board and establishes predetermined electrical conduction between the wiring layers through upper-lower side conducting vias provided in the electrically insulating layers.

Abstract: A phase change memory device is disclosed. A first columnar electrode and a second columnar electrode are provided, both arranged horizontally. A phase change layer is interposed between the first columnar electrode and the second columnar electrode, electrically connecting both thereof, wherein the entirety of the phase change layer is disposed on a plane. A bottom electrode electrically connects the first columnar electrode. A top electrode electrically connects the second columnar electrode.

Abstract: Systems and arrangements to interconnect cells and structures within cells of an integrated circuit to enhance cell density are disclosed. Embodiments comprise an adjusted polysilicon gate pitch to metal wire pitch relationship to improve area scalars while increasing ACLV tolerance with a fixed polysilicon gate pitch. In some embodiments, the wire pitch for at least one metallization layer is adjusted to match the pitch for the polysilicon gate. In one embodiment, the next to the lowest metallization layer running in the same orientation as the polysilicon gate, utilized to access the input or output of the interconnected cell structures is relaxed to match the minimum contacted gate pitch and the metal is aligned above each polysilicon gate. In another embodiment, the polysilicon gate pitch may be relaxed to attain a smaller lowest common multiple with the wire pitch for an integrated circuit to reduce the minimum step off.

Abstract: A semiconductor device having SRAM cell units each comprising a pair of driving transistors, a pair of load transistors and a pair of access transistors, in which each of the transistors has a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulting film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; a longitudinal direction of each semiconductor layer extends along a first direction; and between the adjacent SRAM cell units in the first direction, the semiconductor layer in one of the corresponding transistors is located on a center line of the semiconductor layer in the other transistor which center line extends along the first direction.

Abstract: A semiconductor integrated circuit includes a function block arranged on a substrate, a first buffering cell arranged adjacent to a first side of the function block, a second buffering cell arranged adjacent to a second side adjacent to the first side of the function block, and signal wiring passing over the function block obliquely relative to the first side and the second side, connecting the first buffering cell and the second buffering cell.

Abstract: A fabrication method for an optical transmission channel board includes a first step of forming on a substrate a layer containing an electrically conductive material, and a second step of patterning said layer containing an electrically conductive material formed on said substrate, and thereby forming circuit patterns at least a part of which is used as an electric circuit and at least a part of which positionally regulates an optical transmission channel.

Abstract: After a first electronic component is inserted into a base substrate, first circuit patterns are formed on the inserted first electronic component, and then a second electronic component is mounted on the first circuit patterns to complete an electronic component-mounted component. According to the above method, a thickness of a module may be decreased by a thickness of the base substrate. Further, since electronic components are surface-mounted, electronic components of arbitrary sizes and types may be used.

Abstract: There is provided a method of easily forming thin film transistors having the same characteristics in fabricating a differential circuit or a current mirror circuit utilizing two thin film transistors made of a polycrystalline silicon semiconductor. Four each thin film transistors are used in a differential circuit and a current mirror circuit, respectively. The thin film transistors are arranged to be symmetric to each other about a symmetry center instead of using thin film transistors arranged adjacently on the substrate in the respective circuits.