Abstract: An apparatus and method for holding a semiconductor device in a wafer. A bar is connected to the wafer. A first sidewall comprises a first end and a second, and is connected to the bar at its first end. A first tab comprises a first end and a second end, and is connected to the second end of the first sidewall at its first end and connected to the first side of the semiconductor device at its second end. The thickness of the first tab is less than the thickness of the bar and the thickness of the first sidewall.

Abstract: A decoupling capacitor, a wafer stack package including the decoupling capacitor, and a method of fabricating the wafer stack package are provided. The decoupling capacitor may include a first electrode formed on an upper surface of a first wafer, a second electrode formed on a lower surface of a second wafer, and an adhesive material having a high dielectric constant and combining the first wafer with the second wafer. In the decoupling capacitor the first and second electrodes operate as two electrodes of the decoupling capacitor, and the adhesive material operates as a dielectric of the decoupling capacitor.

Abstract: A method and the resultant memory is described for forming an array of floating body memory cells and logic transistors on an SOI substrate. The floating bodies for the cells are formed over the buried oxide, the transistors in the logic section are formed in the bulk silicon.

Abstract: A CMOS solid-state imaging device configured to restrain the occurrence of white spots and dark current caused by pixel defects, and also to increase the saturation signal amount. Adjacent pixels are separated by an element isolation portion formed of a diffusion layer and an insulating layer thereon, and the insulating layer of the element isolation portion is formed in a position equal to or shallower than the position of a pn junction on the side of an accumulation layer of a photoelectric conversion portion 38 constituting a pixel.

Abstract: Semiconductor dice (100, 200) of integrated circuit chips are provided with solder bump pads (130, 230) distributed over active areas of the dice to supply the I/O interconnects without including peripheral wire bond pads. The dice are further provided with protective ESD structures (140p/140i, 240p/240i) arranged in a network that includes ESD structures that extend into the interior areas of the dice. This allows the ESD structures to be placed proximate to respective power and ground connections, and positioned to reduce an average interconnect length between interior bump pads and the ESD structures relative to an average path length between the interior bump pads and the die peripheral area.

Abstract: An image sensor device is disclosed. The image sensor device includes a semiconductor substrate having a first pixel region and a second pixel region. A first photo-conversion device is disposed within the first pixel region of the semiconductor substrate to receive a first light source. A second photo-conversion device is disposed within the second pixel region of the semiconductor substrate to receive a second light source different from the first light source. The surface of the semiconductor substrate corresponding to the first photo-conversion device and the second photo-conversion device has a first microstructure and a second microstructure, respectively, permitting a reflectivity of the first pixel region with respect to the first light source to be lower than a reflectivity of the second pixel region with respect to the first light source. The invention also discloses a fabrication method of the image sensor device.

Abstract: An integrated circuit 78 is formed of multiple layers of circuits 14, 16 superimposed to produce stacks of circuit blocks 2, 4. Stack control circuitry 18, 20 is associated with the input and output signals from the circuit blocks to direct these to/from the currently active circuit block(s) as appropriate. The superimposed circuit blocks 2, 4 provide redundancy for each other, both for manufacturing defect resistance and for operational redundancy, such as providing multiple modular redundancy in safety critical environments.

Abstract: An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed.

Abstract: An integrated circuit structure includes a semiconductor wafer, which includes a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer. A carrier wafer is mounted onto the semiconductor wafer. The carrier wafer has a second notch overlapping at least a portion of the first notch. A side of the carrier wafer facing the semiconductor wafer forms a sharp angle with an edge of the carrier wafer. The carrier wafer has a resistivity lower than about 1×108 Ohm-cm.

Abstract: An apparatus for etching a substrate includes (a) a nozzle system including at least one nozzle through which acid solution containing at least hydrofluoric acid is sprayed onto the substrate, (b) a mover which moves at least one of the nozzle system and the substrate relative to the other in a predetermined direction in such a condition that the substrate and the nozzle system face each other, (c) a filter system which filters off particles out of the acid solution having been sprayed onto the substrate, and (d) a circulation system which circulates the acid solution having been sprayed onto the substrate, to the filter system, and further, to the nozzle system from the filter system.

Abstract: A semiconductor memory device has an asymmetric buried gate structure with a stepped top surface and a method for fabricating the same. The method for fabricating the semiconductor memory device includes: etching a predetermined region of a semiconductor substrate to form an isolation layer defining an active region; forming a recess within the active region; forming a metal layer filling the recess; asymmetrically etching the metal layer to form an asymmetric gate having a stepped top surface at a predetermined portion of the recess; and forming a capping oxide layer filling a remaining portion of the recess where the asymmetric gate is not formed, thereby obtaining an asymmetric buried gate including the asymmetric gate and the capping oxide layer.

Abstract: A die (or of a stack of die) is mounted over and elevated above a support, and is electrically connected to circuitry in the support. Pillars of electrically conductive material are formed on a set of bond pads at a mount side of the support, and the elevated die (or at least one die in the elevated stack of die) is electrically connected to the support, by traces of an electrically conductive material contacting interconnect pads on the die to the pillars, and through the pillars to the support. Also, tiered offset stacked die assemblies in a zig-zag configuration, in which the interconnect edges of a first (lower) tier face in a first direction, and the interconnect edges of a second (upper) tier, stacked over the first tier, face in a second direction, different from the first direction, are electrically connected to a support.

Abstract: An IC device (100) includes an IC body (106) having a base layer (108) and first and second upper layers (114, 116) on the base layer. The IC body includes a cavity region (104) extending through said base and first upper layers and at least a portion of said second upper layer. In the IC device, a portion of said second upper layer in the cavity region comprises a planar inductive element (102) having first and second contacting ends (140, 142). In the IC device, at least one support member (128, 130, 132) extends at least partially into said cavity region from said IC body in at least a first direction parallel to said base layer and intersects at least a portion of said planar inductive element.

Abstract: A semiconductor device includes a semiconductor substrate of n-type silicon including, in an upper portion thereof, a first polarity inversion region and a second polarity inversion regions spaced from each other and doped with a p-type impurity. A first HFET including a first active layer and a second HFET including a second active layer both made of a group III-V nitride semiconductor are independently formed on the respective polarity inversion regions in the semiconductor substrate, and the HFETs are electrically connected to each other through interconnects.

Abstract: A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.

Abstract: A vertically-integrated image sensor is proposed with the performance characteristics of single crystal silicon but with the area coverage and cost of arrays fabricated on glass. The image sensor can include a backplane array having readout elements implemented in silicon-on-glass, a frontplane array of photosensitive elements vertically integrated above the backplane, and an interconnect layer disposed between the backplane array and the image sensing array. Since large area silicon-on-glass backplanes are formed by tiling thin single-crystal silicon layers cleaved from a thick silicon wafer side-by-side on large area glass gaps between the tiled silicon backplane would normally result in gaps in the image captured by the array. Therefore, embodiments further propose that the pixel pitch in both horizontal and vertical directions of the frontplane be larger than the pixel pitch of the backplane, with the pixel pitch difference being sufficient that the frontplane bridges the gap between backplane tiles.

Abstract: The present invention discloses a capacitive MEMS switch on top of a semiconductor substrate containing a CMOS driving circuitry. The capacitive MEMS switch disclosed includes: 1) a semiconductor substrate containing a driving circuitry inside, and first and second conductors as well as a bottom electrode on top; 2) a suspended composite beam above and anchored onto the semiconductor substrate, containing a top electrode aligned to the bottom electrode with a first vertical distance, a top conductor, capped by a dielectric layer, having a first and second contact tips aligned with the first and second bottom conductors with a second vertical distance differentially smaller than the first vertical distance. The electrostatic attraction generated between the top electrode and the bottom electrode pulls the first and second contact tips in physical contact with and electrically connects the first and second bottom conductors through the top conductor.

Abstract: Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P+ substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P+-doped substrate contact in the bulk silicon layer of the SOI substrate.

Abstract: An integrated structure of an IGBT and a diode includes a plurality of doped cathode regions, and a method of forming the same is provided. The doped cathode regions are stacked in a semiconductor substrate, overlapping and contacting with each other. As compared with other doped cathode regions, the higher a doped cathode region is disposed, the larger implantation area the doped cathode region has. The doped cathode regions and the semiconductor substrate have different conductive types, and are applied as a cathode of the diode and a collector of the IGBT. The stacked doped cathode regions can increase the thinness of the cathode, and prevent the wafer from being overly thinned and broken.

Abstract: A high temperature micromachined ultrasonic transducer (HTCMUT) is provided. The HTCMUT includes a silicon on insulator (SOI) substrate having a doped first silicon layer, a doped second silicon layer, and a first insulating layer disposed between the first and second silicon layers. A cavity is disposed in the first silicon layer, where a cross section of the cavity includes a horizontal cavity portion on top of vertical cavity portions disposed at each end of the horizontal cavity portion, and the vertical cavity portion spans from the first insulating layer through the first silicon layer, such that a portion of the first silicon layer is isolated by the first insulating layer and the cavity. A membrane layer is disposed on the first silicon layer top surface, and spans across the cavity. A bottom electrode is disposed on the bottom of the second silicon layer.

Abstract: A method for fabricating double-gate and tri-gate transistors in the same process flow is described. In one embodiment, a sacrificial layer is formed over stacks that include semiconductor bodies and insulative members. The sacrificial layer is planarized prior to forming gate-defining members. After forming the gate-defining members, remaining insulative member portions are removed from above the semiconductor body of the tri-gate device but not the I-gate device. This facilitates the formation of metallization on three sides of the tri-gate device, and the formation of independent gates for the I-gate device.

Abstract: Methods and apparatus for an electronic device such as a field effect transistor. One embodiment includes fabrication of an FET utilizing single walled carbon nanotubes as the semiconducting material. In one embodiment, the FETs are vertical arrangements of SWCNTs, and in some embodiments prepared within porous anodic alumina (PAA). Various embodiments pertain to different methods for fabricating the drains, sources, and gates.

Abstract: A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of said metal layers, wherein said monocrystalline layer comprises second alignment marks; and performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks.

Abstract: An upper surface of a semiconductor substrate includes a first portion where a dielectric film is provided, and a second portion where the dielectric film is not provided, wherein the second portion is located in the periphery of the first portion. The upper surface of the semiconductor substrate is covered with a sealing resin.

Abstract: A method for fabricating a flexible semiconductor device includes: preparing a layered film 80 including a first metal layer 10, an inorganic insulating layer 20, a semiconductor layer 30, and a second metal layer 40 which are sequentially formed; etching the first metal layer 10 to form a gate electrode 12g; compression bonding a resin layer 50 to a surface of the layered film 80 provided with the gate electrode 12g to allow the gate electrode 12g to be embedded in the resin layer 50; and etching the second metal layer 40 to form a source electrode 42s and a drain electrode 42d, wherein the inorganic insulating layer 20 on the gate electrode 12g functions as a gate insulating film 22, and the semiconductor layer 30 between the source electrode 42s and drain electrode 42d on the inorganic insulating layer 20 functions as a channel 32.

Abstract: An integrated circuit includes a plurality of trench MOSFET and a plurality of trench Schottky rectifier. The integrated circuit further comprises: tilt-angle implanted body dopant regions surrounding a lower portion of all trench gates sidewalls for reducing Qgd; a source dopant region disposed below a bottom surface of all trench gates for functioning as a current path for preventing a resistance increased caused by the body dopant regions.

Abstract: The present invention has been made and an object thereof is to provide a thermosetting die-bonding film which can remarkably reduce working hours at the time of die bonding of a semiconductor chip, and a dicing die-bonding film including the thermosetting die-bonding film and a dicing film layered to each other. The present invention relates to a thermosetting die-bonding film used to produce a semiconductor device, comprising a thermosetting catalyst in a non-crystalline state in an amount within a range from 0.2 to 1 part by weight based on 100 parts by weight of an organic component in the film.

Abstract: An integrated circuit including ESD device is disclosed. One embodiment includes a semiconductor region being electrically isolated from adjacent semiconductor regions by an isolating region. Both an ESD device and a device configured to emit radiation are formed within the semiconductor region.

Abstract: A chip stack is created by stacking a plurality of semiconductor chips while connecting respective through electrodes of the semiconductor chips to each other, and forming a first sealing resin layer for covering the periphery of the plurality of stacked semiconductor chips, and filling gaps between the semiconductor chips. Subsequently, the chip stack is fixed on a supporting board or a wiring board which is formed with predetermined wiring.

Abstract: A CCD containing circuit and method for making the same. The circuit includes a CCD array and a protection circuit. The CCD array is constructed on an integrated circuit substrate and includes a plurality of gate electrodes that are insulated from the substrate by an insulating layer. The gate electrodes are connected to a conductor bonded to the substrate. The protection circuit is also constructed on the substrate. The protection circuit is connected to the conductor and to the substrate and protects the CCD array from both negative and positive voltage swings generated by electrostatic discharge events and the like. The protection circuit and the CCD can be constructed in the same integrated circuit fabrication process.

Abstract: In a method for fabricating a flexible pixel array substrate, first, a release layer is formed on a rigid substrate. Next, on the release layer, a polymer film is formed, the adhesive strength between the rigid substrate and the release layer being higher than that between the release layer and the polymer film. The polymer film is formed by spin coating a polymer monomer and performing a curing process to form a polymer layer. Afterwards, a pixel array is formed on the polymer film. The polymer film with the pixel array formed thereon is separated from the rigid substrate.

Abstract: A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.

Abstract: An optical waveguide apparatus having a very simple structure that can modulate a signal light guided through an optical waveguide is provided. A photoresist 13 is applied to an upper side of an SOI film 12, a photoresist mask 14 is formed, and the SOI film in a region that is not covered with the photoresist mask 14 is removed by etching to obtain an optical waveguide 15 having a single-crystal silicon core. Further, a light emitting device capable of irradiating the single-crystal silicon core with a light having a wavelength of 1.1 ?m or below is provided on a back surface side of a quartz substrate 20 to provide an optical waveguide apparatus. When the light emitting device 30 does not apply a light, the light guided through the optical waveguide 15 is guided as it is.

Abstract: A stacked microelectronic assembly is provided which includes first and second stacked microelectronic elements. Each of the first and second microelectronic elements can include a conductive layer extending along a face of such microelectronic element. At least one of the first and second microelectronic elements can include a recess extending from the rear surface towards the front surface, and a conductive via extending from the recess through the bond pad and electrically connected to the bond pad, with a conductive layer connected to the via and extending along a rear face of the microelectronic element towards an edge of the microelectronic element. A plurality of leads can extend from the conductive layers of the first and second microelectronic elements and a plurality of terminals of the assembly can be electrically connected with the leads.

Abstract: An electrical circuit includes at least two unit cells configured on a planar substrate which extends in one plane. The unit cells respectively have at least two contact points with a different function and include at least one dielectric layer disposed on the substrate and/or on the unit cells and at least two contact surfaces which are disposed parallel to the plane above the contact points and/or the substrate. The contact points with the same function are connected electrically to at least one common contact surface for at least a part of the contact points of the same function via at least one through-contacting through the dielectric layer and able to be contacted in common from outside via the corresponding contact surfaces.

Abstract: A method of fabricating a resistance variable device includes forming selection devices on a substrate, forming a conductive layer on the selection devices, patterning the conductive layer in a first direction to form conductive patterns spaced apart from each other in the first direction and connecting a pair of adjacent selection devices to each other in the first direction, forming a resistance-variable-material-layer on the conductive patterns, and patterning the resistance-variable-material-layer and the conductive patterns in a second direction to form rows of resistance-variable material extending in the second direction and to form electrodes spaced apart from one another, such that each electrode corresponds to a separate selection device.

Abstract: Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the se

Abstract: A method of depositing a bilayer of tungsten over tungsten nitride by a plasma sputtering process in which krypton is used as the sputter working gas during the tungsten deposition. Argon may be used as the sputtering working gas during the reactive sputtering deposition of tungsten nitride. The beneficial effect of reduction of tungsten resistivity is increased when the thickness of the tungsten layer is less than 50 nm and further increased when less than 35 nm. The method may be used in forming a gate stack including a polysilicon layer over a gate oxide layer over a silicon gate region of a MOS transistor in which the tungsten nitride acts as a barrier. A plasma sputter chamber in which the invention may be practiced includes gas sources of krypton, argon, and nitrogen.

Abstract: A method for preventing arcing during deep via plasma etching is provided. The method comprises forming a first patterned set of parallel conductive lines over a substrate and forming a plurality of semiconductor pillars on the first patterned set of parallel conductive lines and extending therefrom, wherein a pillar comprises a first barrier layer, an antifuse layer, a diode, and a second barrier layer, wherein an electric current flows through the diode upon a breakdown of the antifuse layer. The method further comprises depositing a dielectric between the plurality of semiconductor pillars, and plasma etching a deep via recess through the dielectric and through the underlying layer after the steps of forming a plurality of semiconductor pillars and depositing a dielectric. An embodiment of the invention comprises a memory array device.

Abstract: To provide a semiconductor module, a terminal strip, a method for manufacturing the terminal strip, and a method for manufacturing the semiconductor module in which loop inductance is decreased. A terminal strip includes a grounding (GND) conductor, power supply (VDD) conductors, signal line conductors, and insulators. The insulators intervene between the GND conductor and the VDD conductors. Similarly, the insulators intervene between the GND conductor and the signal line conductors. In the terminal strip, since the GND conductor and the VDD conductors are disposed close to each other, mutual inductance between GND wiring and VDD wiring can be increased. Thus, loop inductance can be decreased.

Abstract: A nonvolatile semiconductor memory device according to the present invention includes a memory cell array layer including a first line; a plurality of second and third lines that are formed below or above the first line and cross each other; and a plurality of memory cells arranged at each intersection of the second and third lines, the memory cell including a variable resistor and a transistor, which are connected to each other in series between the first line and the third line, the variable resistor being electrically rewritable and storing a resistance value as data in a nonvolatile manner, and the transistor being a columnar transistor having the second line arranged at its side face as a gate.

Abstract: A semiconductor multi-package module having stacked second and first packages, each package including a die attached to a substrate, in which the first and second package substrates are interconnected by wire bonding, and in which the first package is a flip chip ball grid array package in a die-up configuration. Also, a method for making a semiconductor multi-package module, by providing a first package including a first package substrate and having a die-up flip chip configuration, affixing a second package including a second package substrate an upper surface of the first package, and forming z-interconnects between the first and second package substrates.

Abstract: A semiconductor component arrangement is disclosed. In one embodiment, the semiconductor component arrangement includes a power transistor formed within a semiconductor layer in at least one first region and further semiconductor components formed at least in a second region, an effective thickness of the semiconductor layer being smaller in the first region than in the second region.

Abstract: Provided is a semiconductor device including a semiconductor substrate having transistors formed thereon, a first interlayer insulating film formed above the semiconductor substrate and the transistors, a ferroelectric capacitor formed above the first interlayer insulating film, a second interlayer insulating film formed above the first interlayer insulating film and the ferroelectric capacitor, a first metal wiring formed on the second interlayer insulating film, and a protection film formed on an upper surface of the wiring but not on a side surface of the wiring.

Abstract: In sophisticated semiconductor devices, an asymmetric transistor configuration may be obtained on the basis of an asymmetric well implantation while avoiding a tilted implantation process. For this purpose, a graded implantation mask may be formed, such as a graded resist mask, which may have a higher ion blocking capability at the drain side compared to the source side of the asymmetric transistor. For instance, the asymmetric configuration may be obtained on the basis of a non-tilted implantation process with a high degree of performance gain and may be accomplished irrespective of the technology standard under consideration.

Abstract: A method of manufacturing a memory device and a phase-change memory device is presented. The method of manufacturing the memory device includes performing Ge ion implantation on a top surface of a first layer. The method also includes performing a fast heat treatment on the ion-implanted first layer. The method also includes forming a second layer on a top of the fast heat-treated first layer.

Abstract: Transistor devices are formed with nickel silicide layers formulated to prevent degradation upon removal of overlying stress liners. Embodiments include transistors with nickel silicide layers having a platinum composition gradient increasing in platinum content toward the upper surfaces thereof, i.e., increasing in platinum in a direction away from the gate electrode and source/drain regions. Embodiments include forming a first layer of nickel having a first amount of platinum and forming, on the first layer of nickel, a second layer of nickel having a second amount of platinum, the second weight percent of platinum being greater than the first weight percent. The layers of nickel are then annealed to form a nickel silicide layer having the platinum composition gradient increasing in platinum toward the upper surface.

Abstract: A memory card includes a circuit board, a first semiconductor chip mounted on the circuit board with a bump sandwiched between the first semiconductor chip and the circuit board, a second semiconductor chip mounted on the circuit board with a bump sandwiched between the second semiconductor chip and the circuit board with a clearance not greater than 1 mm between the first semiconductor chip and the second semiconductor chip, a first sealing resin layer surrounding the bump and existing between the first semiconductor chip and the circuit board, and a second sealing resin layer surrounding the bump and existing between the second semiconductor chip and the circuit board, and a cover covering the first semiconductor chip, the second semiconductor chip on a principal face of the circuit board.

Abstract: A vertically aligned thin-film transistor array substrate in which there is no reduction in aperture ratio includes an etching-stop layer formed on an insulating layer; a passivation layer formed on the insulating layer that includes the etching-stop layer; a depression formed in the passivation layer and hollowing the passivation layer to the surface of the etching-stop layer; and a pixel electrode, which is recessed in conformity with the depression, formed on the passivation layer that includes the depression; wherein the etching-stop layer comprises a transparent semiconductor.

Abstract: An electronic device includes a base having a first wiring thereon; a flexible film having a second wiring thereon; a plurality of elements each including a first connecting portion and a second connecting portion; and an adhesive agent layer, wherein each of the elements is sandwiched between the base and the film in a state in which the first connecting portion is in contact with the first wiring, the second connecting portion is in contact with the second wiring, and a tensile force is applied to the film, and, in this state, the base and the film are bonded with the adhesive agent layer.