Abstract: There are provided a method of forming fine patterns in a semiconductor device, and a method of forming a gate with a fine critical dimension using the same. In the method of forming fine patterns in a semiconductor device, a plurality of sidewall buffer patterns are formed on a gate insulating layer formed on a substrate, wherein the plurality of the sidewall buffer patterns are spaced apart from each other by a predetermined distance. A sidewall layer is deposited on the sidewall buffer patterns as well as the gate insulating layer. The sidewall layer is etched such that sidewall patterns remain on sidewalls of the sidewall buffer patterns.

Abstract: An integrated circuit comprising at least one signal path which is adapted to route at least one signal from an origin to a target block, said signal path comprising at least an adjustable driver circuit comprising an input and an output, which is adapted to receive an electric signal having a first signal power as an input signal and which is adapted to provide an electric signal having a second signal power as an output signal is provided. Furthermore, the integrated circuit comprises at least one interconnect having an ohmic resistance and an electric capacity and being adapted to route said electric signal having a second signal power to said target block. Furthermore, a method for manufacturing such an integrated circuit is provided.

Abstract: A microelectromechanical systems (MEMS) display element may include a photovoltaic structure configured to generate electric energy from incident light. In one embodiment, the display element includes a first layer that is at least partially transmissive of light, a second layer that is at least partially reflective of light, and a photovoltaic element that is formed on the first layer or the second layer or formed between the first layer and the second layer. The second layer is spaced from the first layer and is selectably movable between a first position in which the display element has a first reflectivity and a second position in which the display element has a second reflectivity. The first reflectivity is greater than the second reflectivity. The photovoltaic element is at least partially absorptive of light and is configured to convert a portion of the absorbed light into electric energy, at least when the second layer is in the second position.

Abstract: High voltage-resistant semiconductor devices adapted to control threshold voltage by utilizing threshold voltage variation caused by plasma damage resulting from the formation of multilayer wiring, and a manufacturing method thereof. Exemplary high voltage-resistant semiconductor devices include a plurality of MOS transistors having gate insulating films not less than about 350 ? in thickness on a silicon substrate, and the MOS transistors have different area ratios between gate electrode-gate insulating film contact areas and total opening areas of contacts formed on the gate electrodes.

Abstract: A photo-detector, in which metal wiring for connecting electrodes is arranged on a planarized surface and thus the metal wiring arrangement is simplified, and a method of manufacturing the same are provided. The photo-detector includes a multi-layer compound semiconductor layer formed on a compound semiconductor substrate. A number of p-n junction diodes are arranged in a regular order in a selected region of the compound semiconductor layer, and an isolation region for individually isolating the p-n junction diodes is formed by implanting impurity ions in the multi-layer compound semiconductor layer. The isolation region and the surface of the compound semiconductor layer are positioned on the same level. The isolation region may be a Fe-impurity region.

Abstract: A semiconductor device has a first region (10) and a second region (20), gate trenches (50) being formed in paid first and second regions including insulated gates to control conduction between source regions (42) and a common drain region (40) through a body region separated into first (34) and second (36) body regions. Isolation between the first and second regions is provided in a simple way by providing a gap between the first and second body regions (34,36) formed by eg. at least one trench (52) or a part of the drain region.

Abstract: In a CMOS image sensor and method of fabricating the same, the CMOS image sensor is comprised of a pixel array generating image signals and a peripheral circuit processing the image signals. In the method, a substrate is provided having a pixel region and a peripheral circuit region. A photo-receiving element and at least one transistor are formed on the pixel region of the substrate and a transistor is formed on the peripheral circuit region of the substrate. A silicide barrier pattern is formed to cover a region where the photo-receiving element is formed. A silicide layer is formed on a predetermined region of the substrate. An interlevel insulation film is formed on the silicide barrier layer. At least one contact hole penetrating the interlevel insulation film is formed, the at least one contact hole exposing a predetermined region of the silicide layer.

Abstract: The invention provides a laminating system in which one of second and third substrates for sealing a thin film integrated circuit is supplied to a first substrate having the plurality of thin film integrated circuit while being extruded in a heated and melted state, and further rollers are used for supplying the other substrate, receiving IC chips, separating, and sealing. Processes of separating the thin film integrated circuits provided over the first substrate, sealing the separated thin film integrated circuits, and receiving the sealed thin film integrated circuits can be continuously carried out by rotating the rollers. Thus, the production efficiency can be extremely improved.

Abstract: A method and the resultant memory is described for forming an array of floating body memory cells and logic transistors on an SOI substrate. The floating bodies for the cells are formed over the buried oxide, the transistors in the logic section are formed in the bulk silicon.

Abstract: A method of manufacturing an ultra thin integrated circuit comprises providing a substrate having a front side, a back side, and an edge extending from the front side to the back side; creating a defect layer in the substrate; forming semiconductor devices proximate the front side after creating the defect layer; and cleaving proximate the defect layer after forming the semiconductor devices. Other methods and apparatus are also provided.

Abstract: Provided are semiconductor devices and methods for fabricating and using the semiconductor devices, wherein the semiconductor devices may include a first element, a second element, and a plurality of parallel IO lines connecting the first element with the second element. The plurality of IO lines may have different lengths and the shortest IO line from among the plurality of the IO lines may be adjacent to a longest IO line from among the plurality of the IO lines.

Abstract: A method of relieving wafer stress is provided. A wafer is provided, wherein at least a dielectric layer has already formed over the wafer and the wafer has a first and a second area. At least no circuits are formed on the dielectric layer within the first area. Thereafter, openings are formed in the dielectric layer within the first area. A material layer is formed over the dielectric layer. Thus, pits are formed on the surface of the material layer at locations above the openings. Through the pits on the material layer, stress within the material layer is relieved and hence the amount of stress conferred to the wafer is reduced.

Abstract: The present invention relates to semiconductor devices comprising two or more dies stacked vertically on top of one another, and methods of making the semiconductor devices. The methods may comprise a combination of wafer-level through silicon interconnect fabrication and wafer-level assembly processes.

Abstract: A method of forming an integrated circuit structure on a substrate, the substrate includes a primary region and a secondary region. A first layer of a first material of a first thickness is formed over the substrate. A portion of the first layer is removed over the primary region to expose the substrate. The structure is exposed to an oxidizing medium. This forms a second layer, for example, of an oxide material primary region of the substrate. The second layer has a second thickness. Additionally, at least a portion of said first layer is converted to a third layer, for example, of an oxynitride material. The third layer has a third thickness.

Abstract: A wafer having a heat dissipation structure is provided. The wafer having the heat dissipation structure includes a wafer and a number of metallic heat dissipation parts. The wafer has a first surface and a second surface opposite thereto. Besides, a number of blind holes are formed on the second surface of the wafer. The metallic heat dissipation parts are partially embedded in the blind holes respectively and protrude from the second surface of the wafer.

Abstract: For producing a photovoltaic module (1), the front electrode layer (3), the semi-conductor layer (4) and the back electrode layer (5) are patterned by separating lines (6, 7, 8) to form series-connected cells (C1, C2, . . . Cn, Cn+1) with a laser (14) emitting infrared radiation. During patterning of the semiconductor layer (4) and the back electrode layer (5) the power of the laser (14) is so reduced that the front electrode layer (3) is not damaged.

Abstract: Methods for integrating quartz-based resonators with electronics on a large area wafer through direct pick-and-place and flip-chip bonding or wafer-to-wafer bonding using handle wafers are described. The resulting combination of quartz-based resonators and large area electronics wafer solves the problem of the quartz-electronics substrate diameter mismatch and enables the integration of arrays of quartz devices of different frequencies with the same electronics.

Abstract: A multi-chip device includes LED sensors for sensing light separated by a predetermined interval in a wafer, LEDs for emitting light formed over the wafer respectively corresponding to the LED sensors, a driving circuit formed between the LEDs over the wafer, an insulating film over the wafer, and trenches in the insulating film exposing the LEDs.

Abstract: Methods and reworked intermediate and resultant electronic modules made thereby, whereby a component in need of rework is located and removed from the module to reveal encapsulated solder connections residing within an underfill matrix. Heights of both the solder connections and underfill matrix are reduced, followed by etching the solder out of the solder connections to form openings within the underfill matrix. The underfill material is then removed to expose metallurgy of the substrate. A blank having a release layer with an array of solder connections is aligned with the exposed metallurgy, and this solder array is transferred from the blank onto the metallurgy. The transferred solder connections are then flattened using heat and pressure, followed by attaching solder connections of a new component to the flattened solder connections and underfilling these reworked solder connections residing between the new chip and substrate.

Abstract: In the method for producing a bonded wafer by bonding a wafer for active layer to a wafer for support layer and then thinning the wafer for active layer, when oxygen ions are implanted into the wafer for active layer, the implantation step is divided into two stages conducted under specified conditions.

Abstract: A process for forming an electronic device can be performed, such that as little as one gate electric layer may be formed within each region of the electronic device. In one embodiment, the electronic device can include an NVM array and other regions that have different gate dielectric layers. By protecting the field isolation regions within the NVM array and other regions while gate dielectric layer are formed, the field isolation regions may be exposed to as little as one oxide etch between the time any of the gate dielectric layers are formed the time such gate dielectric layers are covered by gate electrode layers. The process helps to reduce field isolation erosion and reduce problems associated therewith.

Abstract: A method for manufacturing a semiconductor device includes steps of forming an embedded channel 12 in a semiconductor substrate 11, forming a resist layer on the embedded channel 12 through an oxide film 14, exposing the resist layer using a grating mask the light transmissivity of which varies toward transfer directions of electric charges, developing the exposed resist layer to form a resist mask having a gradient, forming a first impurity region 13 having a concentration gradient by injecting ions into the embedded channel 12 through the resist mask, and arranging transfer electrodes 15 at prescribed positions on the first impurity region 13 through the oxide film 14 after removing the resist mask, wherein a potential profile becomes deeper toward the transfer directions of the electric charges.

Abstract: An image sensor includes a circuitry, a substrate, an electrical junction region, a high concentration first conduction type region, and a photodiode. The circuitry includes a transistor and is formed on and/or over the substrate. The electrical junction region is formed in one side of the transistor. The high concentration first conduction type region is formed on and/or over the electrical junction region. The photodiode is formed over the circuitry.

Abstract: By hydrogen-terminating a semiconductor surface using a solution containing HF2? ions and an oxidant, the hydrogen termination can be quickly carried out. In this case, the semiconductor surface is silicon having a (111) surface, a (110) surface, or a (551) surface.

Abstract: A method for manufacturing a light-emitting device comprising the steps of cutting a light-emitting unit by a laser beam, and cleaning the light-emitting unit by an acid solution to remove by-products resulted from the laser cutting.

Abstract: In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.

Abstract: A method of forming a backside protection film includes forming a first coating layer on a first heterogeneous film, the first coating layer being at a C-stage state, forming a second coating layer on a second heterogeneous film, the second coating layer being at a B-stage state, separating the first coating layer from the first heterogeneous film, and attaching the first coating layer to the second coating layer, the second coating layer being between the second heterogeneous film and the first coating layer, and each of the first and second heterogeneous films being formed by coating a first material layer with a second material.

Abstract: A thin film transistor display substrate comprises a base substrate on which a pixel area including a first reflection area and a second reflection area is defined. A gate line formed on the base substrate and a data line formed on the base substrate. The data line is insulated from and intersected with the gate line to define the pixel area. A thin film transistor is formed in the pixel area and connected to the gate line and the data line. A first reflection layer is formed on the base substrate and corresponds to the first reflection area. A color filter is formed on the first reflection layer and corresponds to the pixel area. A second reflection layer is formed on the color filter and corresponds to the second reflection area. A pixel electrode is formed on the color filter and is electrically connected to the thin film transistor.

Abstract: One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions. The nanofin transistor also has a surrounding gate insulator around the nanofin structure and a surrounding gate surrounding the channel region and separated from the nanofin channel by the surrounding gate insulator. The memory includes a data-bit line connected to the first source/drain region, at least one word line connected to the surrounding gate of the nanofin transistor, and a stacked capacitor above the nanofin transistor and connected between the second source/drain region and a reference potential. Other aspects are provided herein.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a substrate; mounting a base integrated circuit on the substrate; forming a leadframe interposer, over the base integrated circuit, by: providing a metal sheet, mounting an integrated circuit die on the metal sheet, injecting a molded package body on the integrated circuit die and the metal sheet, and forming a ball pad, a bond finger, or a combination thereof from the metal sheet that is not protected by the molded package body; coupling a circuit package on the ball pad; and forming a component package on the substrate, the base integrated circuit, and the leadframe interposer.

Abstract: A first metal layer of aluminum or an aluminum alloy is formed on a second interlayer insulating layer, and a second metal layer of silver or a silver alloy, which is patterned in the same pattern as the first metal layer, is formed on the first metal layer. The first metal layer and the second metal layer constitute wirings. The wirings are patterned in such a way as to overlie the gate lines and data lines of associated TFTs, and are laid out in such a way as to cover the TFTs.

Abstract: An integrated circuit chip has one or more electrically conductive nano-fibers formed on one or more contact pads of the integrated circuit chip. The one or more electrically conductive nano-fibers are configured to provide an adhesive force by intermolecular forces and establish an electrical connection with one or more contact pads disposed on the surface of a chip package.

Abstract: A method of dividing a wafer having a plurality of devices, which are formed in a plurality of areas sectioned by streets formed in a lattice pattern on the front surface and test metal patterns which are formed on the streets, having a metal pattern breaking step for forming a break line in the test metal patterns by applying a pulse laser beam having permeability to the wafer to the rear surface of the wafer with its focal point set near the test metal patterns; a deteriorated layer forming step for forming a deteriorated layer along the streets above the break lines in the inside of the wafer by applying a pulse laser beam having permeability to the wafer to the rear surface of the wafer with its focal point set to a position above the break lines in the inside of the wafer; and a dividing step.

Abstract: A high temperature micromachined ultrasonic transducer (HTCMUT) is provided. The HTCMUT includes a silicon on insulator (SOI) substrate having a doped first silicon layer, a doped second silicon layer, and a first insulating layer disposed between the first and second silicon layers. A cavity is disposed in the first silicon layer, where a cross section of the cavity includes a horizontal cavity portion on top of vertical cavity portions disposed at each end of the horizontal cavity portion, and the vertical cavity portion spans from the first insulating layer through the first silicon layer, such that a portion of the first silicon layer is isolated by the first insulating layer and the cavity. A membrane layer is disposed on the first silicon layer top surface, and spans across the cavity. A bottom electrode is disposed on the bottom of the second silicon layer.

Abstract: As well as achieving both downsizing and thickness reduction and sensitivity improvement of a semiconductor device that has: a MEMS sensor formed by bulk micromachining technique such as an acceleration sensor and an angular rate sensor; and an LSI circuit, a packaging structure of the semiconductor device having the MEMS sensor and the LSI circuit can be simplified. An integrated circuit having MISFETs and wirings is formed on a silicon layer of an SOI substrate, and the MEMS sensor containing a structure inside is formed by processing a substrate layer of the SOI substrate. In other words, by using both surfaces of the SOI substrate, the integrated circuit and the MEMS sensor are mounted on one SOI substrate. The integrated circuit and the MEMS sensor are electrically connected to each other by a through-electrode provided in the SOI substrate.

Abstract: Flash memory device structures and methods of manufacture thereof are disclosed. The flash memory devices are manufactured on silicon-on-insulator (SOI) substrates. Shallow trench isolation (STI) regions and the buried oxide layer of the SOI substrate are used to isolate adjacent devices from one another. The methods of manufacture require fewer lithography masks and may be implemented in stand-alone flash memory devices, embedded flash memory devices, and system on a chip (SoC) flash memory devices.

Abstract: A resistive element having two vertical resistive portions placed in two holes formed in the upper portion of a substrate and a horizontal resistive portion placed in a buried cavity connecting the bottoms of the holes.

Abstract: A method, a system and a computer readable medium for three dimensional packaging with wafer-level bonding and chip-level repair. A first wafer is provided having a first plurality of chips. A second wafer is provided having a second plurality of chips. At least one chip is removed from the second wafer while retaining the relative alignment of the remaining chips in the second wafer. The first and second wafers are aligned and joined with wafer-to-wafer techniques. Where a bad chip having a relative physical position within the second wafer corresponding to a relative physical position within the first wafer of a good chip is removed, a good chip may be aligned and bonded to the first wafer using die-to-wafer techniques.

Abstract: Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate and forming at least on Fin-JFET on the substrate.

Abstract: A process for producing a circuit substrate having a resin sheet having embedded circuit chips which is obtained by embedding circuit chips into a resin sheet, which comprises steps of (a) arranging and fixing circuit chips on a substrate for processing, (b) coating the substrate for processing on which the circuit chips have been arranged and fixed with a liquid material for forming a resin sheet of an energy curing type to form an uncured coating layer, (c) curing the uncured coating layer by impressing energy to form a layer of a resin sheet having embedded circuit chips, and (d) removing the substrate for processing from the layer of a resin sheet having embedded circuit chips, and a circuit substrate obtained in accordance with the process. A circuit substrate having a resin sheet having embedded circuit chips for controlling pixels of displays and the like can be produced efficiently with excellent quality and excellent productivity.

Abstract: A solid-state imaging device includes a plurality of photodiode regions arranged in an array, a non-transparent border region existing around each photodiode region, and a microlens array including a plurality of microlenses arranged in an array corresponding to the plurality of photodiode regions; wherein each microlens functions to converge incident light advancing straight toward the non-transparent border region around the corresponding photodiode region into that photodiode region, and the microlens array is formed using a transparent diamond-like carbon (DLC) film, the DLC film including a region where its refractive index is modulated corresponding to each microlens, and a light-converging effect being caused when light flux passes through the region where the refractive index was modulated.

Abstract: In a method of manufacturing a semiconductor device, a polycrystalline silicon film is deposited on a gate insulating film formed over a substrate and is doped with a P-type impurity to form the first polycrystalline silicon film with a P-type conductivity. A high melting point polycide film is deposited on the P-type first polycrystalline silicon film. The P-type first polycrystalline silicon film, high melting point metallic polycide film, and insulating film are etched to form a gate electrode. A second polycrystalline silicon film different from the P-type first polycrystalline silicon film is deposited on the substrate. The second polycrystalline silicon film is etched to form a resistor composed of the second polycrystalline silicon film.

Abstract: The present invention provides a laminated conductive film, comprising a transparent conductive film and Al-based film, that is capable of realizing a high-quality film with superior electro-optical properties, without providing a buffer layer or protective layer. A laminated conductive film according to one aspect of the present invention is provided with a transparent conductive film having optical transmissivity, and a metal conductive film laminated directly on the transparent conductive film and electrically connected to the transparent conductive film. The metal conductive film is made of Al or has Al as a main component thereof and contains at least one of nitrogen atom and oxygen atom at least in the vicinity of the interface with the transparent conductive film.

Abstract: A method includes steps of providing first and second substrates, and forming a bonding interface between them using a conductive bonding region. A portion of the second substrate is removed to form a mesa structure. A vertically oriented semiconductor device is formed with the mesa structure. A portion of the conductive bonding region is removed to form a contact. The vertically oriented semiconductor device is carried by the contact.

Abstract: The present invention provides a method for manufacturing a bonded wafer comprising steps of forming an oxide film on at least a surface of a base wafer or a surface of a bond wafer; bringing the base wafer and the bond wafer into close contact via the oxide film; subjecting these wafers to a heat treatment under an oxidizing atmosphere to bond the wafers together; grinding and removing the outer periphery of the bond wafer so that the outer periphery has a predetermined thickness; subsequently removing an unbonded portion of the outer periphery of the bond wafer by etching; and then thinning the bond wafer so that the bond wafer has a desired thickness, wherein the etching is conducted by using a mixed acid at 30° C. or less at least comprising hydrofluoric acid, nitric acid, and acetic acid.

Abstract: The invention relates to a method of improving a surface of a semiconductor substrate which is at least partially made of silicon. Defects present in or on the semiconductor substrate can be really repaired to provide a semiconductor substrate with a high surface quality. This is achieved by a selective epitaxial deposition in the at least one hole in the surface of the semiconductor substrate. Generally, the deposition step is preceded by an etching step which removes the defects and leaves behind at least one hole that can be plugged or filled with the selective epitaxial deposition of silicon to repair the substrate.

Abstract: Examples of a computer system packaged in a three-dimensional stack of dies are described. The package includes an electrical die and an optical die coupled to and stacked with the electrical die. The electrical die includes circuitry to process and communicate electrical signals, and the optical die includes structures to transport optical signals. The electrical die has a smaller area than the optical die so that the optical die includes an exposed mezzanine which is configured with optical input/output ports. Additionally, the packaging can be configured to provide structural support against insertion forces for external optical connections.

Abstract: A power semiconductor device comprising a first group of power transistor cells arranged in a first area of the power semiconductor device and a second group of power transistor cells arranged in a second area of the power semiconductor device. The first group of power transistor cells has an overall cell density different from that of the second group of power transistor cells such that the first and second groups of power transistor cells have different charge carrier densities.

Abstract: A CMOS solid-state imaging device configured to restrain the occurrence of white spots and dark current caused by pixel defects, and also to increase the saturation signal amount. Adjacent pixels are separated by an element isolation portion formed of a diffusion layer and an insulating layer thereon, and the insulating layer of the element isolation portion is formed in a position equal to or shallower than the position of a pn junction on the side of an accumulation layer of a photoelectric conversion portion 38 constituting a pixel.

Abstract: A method of making a circuitized substrate (e.g., PCB) including at least one and possibly several internal optical pathways as part thereof such that the resulting substrate will be capable of transmitting and/or receiving both electrical and optical signals. The method involves forming at least one opening between a side of the optical core and an adjacent upstanding member such that the opening is defined by at least one angular sidewall. Light passing through the optical core material (or into the core from above) is reflected off this angular sidewall. The medium (e.g., air) within the opening thus also serves as a reflecting medium due to its own reflective index in comparison to that of the adjacent optical core material. The method utilizes many processes used in conventional PCB manufacturing, thereby keeping costs to a minimum.