Abstract: Methods and apparatuses using pixels with shared readout circuits are used to increase pixel fill factor and operation efficiency.

Abstract: An integrated semiconductor device includes a resistor and an FET device formed from a stack of layers. The stack of layers includes a dielectric layer formed on a substrate; a metal conductor layer having lower electrical resistance formed on the dielectric layer; and a polysilicon layer formed on the metal conductor layer. A resistor stack is formed by patterning a portion of the original stack of layers into a resistor. An FET stack is formed from another portion of the original stack of layers. The FET stack is doped to form a gate electrode and the resistor stack is doped aside from the resistor portion thereof. Then terminals are formed at distal ends of the resistor in a doped portion of the polysilicon layer. Alternatively, the polysilicon layer is etched away from the resistor stack followed by forming terminals at distal ends of the metal conductor in the resistor stack.

Abstract: In a layout method for a semiconductor integrated circuit by using cell library data, a plurality of cell patterns are arranged in a first direction. One of gate patterns in one of the plurality of cell patterns is specified as a reference gate pattern. An additional cell pattern is arranged in a second direction orthogonal to the first direction such that a number of gate patterns within a predetermined area containing the reference gate pattern satisfies a constraint condition.

Abstract: A laser diode system is disclosed in which a substrate made of a semiconductor material containing laser diodes is bonded to a substrate made from a metallic material without the use of any intermediate joining or soldering layers between the two substrates. The metal substrate acts as an electrode and/or heat sink for the laser diode semiconductor substrate. Microchannels may be included in the metal substrate to allow coolant fluid to pass through, thereby facilitating the removal of heat from the laser diode substrate. A second metal substrate including cooling fluid microchannels may also be bonded to the laser diode substrate to provide greater heat transfer from the laser diode substrate. The bonding of the substrates at low temperatures, combined with modifications to the substrate surfaces, enables the realization of a low electrical resistance interface and a low thermal resistance interface between the bonded substrates.

Abstract: There are provided a plurality of semiconductor apparatuses judged as good items in electrical and functional inspections while having internal connection terminals disposed on electrode pads of semiconductor chips, resin layers which are disposed on surfaces of the semiconductor chips in which the electrode pads are formed and expose the internal connection terminals, and wiring patterns which are disposed on the resin layers and are connected to the internal connection terminals, a wiring substrate on which the plurality of semiconductor apparatuses are stepwise stacked, the wiring substrate electrically connected to the plurality of semiconductor apparatuses, and a sealing resin with which the plurality of semiconductor apparatuses are sealed.

Abstract: Disclosed herein is a semiconductor device with high reliability which has TFT of adequate structure arranged according to the circuit performance required. The semiconductor has the driving circuit and the pixel portion on the same substrate. It is characterized in that the storage capacitance is formed between the first electrode formed on the same layer as the light blocking film and the second electrode formed from a semiconductor film of the same composition as the drain region, and the first base insulating film is removed at the part of the storage capacitance so that the second base insulating film is used as the dielectric of the storage capacitance. This structure provides a large storage capacitance in a small area.

Abstract: There is disclosed a contact structure for electrically connecting conducting lines formed on a first substrate of an electrooptical device such as a liquid crystal display with conducting lines formed on a second substrate via conducting spacers while assuring a uniform cell gap among different cells if the interlayer dielectric film thickness is nonuniform across the cell or among different cells. A first conducting film and a dielectric film are deposited on the first substrate. Openings are formed in the dielectric film. A second conducting film covers the dielectric film left and the openings. The conducting spacers electrically connect the second conducting film over the first substrate with a third conducting film on the second substrate. The cell gap depends only on the size of the spacers, which maintain the cell gap.

Abstract: Stacked microelectronic devices and methods of manufacturing stacked microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes forming a plurality of electrically isolated, multi-tiered metal spacers on a front side of a first microelectronic die, and attaching a back-side surface of a second microelectronic die to individual metal spacers. In another embodiment, the method of manufacturing the microelectronic device may further include forming top-tier spacer elements on front-side wire bonds of the first die.

Abstract: In accordance with an embodiment of the invention, an integrated circuit including a plurality of connection pads is provided, wherein a first connection pad is configured in accordance with a first contacting technology, and wherein a second connection pad is configured in accordance with a second contacting technology. The second contacting technology is different from the first contacting technology.

Abstract: An semiconductor device is disclosed. The device includes a semiconductor body, a layer of insulating material disposed over the semiconductor body, and a region of gate electrode material disposed over the layer of insulating material. Also included are a source region adjacent to gate region and a drain region adjacent to the gate region. A gate connection is disposed over the semiconductor body, wherein the gate connection includes a region of gate electrode material electrically coupling a contact region to the gate electrode. An insulating region is disposed on the semiconductor body beneath the gate connection.

Abstract: A module including a carrier and a semiconductor chip applied to the carrier. An external contact element is provided having a first portion and a second portion extending perpendicular to the first portion, wherein a thickness of the second portion is smaller than a thickness of the carrier.

Abstract: A phase change memory device is provided. The phase change memory device comprises a substrate. A first conductive layer is formed on the substrate. A heating electrode is formed on the first conductive layer, and electrically connected to the first conductive layer, wherein the heating electrode comprises a carbon nanotube (CNT). A phase change material layer covers the heating electrode. A second conductive layer is formed on the phase change material layer, and electrically connected to the phase change material layer.

Abstract: It is object to provide a manufacturing method of an SOI substrate provided with a single-crystal semiconductor layer, even in the case where a substrate having a low allowable temperature limit, such as a glass substrate, is used and to manufacture a high-performance semiconductor device using such an SOI substrate. Light irradiation is performed on a semiconductor layer which is separated from a semiconductor substrate and bonded to a support substrate having an insulating surface, using light having a wavelength of 365 nm or more and 700 nm or less, and a film thickness d (nm) of the semiconductor layer which is irradiated with the light is made to satisfy d=?/2n×m±? (nm), when a light wavelength is ? (nm), a refractive index of the semiconductor layer is n, m is a natural number greater than or equal to 1 (m=1, 2, 3, 4, . . . ), and 0???10 is satisfied.

Abstract: A polymer-based, self-aligned wafer-level heterogeneous integration system, SA WLIT, for integrating semiconductor integrated circuit (IC) chips to a substrate is presented. The system includes a method including preparing a substrate, flipping the substrate onto a polymer-based flat surface and securing the substrate to the flat surface, mounting semiconductor chips into the prepared substrate, integrating the chips to the substrate with another polymer-based material, and removing the resulting multi-chip module from the flat surface. The chips may then be connected with each other and regions off the multi-chip module with metal interconnect processing technology. A multi-chip module prepared by the polymer-based, self-aligned heterogeneous integration system including semiconductor chips mounted in a prepared substrate. The chips may be connected to the substrate by a polymer-based integrating material.

Abstract: A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (SixOyNz) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched SixOyNz layer is used to etch an amorphous carbon layer. Silicon, oxide, and/or tungsten layers are etched using the amorphous carbon layer. In one implementation, conductive rails of the 3-D monolithic memory device are formed by etching an oxide layer such as silicon dioxide (SiO2) using the patterned amorphous carbon layer as a hard mask. Memory cell diodes are formed as pillars in polysilicon between the conductive rails by etching a polysilicon layer using another patterned amorphous carbon layer as a hard mask. Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-D monolithic memory device.

Abstract: The invention provides an integrated circuit package and method for operating and fabricating thereof. The package comprises a transparent substrate having a first surface and a second surface opposite to each other and a semiconductor layer formed on the second surface of the transparent substrate. A photosensitive device is fabricated on the semiconductor layer and a metal plug is formed over the second surface of the transparent substrate and they are electrically connected to each other. A solder ball is formed over the second surface of the transparent substrate and electrically connected to the metal plug. In the package, the photosensitive device senses light penetrating the transparent substrate and the semiconductor layer through its backside to produce a signal which is subsequently transmitted to solder ball by the metal plug. Thus, the signal conductive path is shortened.

Abstract: A high performance circuit is formed by using a TFT with less fluctuation in characteristics, and a semiconductor device including such a circuit is formed. When the TFT is formed, first, a base film and a semiconductor film are continuously formed on a quartz substrate without exposing to the air. After the semiconductor film is crystallized by using a catalytic element, the catalytic element is removed. In the TFT formed in such a process, fluctuation in electrical characteristics such as a threshold voltage and a subthreshold coefficient is extremely small. Thus, it is possible to form a circuit, such as a differential amplifier circuit, which is apt to receive an influence of characteristic fluctuation of a TFT.

Abstract: A method of dividing a wafer having a plurality of micro electro mechanical systems and a plurality of streets for partitioning the micro electro mechanical systems formed on the front surface of a wafer substrate, the method comprising a protective tape affixing step for affixing a protective tape to the front surface of the wafer; a cut groove-forming step for forming a cut groove by cutting the wafer having the protective tape affixed thereto along the streets from the back surface of the wafer substrate, leaving a cutting margin having a predetermined thickness on the front surface side of the wafer substrate; and a cutting step for cutting the cutting margins by applying a laser beam to the cutting margins of the cut grooves formed along the streets.

Abstract: It is realized a high sensitive solid-state imaging apparatus which corresponds to an optical system having a short focal length (an optical system having a large incident angle ?). Each pixel (2.8 mm square in size) includes a distributed refractive index lens (1), a color filter (2) for green, Al wirings (3), a signal transmitting unit (4), a planarized layer (5), a light-receiving element (Si photodiode) (6), and an Si substrate (7). The concentric circle structure of the distributed index lens is made of four types of materials having different refractive indexes such as TiO2 (n=2.53), SiN (n=2.53), SiO2 (n=2.53), and air (n=1.0). In the concentric structure, a radial difference of outer peripheries of adjacent circular light-transmitting films is 100 nm. Furthermore, the film thickness is 0.4 ?m.

Abstract: A packaging substrate and a manufacturing method thereof are provided. The manufacturing method includes following steps. First, a first packaging substrate including several first substrate units and at least one defected substrate unit is provided. Next, the defected substrate unit is separated from the packaging substrate, and at least one opening is formed in a frame of the first packaging substrate correspondingly. Then, a second substrate unit is provided. The shape of the second substrate unit is different from the shape of the opening. Afterwards, the second substrate unit is disposed in the opening.

Abstract: A first substrate of single-crystal silicon within which is formed an embrittled layer and over a surface of which is formed a first insulating film is provided; a second insulating film is formed over a surface of a second substrate; at least one surface of either the first insulating film or the second insulating film is exposed to a plasma atmosphere or an ion atmosphere, and that surface of the first insulating film or the second insulating film is activated; the first substrate and the second substrate are bonded together with the first insulating film and the second insulating film interposed therebetween; a single-crystal silicon film is separated from the first substrate at an interface of the embrittled layer of the first substrate, and a thin film single-crystal silicon film is formed over the second substrate with the first insulating film and the second insulating film interposed therebetween.

Abstract: A method of making a monolithic, three dimensional NAND string, includes forming a select transistor, forming a first memory cell over a second memory cell, forming a first word line for the first memory cell, forming a second word line for the second memory cell, forming a bit line, forming a source line, and forming a select gate line for the select transistor. The first and the second word lines are not parallel to the bit line, and the first and the second word lines extend parallel to at least one of the source line and the select gate line.

Abstract: Disclosed in an electrophoretic display device having a charged ink layer. In this disclosed device, the ink layer is disposed on the active region (an image display region) and the peripheral region located around the active region, and an electric field is applied to a portion of the electrophoretic ink film corresponding to the peripheral region. Therefore, the peripheral region does not look stained.

Abstract: A method of manufacturing a semiconductor device is provided. First, a substrate is provided. The substrate includes a high-voltage device region and a low-voltage device region. The high-voltage device region has a source/drain predetermined region, a pick-up predetermined region and a channel predetermined region. A first dielectric layer is formed on the substrate. Then, the first dielectric layer in the low-voltage device region is removed along with the first dielectric layer in the source/drain predetermined region and the pick-up predetermined region. Afterwards, a second dielectric layer is formed in the low-voltage device region. The thickness of the second dielectric layer is smaller than the thickness of the first dielectric layer. Then, gates are formed in the channel predetermined region and the low-voltage device region respectively. Next, a source/drain region is formed in the substrate of the source/drain predetermined region.

Abstract: Disclosed is an image sensor which includes a plurality of pixel patterns formed on corresponding metal interconnections of an interlayer dielectric and a dummy pixel pattern formed between adjacent pixel patterns of the plurality of the pixel patterns. The dummy pixel patterns are not formed connected to the metal interconnections. The dummy pixel patterns can be formed spaced a distance apart from the plurality of pixel patterns such that air gaps form between the dummy pixel patterns and the pixel patterns in an intrinsic layer that is formed on the dummy pixel pattern and the plurality of pixel patterns.

Abstract: A semiconductor device includes a first inverter, a second inverter, and an inner wiring connecting the inverters, in which the inner wiring forms a capacitor element, and the capacitor element includes an interlayer insulation film having an aperture on a semiconductor substrate, a lower electrode covering a bottom wall and a side wall of the aperture, the bottom wall being the semiconductor substrate and the side wall being a part of the interlayer insulation film, a capacitor insulation film arranged on the lower electrode and a part of the interlayer insulation film, the capacitor insulation film covering corners of the capacitor insulation film, the corners being situated at opposite side of the semiconductor substrate, and an upper electrode on the capacitor insulation film, the upper electrode covering the aperture.

Abstract: A flat panel display device, more particularly, an Organic Light Emitting Diode (OLED) display device having uniform electrical characteristics and a method of fabricating the same include: a thin film transistor of which a semiconductor layer including a source, a drain, and a channel region formed in a super grain silicon (SGS) crystallization growth region; a capacitor formed in an SGS crystallization seed region; and an OLED electrically connected to the thin film transistor. Further, a length of the channel region of the silicon layer is parallel with the growth direction in the SGS growth region to improve the electrical properties thereof.

Abstract: A method using an etchant and a laser for localized precise heating enables precise etching and release of MEMS devices with improved process control while expanding the number of materials used to make MEMS, including silicon-dioxide patterned films buried in and subsequently released from bulk silicon, as a direct write method of release of patterned structures that enables removal of only that material needed to allow the device to perform to be precisely released, after which, the bulk material can be further processed for additional electrical or packaging functions.

Abstract: A display device and its method of manufacture. The display device is formed to include a substrate having an upper surface, a recess region having a bottom surface and sidewalls, a light-emitting element and a switch element. The light-emitting element includes a first electrode disposed on the recess region, a light-emitting layer disposed on the first electrode, and a second electrode disposed on the light-emitting layer. The switch element is disposed on the substrate and electrically connected to the light-emitting element. The bottom surface of the recess region is lower than the bottom surface of the active layer.

Abstract: A method for forming TGO structures includes providing a substrate containing regions of first, second and third kinds in which devices with respective first, second and third gate oxide layers of different thicknesses are to be formed. The second gate oxide layer is formed over the substrate and then removed from regions of the first kind where the first gate oxide layer is subsequently grown. A first conductive layer is deposited over the substrate. The first conductive layer and second gate oxide layer are subsequently removed from regions of the third kind. The third gate oxide layer followed by deposition of a second conductive layer is formed over the substrate and then removed except from over regions of the third kind.

Abstract: An example of the present application is directed to an integrated circuit having a first plurality of transistors and a second plurality of transistors. Each of the first plurality of transistors comprises a first gate structure oriented in a first direction and each of the second plurality of transistors comprises a second gate structure oriented in a second direction. Each of the first plurality of transistors are formed with at least one more pocket region than each of the second plurality of transistors. Methods for forming the integrated circuit devices of the present application are also disclosed.

Abstract: Semiconductor devices with selective stress memory effect and fabrication methods thereof. The semiconductor device comprises a semiconductor substrate with a first region and a second region. Both the first region and the second region have a first doped region and a second doped region separated by an insulation layer. A PMOS transistor is disposed on the first doped region layer. An NMOS transistor is disposed on the second doped region. A first capping layer is disposed covering the NMOS transistor over the first region. A second capping layer is disposed covering the PMOS transistor over the first region. The thickness of the first capping layer is different from the thickness of the second capping layer, thereby different stress is induced on the PMOS transistor and the NMOS transistor respectively. The PMOS transistor and the NMOS transistor over the second region are silicided.

Abstract: A nanostructure comprising germanium, including wires of less than 1 micron in diameter and walls of less than 1 micron in width, in contact with the substrate and extending outward from the substrate is provided along with a method of preparation.

Abstract: A method of packaging a semiconductor includes providing a support structure. An adhesive layer is formed overlying the support structure and is in contact with the support structure. A plurality of semiconductor die is placed on the adhesive layer. The semiconductor die are laterally separated from each other and have electrical contacts that are in contact with the adhesive layer. A layer of encapsulating material is formed overlying and between the plurality of semiconductor die and has a distribution of filler material. A concentration of the filler material is increased in all areas laterally adjacent each of the plurality of semiconductor die.

Abstract: The present invention discloses improved method for manufacturing semiconductor device wherein the gate oxide films in the cell region, VPP peripheral circuit region and VDD peripheral circuit region are formed to have different thicknesses from one another so that the threshold voltage of the cell transistor may be increased to a desired value as well as increasing the operation speed of the transistor and suppress the short channel effect.

Abstract: A MEMS microphone module having an application specific IC and a microphone chip is disclosed. The application specific IC has a plurality of first vias and a plurality of first pads, and the first vias are connected to the first pads. The microphone chip has a resonant cavity, a plurality of second vias and a plurality of second pads, and the second vias are connected to the second pads. The microphone chip is disposed on a first surface of the application specific IC with an opening of the resonant cavity facing toward a first surface of the application specific IC. The second conductive vias of the microphone chip are also electrically connected to the first vias of the application specific IC. By placing the microphone chip on the first surface of the application specific IC, the present invention could reduce the package size and increase the reliability of the package.

Abstract: The embodiment relates to a complementary metal oxide semiconductor (CMOS) image sensor and more particularly, to a CMOS image sensor and a manufacturing method thereof capable of improving electron storing capacity in a floating diffusion area. The CMOS image sensor includes a first gate electrode on a semiconductor substrate; a photodiode in the semiconductor substrate on one side of the first gate electrode; a floating diffusion area in the semiconductor substrate on an opposite side of the first gate electrode; a capacitor including a lower capacitor electrode connected to the floating diffusion area, a dielectric layer on the lower capacitor electrode, and an upper capacitor electrode; a drive capacitor coupled to the lower capacitor electrode and having a second gate electrode connected to the floating diffusion area. The electron storing capacity of the floating diffusion node is increased, making it possible to improve the dynamic range of the image sensor.

Abstract: A method is provided for manufacturing an integrated circuit having a plurality of MOSFET devices, comprising the steps of: providing a plurality of MOSFET devices each having a first and a second structural parameter associated therewith, wherein a value of one of the first and a second structural parameter of each device is selected to provide a value of a performance parameter of the device substantially equal to a predetermined reference value, the predetermined reference value being the same for each device.

Abstract: The present invention relates to light emitting diodes, LEDs. In particular the invention relates to a LED comprising a nanowire as an active component. The nanostructured LED according to the embodiments of the invention comprises a substrate and at an upstanding nanowire protruding from the substrate. A pn-junction giving an active region to produce light is present within the structure. The nanowire, or at least a part of the nanowire, forms a wave-guiding section directing at least a portion of the light produced in the active region in a direction given by the nanowire.

Abstract: An image sensor and a method for manufacturing the same. In one example embodiment of the invention, an image sensor includes a semiconductor substrate in which a plurality of photodiodes are formed, an insulating layer formed on the semiconductor substrate, a color filter layer formed on the insulating layer, a planarization layer formed on a whole surface of the resultant comprising the color filter layer and having a plurality of concave parts disposed at regular intervals, and a plurality of micro lenses formed within each of the concave portions of the planarization layer and disposed at regular intervals.

Abstract: A method for manufacturing passive components is disclosed. First, a substrate is provided, and a connecting region, a capacitor region and an inductance region are defined in the substrate. The substrate includes a first metal layer and an insulating layer on the first metal layer. Subsequently, the insulating layer is etched, and then the first metal layer is etched. Thus, an outer connecting pad in the connecting region and a bottom electrode in the capacitor region are formed simultaneously, and a part of the insulating layer on the bottom electrode remains. Thereafter, a dielectric layer is deposited, and then a dual damascene copper process is performed to form an inductance structure and a top electrode of a capacitor in the dielectric layer simultaneously. Next, a passive layer is deposited and an etching process is thereafter performed to expose the outer connecting pad.

Abstract: An electronic circuit on a semiconductor substrate having isolated multiple gate field effect transistor circuit blocks is disclosed. In some embodiments, an electronic circuit has a substrate having a buried oxide insulating region. A MuGFET device may be formed above the buried oxide region and coupled to a first source of reference potential. A semiconductor device may be formed above the substrate and coupled to a second source of reference potential. A coupling network may be formed to couple the MuGFET device to the semiconductor device.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.

Abstract: In a semiconductor device and a method of fabrication thereof, a semiconductor device comprises a substrate including transistors and partitioned into a memory region and a logic region. A bit line is electrically connected to at least one of the transistors in the memory region. A logic capacitor is formed on the logic region. The logic capacitor includes a logic lower metal electrode of a same layer as that of the bit line, a logic dielectric film, and a logic upper metal electrode.

Abstract: A trenched semiconductor power device that includes a trenched gate disposed in an extended continuous trench surrounding a plurality of transistor cells wherein the layout of the trenched gate surrounding the transistor cells as closed cells having truncated corners or rounded corners. In an exemplary embodiment, the closed cells further includes a contact metal to contact a source and a body regions wherein the contact metal the trenched gate surrounding the transistor cell have a uniform space between them. In another exemplary embodiment, the semiconductor power device further includes a contact dopant region disposed below the contact metal to enhance an electrical contact between the metal contact and the source region and the body region, and the contact dopant region having substantially circular shape to achieve a uniform space between the contact dopant region and the trenched gate surrounding the closed cells.

Abstract: A method and device for image sensing. The method includes forming a first well and a second well in a substrate, forming a gate oxide layer on the substrate, and depositing a first gate region and a second gate region on the gate oxide layer. The first gate region is associated with the first well, and the second gate region is associated with the second well. Additionally, the method includes forming a third well in the substrate, implanting a first plurality of ions to form a first lightly doped source region and a first lightly doped drain region in the first well, implanting a second plurality of ions to form at least a second lightly doped drain region in the second well, and implanting a third plurality of ions to form a source in the second well.

Abstract: A semiconductor device and a method for forming it are described. The semoiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.

Abstract: A transistor, which is formed in a semiconductor substrate having a top surface, includes first and second source/drain regions, a channel connecting the first and second source/drain regions, and a gate electrode for controlling an electrical current flowing in the channel. The gate electrode is disposed in a lower portion of a gate groove defined in the top surface of the semiconductor substrate. The upper portion of the groove is filled with an insulating material. The channel includes a fin-like portion in the shape of a ridge having a top side and two lateral sides in a cross-section perpendicular to a direction defined by a line connecting the first and second source/drain regions. The gate electrode encloses the channel at the top side and the two lateral sides thereof.

Abstract: A method for forming TGO structures includes providing a substrate containing regions of first, second and third kinds in which devices with respective first, second and third gate oxide layers of different thicknesses are to be formed. The second gate oxide layer is formed over the substrate and then removed from regions of the first kind where the first gate oxide layer is subsequently grown. A first conductive layer is deposited over the substrate. The first conductive layer and second gate oxide layer are subsequently removed from regions of the third kind. The third gate oxide layer followed by deposition of a second conductive layer is formed over the substrate and then removed except from over regions of the third kind.

Abstract: The package substrate of the present invention comprises a carrying board, bump pads, wire bonding pads, a solder mask, metallic bumps, and a metallic protective layer. The solder pads and the wire bonding pads are disposed on the surface of the carrying board. The solder mask is patterned to expose bump pads, wire bonding pads, and part of the surface of the substrate on the periphery of the wire bonding pads. The metallic bumps are disposed on the surface of the bump pads and extend to the surface of the solder mask. The metallic protective layer is disposed on the surfaces of the metallic bumps and the wire bonding pads. Besides, a method for manufacturing this package substrate, a semiconductor package structure comprising this package substrate, and a manufacturing method thereof are disclosed. Therefore, the manufacturing process of the package substrate is simple, and the package substrate is slim.