Abstract: A method of making semiconductor die terminals and a semiconductor device with die terminals made according to the present method. At least a first mask layer is selectively printed on at least a portion of a wafer containing a plurality of the semiconductor devices to create first recesses aligned with electrical terminals on the semiconductor devices. A conductive material is deposited in a plurality of the first recesses to form die terminals on the semiconductor devices. The first mask layer is removed to expose the die terminals, and the wafer is diced into a plurality of discrete semiconductor devices.

Abstract: A pressure sensor system comprising a pressure sensor chip is disclosed. The pressure sensor chip comprises a sensing side where pressure sensing is performed and one or more interconnections where electrical connections are made at the other side of the chip. The pressure sensor comprising an integrated circuit (1) forming a substrate, the substrate comprising a membrane shaped portion adapted for being exposed to the pressure, the integrated circuit (1) comprising both pressure signal sensing components and pressure signal processing components.

Abstract: Embodiments of microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the fabrication method includes printing a patterned die attach material onto the backside of a wafer including an array of non-singulated microelectronic die each having an interior keep-out area, such as a central keep-out area. The die attach material, such as a B-stage epoxy, is printed onto the wafer in a predetermined pattern such that the die attach material does not encroaching into the interior keep-out areas. The wafer is singulated to produce singulated microelectronic die each including a layer of die attach material. The singulated microelectronic die are then placed onto leadframes or other package substrates with the die attach material contacting the package substrates. The layer of die attach material is then fully cured to adhere an outer peripheral portion of the singulated microelectronic die to its package substrate.

Abstract: A method to prevent contamination of the principal surface side in a process of grinding the back surface side of a semiconductor wafer. At an intersection of a scribe region of a semiconductor wafer whose back surface side is to be ground, a plurality of insulating layers is laminated over the principal surface in the same manner as an insulating layer constituting a wiring layer laminated over a device region. Moreover, in the same layer as an uppermost wiring disposed at the uppermost layer among a plurality of the wiring layers formed for a device region, a metal pattern is formed. Furthermore, a second insulating layer covering the uppermost wiring is also formed over the metal pattern so as to cover the same.

Abstract: A method of processing wafers for saving material and protecting environment is implemented to collect defective or incomplete wafers and perform cutting operation to create a plurality of separate dies. According to the requirement of a specification, the backs of the dies are grinded to allow each die to have a predetermined thickness. Thereafter, the grinded dies with completeness are sequentially placed onto a carrying means. With the method, the defective or incomplete wafers, which would be discarded in general wafer manufacturing, may be reclaimed to go through cutting, grinding, and selecting operations, so that the dies with completeness on the defective wafers can be picked out and processed again, so as to increase the yield, lower the manufacturing cost, reduce the amount of the wafer waste, increase the wafer utilization, and meet the demands of energy saving, carbon reduction, and environmental protection.

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly.

Abstract: There is provided a laser processing method of a sapphire substrate including preparing a sapphire substrate on which plural stacked portions spaced from each other are formed, irradiating a short pulse laser beam from a laser light source, making the laser beam irradiated from the laser light source pass through a beam shaping module, adjusting a position of a light concentrating unit or the sapphire substrate such that the laser beam is concentrated to the inside of the sapphire substrate through the light concentrating unit, and forming a phase transformation area within the sapphire substrate by irradiating the laser beam into the sapphire substrate. The laser beam is introduced into the sapphire substrate while avoiding an area where the stacked portions are formed on the sapphire substrate, so that the phase transformation area is formed within the sapphire substrate.

Abstract: Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die.

Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor stack, a first electrode, a second electrode, a first interconnect, an insulating film, and a second interconnect. The semiconductor stack includes a first major surface, a second major surface provided on a side opposite to the first major surface, a side face, and a light emitting layer. The first electrode is provided on the first major surface. The second electrode is provided at least on a peripheral portion of the second major surface. The first interconnect is provided on the first electrode. The insulating film is provided on the side face of the semiconductor stack. The second interconnect is provided on the side face of the semiconductor stack via the insulating film. The second interconnect is connected to the second electrode in outside of the peripheral portion of the second major surface of the semiconductor stack.

Abstract: An active device substrate includes a flexible substrate, an inorganic de-bonding layer, and at least one active device. The flexible substrate has a first surface and a second surface opposite to the first surface, wherein the first surface is a flat surface. The inorganic de-bonding layer covers the first surface of the flexible substrate, and the material of the inorganic de-bonding layer is metal, metal oxide or combination thereof. The active device is disposed on or above the second surface of the flexible substrate.

Abstract: Method for bonding of a plurality of chips onto a base wafer which contains chips on the front, the chips being stacked in at least one layer on the back of the base wafer and electrically conductive connections are established between the vertically adjacent chips, with the following steps: a) fixing of the front of the base wafer on a carrier, b) placing at least one layer of chips in defined positions on the back of the base wafer, and c) heat treatment of the chips on the base wafer fixed on the carrier, characterized in that prior to step c) at least partial separation of the chips of the base wafer into separated chip stack sections of the base after takes place.

Abstract: In a wafer processing method, a modified layer is formed inside a wafer along planned dividing lines by irradiating the wafer with a laser beam with such a wavelength as to be transmitted through the wafer from the back surface side of the wafer along the dividing lines. A first modified layer is formed near the back surface of the wafer by irradiating the wafer with the light focal point of the laser beam positioned near the back surface of the wafer. The wafer is then irradiated with the light focal point of the laser beam positioned on the front surface side. Then plural second modified layers are formed in a multi-layering manner with sequential movement of the light focal point toward an area leading to the first modified layer. The wafer is divided into individual devices along the dividing lines by applying an external force to the wafer.

Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of reducing edge warping in a supported semiconductor wafer involves adhering a backside of a semiconductor wafer to an inner portion of a carrier tape of a substrate carrier comprising a tape frame mounted above the carrier tape. The method also involves adhering an adhesive tape to a front side of the semiconductor wafer and to at least a portion of the substrate carrier. The adhesive tape includes an opening exposing an inner region of the front side of the semiconductor wafer.

Abstract: The present invention provides a dicing method that achieves excellent dicing properties at low costs by removing a metal film through a metal processing operation with a diamond tool and then performing pulse laser beam irradiation. The dicing method is a method of dicing a substrate to be processed, devices being formed in the substrate to be processed, a metal film being formed on one surface of the substrate to be processed.

Abstract: According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets.

Abstract: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.

Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer by forming trenches along singulation lines and initiating a cracks from within the trenches, which propagate through the semiconductor wafer in a more controlled manner.

Abstract: A method includes forming a dielectric layer over a substrate, forming an interconnect structure over the dielectric layer, and bonding a die to the interconnect structure. The substrate is then removed, and the dielectric layer is patterned. Connectors are formed at a surface of the dielectric layer, wherein the connectors are electrically coupled to the die.

Abstract: In a wafer dicing press for reducing time and cost for wafer dicing and for evenly applying a dicing pressure to a whole wafer, a wafer dicing press includes a support unit supporting a first side of a wafer; and a pressurization device applying a pressure, by dispersing the pressure, to a second side of the wafer so that a laser-scribed layer of the wafer operates as a division starting point. Accordingly, the wafer dicing press reduces laser radiation and pressure-application times for dividing a wafer into semiconductor devices. This increased efficiency is achieved without increasing the likelihood of damaging the wafer.

Abstract: The present invention aims to enhance the light extraction efficiency of the Group III nitride semiconductor light-emitting device. The inventive Group III nitride semiconductor light-emitting device comprises a substrate; and a Group III nitride semiconductor layer including a light-emitting layer, stacked on the substrate, wherein the side face of the Group III nitride semiconductor layer is tilted with respect to the normal line of the major surface of the substrate.

Abstract: Fractures (17a, 17b) are generated from modified regions (7a, 7b) to front and rear faces (12a, 12b) of a object to be processed (1), respectively, while an unmodified region (2) is interposed between the modified regions (7a, 7b). This can prevent fractures from continuously advancing in the thickness direction of a silicon substrate (12) when forming a plurality of rows of modified regions (7). By generating a stress in the object (1), the fractures (17a, 17b) are connected to each other in the unmodified region (2), so as to cut the object (1). This can prevent fractures from meandering in the rear face (12b) of the object (1) and so forth, whereby the object (1) can be cut accurately along a line to cut the object (5).

Abstract: A method for fabricating semiconductor devices includes: (a) forming a layered structure that includes a temporary substrate, a plurality of spaced apart sacrificial film regions on the temporary substrate, and a plurality of valley-and-peak areas among the sacrificial film regions; (b) growing laterally and epitaxially an epitaxial film layer over the sacrificial film regions and the valley-and-peak areas, wherein gaps are formed among the epitaxial film layer and the valley-and-peak areas; (c) forming a conductive layer to contact the epitaxial film layer; (d) forming a plurality of grooves to divide the epitaxial film layer and the conductive layer into a plurality of epitaxial structures on the temporary substrate; and (e) removing the temporary substrate and the sacrificial film regions from the epitaxial structures by etching the sacrificial film regions through the gaps and the grooves.

Abstract: A method of singulating semiconductor devices in the close proximity to active structures by controlling interface charge of semiconductor device sidewalls is provided that includes forming a scribe on a surface of a semiconductor devices, where the scribe is within 5 degrees of a crystal lattice direction of the semiconductor device, cleaving the semiconductor device along the scribe, where the devices are separated, using a coating process to coat the sidewalls of the cleaved semiconductor device with a passivation material, where the passivation material is disposed to provide a fixed charge density at a semiconductor interface of the sidewalls, and where the fixed charge density interacts with charge carriers in the bulk of the material.

Abstract: A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are uncovered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer.

Abstract: A processing method for a wafer which has, on a surface thereof, a device region in which a plurality of devices are formed and partitioned by division lines and an outer periphery excess region surrounding the device region, includes a dividing groove formation step of irradiating a laser beam of a wavelength having absorbability by a wafer along the division lines to form dividing grooves serving as start points of cutting, and a dividing step of applying external force to the wafer on which the dividing grooves are formed to cut the wafer into the individual devices. At the dividing groove formation step, the dividing grooves are formed along the division lines in the device region while a non-processed region is left in the outer periphery excess region on extension lines of the division lines.

Abstract: A method of manufacturing a solar cell, which includes an edge deletion step using a laser beam, and a manufacturing apparatus which is used in such a method, the method and the apparatus being capable of preventing a shunt and cracks from being generated are provided. By radiating a first laser beam to a multilayer body, which includes a transparent electrode layer, a photoelectric conversion layer, and a back electrode layer sequentially formed on a transparent substrate, from a side of the transparent substrate, the photoelectric conversion layer and the back electrode layer in a first region are removed, and by radiating a second laser beam into the region such that the second laser beam is spaced from a peripheral rim of the region, the transparent electrode layer in a second region is removed.

Abstract: A differential pressure sensor comprises a membrane arranged over a cavity on a semiconductor substrate. A lid layer is arranged at the top side of the device and comprises an access opening for providing access to the top side of the membrane. A channel extends laterally from the cavity and intersects with a bore. The bore is formed by laser drilling from the bottom side of the substrate and provides access to the bottom side of the membrane. The bore extends all through the substrate and optionally into the lid layer.

Abstract: A method of forming a capped die forms a cap wafer having a top side and a bottom side. The bottom side is formed with 1) a plurality of device cavities having a first depth, and 2) a plurality of second cavities that each have a greater depth than the first depth. At least some of the plurality of second cavities each generally circumscribe at least one of the device cavities. The method then secures the cap wafer to a device wafer in a manner that causes a plurality of the device cavities each to circumscribe at least one of circuitry and structure on the device wafer. Next, the method removes at least a portion of the top side of the cap wafer to expose the second cavities. This forms a plurality of caps that each protect the noted circuitry and structure.

Abstract: In accordance with an embodiment of the present invention, a method of fabricating a semiconductor device includes forming a trench from a top surface of a substrate having a device region. The device region is adjacent to the top surface than an opposite bottom surface. The trench surrounds the sidewalls of the device region. The trench is filled with an adhesive. An adhesive layer is formed over the top surface of the substrate. A carrier is attached with the adhesive layer. The substrate is thinned from the bottom surface to expose at least a portion of the adhesive and a back surface of the device region. The adhesive layer is removed and adhesive is etched to expose a sidewall of the device region.

Abstract: Semiconductor device packages comprise a first semiconductor device comprising a heat-generating region located on at least one end thereof. A second semiconductor device is attached to the first semiconductor device. At least a portion of the heat-generating region extends laterally beyond at least one corresponding end of the second semiconductor device. A thermally insulating material at least partially covers the end of the second semiconductor device. Methods of forming a semiconductor device packages comprise attaching a second semiconductor device to a first semiconductor device. The first semiconductor device comprises a heat-generating region at an end thereof. At least a portion of the heat-generating region extends laterally beyond an end of the second semiconductor device. The end of the second semiconductor device is at least partially covered with a thermally insulating material.

Abstract: The invention provides a semiconductor device and a method of automatically inspecting the appearance, which achieves proper recognition of the size of a chipping occurring from an end portion of the semiconductor device toward the element forming region by an automatic appearance inspection machine, and prevents a problem of judging an appearance non-defective product as an appearance defective product. A semiconductor device includes a resin layer extending from an element forming region over a guard ring surrounding the element forming region so as to cover these except a plurality of portions of the guard ring, and a chipping extending from a chip end portion of a semiconductor device toward the end portion of the resin layer.

Abstract: A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.

Abstract: Provided are: a table on which a workpiece is placed, a laser oscillator emitting a laser beam; a light-guide optical system deflecting the beam emitted from the oscillator; a cylindrical extensible bellows surrounding an optical path of the beam after the light-guide optical system deflects the beam; a bend mirror moving in an axial direction of the bellows while extending/contracting the bellows and deflecting the beam having passed through the bellows toward the table; a machining head irradiating the workpiece with the beam deflected by the mirror; an abnormality detector including a beam-sensor light-emitting unit emitting a beam advancing parallel with an axis of the bellows and a beam-sensor light-receiving unit measuring the amount of received light of the beam; and a control device bringing down the laser oscillator when the amount of received light of the beam in the beam-sensor light-receiving unit falls below a first threshold.

Abstract: A method for manufacturing a chip constituted by a functional device formed on a substrate comprises a functional device forming step of forming the functional device on one main face of a sheet-like object to be processed made of silicon; a first modified region forming step of converging a laser light at the object so as to form a first modified region along the one main face of the object at a predetermined depth corresponding to the thickness of the substrate from the one main face; a second modified region forming step of converging the laser light at the object so as to form a second modified region extending such as to correspond to a side edge of the substrate as seen from the one main face on the one main face side in the object such that the second modified region joins with the first modified region along the thickness direction of the object; and an etching step of selectively advancing etching along the first and second modified regions after the first and second modified region forming steps so

Abstract: An epoxy resin composition having excellent connection reliability and transparency, a method for manufacturing a composite unit using the epoxy resin composition, and the composite unit, are disclosed. The manufacturing method includes an attaching step of attaching an epoxy resin composition (2) containing a novolak phenolic curing agent, an acrylic elastomer composed of a copolymer containing dimethylacrylamide and hydroxylethyl methacrylate, an epoxy resin and not less than 5 parts by weight to not more than 20 parts by weight of an inorganic filler to 100 parts by weight of the epoxy resin, to a printed circuit board (1) in the form of a sheet.

Abstract: An embodiment is a device comprising a semiconductor die, an adhesive layer on a first side of the semiconductor die, and a molding compound surrounding the semiconductor die and the adhesive layer, wherein the molding compound is at a same level as the adhesive layer. The device further comprises a first post-passivation interconnect (PPI) electrically coupled to a second side of the semiconductor die, and a first connector electrically coupled to the first PPI, wherein the first connector is over and aligned to the molding compound.

Abstract: Aspects and examples include electrical components and methods of forming electrical components. In one example, a method includes selecting a substrate, forming a pattern of a first conductive material on a top surface of the substrate, forming a pattern of a second conductive material on a bottom surface of the substrate, dicing the substrate into one or more die having a first diced surface and a second diced surface, securing the first diced surface of each of the one or more die to a retaining material, encapsulating the one or more die in an encapsulent to form a reconstituted wafer, and forming a pattern of a third conductive material on the second diced surface by metalizing a surface of the reconstituted wafer.

Abstract: A semiconductor device 100 includes a first insulating material 110 attached to a second main surface 106b of a semiconductor chip 106, and a second insulating material 112 attached to side surfaces of the semiconductor chip 106, the first insulating material 110 and an island 102. The semiconductor chip 106 is fixed to the island 102 via the first insulating material 110 and the second insulating material 112. The first insulating material 110 ensures a high dielectric strength between the semiconductor chip 106 and the island 102. Though the second insulating material 112 having a modulus of elasticity greater than that of the first insulating material 110, the semiconductor chip 106 is firmly attached to the island 102.

Abstract: Techniques for fabricating metal devices, such as vertical light-emitting diode (VLED) devices, power devices, laser diodes, and vertical cavity surface emitting laser devices, are provided. Devices produced accordingly may benefit from greater yields and enhanced performance over conventional metal devices, such as higher brightness of the light-emitting diode and increased thermal conductivity. Moreover, the invention discloses techniques in the fabrication arts that are applicable to GaN-based electronic devices in cases where there is a high heat dissipation rate of the metal devices that have an original non- (or low) thermally conductive and/or non- (or low) electrically conductive carrier substrate that has been removed.

Abstract: A package body (1) with an upper side (2), with an underside (22), opposite from the upper side (2), and with a side surface, which connects the upper side (2) and the underside (22) and is provided as a mounting surface (19), the package body (1) having a plurality of layers (8) which contain a ceramic material, and a main direction of extent of the layers (23, 24, 25) running obliquely in relation to the mounting surface (19). Furthermore, a method for producing a package body (1) is provided.

Abstract: A semiconductor wafer with an assisting dicing structure. The wafer comprises a substrate having a front surface and a rear surface. The front surface of the substrate comprises at least two device regions separated by at least one dicing lane. The rear surface of the substrate comprises at least one pre-dicing trench formed therein and substantially aligned with the dicing lane. A method for dicing a semiconductor wafer is also disclosed.

Abstract: In a high frequency module, electronic components are mounted on a mounting surface of a collective substrate including a plurality of unit substrates that include a via conductor electrically conducted to a ground potential in a peripheral portion thereof, and the mounting surface and the electronic components are encapsulated with an encapsulation layer. The collective substrate is cut on the encapsulation layer side, thereby forming a half-cut groove penetrating through the encapsulation layer and extending halfway along the collective substrate in a thickness direction such that the via conductor is exposed only at a bottom surface of the half-cut groove. A conductive shield layer is formed to cover the encapsulation layer and is electrically conducted to the exposed via conductor. The collective substrate is then cut into individual unit substrates each including the conductive shield layer electrically conducted to the ground potential through the via conductor.

Abstract: A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.

Abstract: A method for fabricating semiconductor devices includes: (a) forming a layered structure that includes a temporary substrate, a plurality of spaced apart sacrificial film regions on the temporary substrate, and a plurality of valley-and-peak areas among the sacrificial film regions; (b) growing laterally and epitaxially an epitaxial film layer over the sacrificial film regions and the valley-and-peak areas, wherein gaps are formed among the epitaxial film layer and the valley-and-peak areas; (c) forming a conductive layer to contact the epitaxial film layer; (d) forming a plurality of grooves to divide the epitaxial film layer and the conductive layer into a plurality of epitaxial structures on the temporary substrate; and (e) removing the temporary substrate and the sacrificial film regions from the epitaxial structures by etching the sacrificial film regions through the gaps and the grooves.

Abstract: A method for assembling die packages includes attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier. The composite carrier includes a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer. The composite carrier minimizes effects of the CTE mismatch between the die and the package substrate during assembly reduces warpage of the die. After the attaching, the semiconductor wafer is removed from the package substrate. Electrically conductive connectors are attached to the bottom surface of the package substrate, and the package substrate is sawed to form a plurality of singulated die packages.

Abstract: A light emitting device is disclosed. The light emitting device includes a first conductive type semiconductor layer, an active layer disposed on the first conductive type semiconductor layer, a tunnel junction layer comprising a second conductive type nitride semiconductor layer and a first conductive type nitride semiconductor layer disposed on the active layer, wherein the first conductive type nitride semiconductor layer and the second conductive type nitride semiconductor layer are PN junctioned, a first electrode disposed on the first conductive type semiconductor layer, and a second electrode disposed on the first conductive type nitride semiconductor layer, wherein a portion of the second electrode is in schottky contact with the second conductive type nitride semiconductor layer through the first conductive type nitride semiconductor layer.

Abstract: A wafer processing method of dividing a wafer along streets. The wafer processing method includes a protective tape attaching step of attaching a protective tape to the front side of the wafer, a modified layer forming step of holding the wafer through the protective tape on a chuck table of a laser processing apparatus under suction and next applying a laser beam having a transmission wavelength to the wafer from the back side of the wafer along the streets, thereby forming a modified layer inside the wafer along each street, and a wafer dividing step of canceling suction holding of the wafer by the chuck table and next applying an air pressure to the wafer now placed on the holding surface in the condition where horizontal movement of the wafer is limited, thereby dividing the wafer along each street where the modified layer is formed, thus obtaining individual devices.

Abstract: A method for preparing a semiconductor wafer into individual semiconductor dies uses both a dicing before grinding step and/or via hole micro-fabrication step, and an adhesive coating step.

Abstract: A semiconductor chip package structure for achieving flip-chip electrical connection without using a wire-bonding process includes a package unit, a semiconductor chip, a first insulative layer, first conductive layers, a second insulative layer, and second conductive layers. The package unit has a receiving groove. The semiconductor chip is received in the receiving groove and has a plurality of conductive pads disposed on its top surface. The first insulative layer is formed between the conductive pads to insulate the conductive pads. The first conductive layers are formed on the first insulative layer and the package unit, and one side of each first conductive layer is electrically connected to the corresponding conductive pad. The second insulative layer is formed between the first conductive layers in order to insulate the first conductive layers from each other. The second conductive layers are respectively formed on the other opposite sides of the first conductive layers.

Abstract: A semiconductor wafer includes: a first semiconductor chip area formed with a semiconductor element; a second semiconductor chip area formed with a semiconductor element; and a scribe area sandwiched between the first and second semiconductor chip areas; wherein: the first semiconductor chip area includes a first metal ring surrounding the semiconductor element formed in the first semiconductor chip area; and the metal ring is constituted of a plurality of metal layers including a lower metal layer and an upper metal layer superposed upon the lower metal layer, and the upper metal layer is superposed upon the lower metal layer in such a manner that an outer side wall of the upper metal layer is flush with the outer side wall of the lower metal layer or is at an inner position of the first semiconductor chip area relative to the outer side wall of the lower metal layer.