Abstract: A method of manufacturing a semiconductor package includes embedding a semiconductor chip in an encapsulant. First contact pads are formed on a first main face of the semiconductor package and second contact pads are formed on a second main face of the semiconductor package opposite the first main face. A diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d?(8/25)x+142 ?m, where x is a pitch of the second contact pads in micrometers.

Abstract: A method for manufacturing an SOI wafer that has an SOI layer formed on a buried insulator layer and is suitable for photolithography with an exposure light having a wavelength ? comprises: designing a thickness of the buried insulator layer of the SOI wafer on the basis of the wavelength ? of the exposure light utilized for the photolithography that is to be performed on the SOI wafer after manufacturing; and fabricating the SOI wafer that has the SOI layer formed on the buried insulator layer having the designed thickness. As a result, there is provided a method for designing an SOI wafer and a method for manufacturing an SOI wafer that enable the variation in the reflection rate of the exposure light due to the variation in the SOI layer thickness and hence variation in the exposure state of a resist to be inhibited in a photolithography operation.

Abstract: Consistent with an example embodiment, there is an integrated circuit device (IC) built on a substrate of a thickness. The IC comprises an active device region of a shape, the active device region having a topside and an underside. Through silicon vias (TSVs) surround the active device region, the TSVs having a depth defined by the substrate thickness. On the underside of and having the shape of the active device region, is an insulating layer. A thin-film conductive shield is on the insulating layer, the conductive shield is in electrical contact with the TSVs.

Abstract: To provide an olefinic expandable substrate and a dicing film that exhibits less contamination characteristics, high expandability without necking, which cannot be achieved by conventional olefinic expandable substrates. In order to achieve the object, an expandable film comprises a 1-butene-?-olefin copolymer (A) having a tensile modulus at 23° C. of 100 to 500 MPa and a propylenic elastomer composition (B) comprising a propylene-?-olefin copolymer (b1) and having a tensile modulus at 23° C. of 10 to 50 MPa, wherein the amount of the component (B) is 30 to 70 weight parts relative to 100 weight parts in total of components (A) and (B).

Abstract: Fractures (17a, 17b) are generated from modified regions (7a, 7b) to front and rear faces (12a, 12b) of a object to be processed (1), respectively, while an unmodified region (2) is interposed between the modified regions (7a, 7b). This can prevent fractures from continuously advancing in the thickness direction of a silicon substrate (12) when forming a plurality of rows of modified regions (7). By generating a stress in the object (1), the fractures (17a, 17b) are connected to each other in the unmodified region (2), so as to cut the object (1). This can prevent fractures from meandering in the rear face (12b) of the object (1) and so forth, whereby the object (1) can be cut accurately along a line to cut the object (5).

Abstract: Methods of manufacturing a flat-pack no-lead microelectronic package (2100) coat exposed base metal at a cut end of a lead frame of the package with solder (1001). One method coats the exposed base metal with solder when the package is in a strip (200, 300). Another method coats the exposed base metal with solder after the package is singulated. As a result, all portions of leads of the package that may receive solder during mounting of the package to a printed circuit board are solder wettable. A solder wettable lead end (504) on the package facilitates formation of a solder fillet during mounting of the package.

Abstract: A method is provided for forming an integrated circuit having a diode. The method includes forming at least one fin in a shallow trench isolation (STI) oxide layer disposed above a substrate layer. The at least one fin extends from a bottom end adjacent the substrate layer to a top end. The method further includes adding a cathode implant in a first region of the at least one fin and the substrate layer and adding an anode implant in a second region of the at least one fin and the substrate layer such that a junction is formed in the substrate layer below the at least one fin. The method also includes etching away a portion of the STI oxide layer to expose the top end of the at least one fin.

Abstract: Various semiconductor workpieces and methods of dicing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a channel in a metallization structure on a backside of a semiconductor workpiece. The semiconductor workpiece includes a substrate. The channel is in substantial alignment with a dicing street on a front side of the semiconductor chip.

Abstract: The present invention provides a dicing tape-integrated film for semiconductor back surface, including a film for flip chip type semiconductor back surface for protecting a back surface of a semiconductor element flip chip-connected onto an adherend, and a dicing tape, the dicing tape including a base material and a pressure-sensitive adhesive layer provided on the base material, the film for flip chip type semiconductor back surface being formed on the pressure-sensitive adhesive layer, in which the pressure-sensitive adhesive layer is a radiation-curable pressure-sensitive adhesive layer whose pressure-sensitive adhesive force toward the film for flip chip type semiconductor back surface is decreased by irradiation with a radiation ray.

Abstract: Under bump passive structures, such as capacitors and inductors, may be formed using the post-processing layers in wafer level packaging. In an embodiment, a packaged semiconductor device is described which includes an under-bump capacitor formed in semiconductor device post-processing layers. As part of the post-processing a first dielectric layer is deposited on the active face of a semiconductor die and then in sequence a first metal layer, second dielectric layer and second metal layer are deposited. The under-bump capacitor is formed from a lower plate in the first metal layer and an upper plate in the second metal layer, the plates being separated by the second dielectric layer. In order to increase capacitance, the capacitor may be formed over one or more openings in the first dielectric layer, such that the layers forming the capacitor are no longer planar but follow the underlying topology.

Abstract: Disclosed is a method for testing multi-chip stacked packages. Initially, one or more substrate-less chip cubes are provided, each consisting of a plurality of chips such as chips stacked together having vertically connected with TSV's where there is a stacked gap between two adjacent chips. Next, the substrate-less chip cubes are adhered onto an adhesive tape where the adhesive tape is attached inside an opening of a tape carrier. Then, a filling encapsulant is formed on the adhesive tape to completely fill the chip stacked gaps. Next, the tape carrier is fixed on a wafer testing carrier in a manner to allow the substrate-less chip cubes to be loaded into a wafer tester without releasing from the adhesive tape. Accordingly, the probers of the wafer tester can be utilized to probe testing electrodes of the substrate-less chip cubes so that it is easy to integrate this testing method in TSV fabrication processes.

Abstract: The present invention provides a dicing tape-integrated film for semiconductor back surface, which includes: a dicing tape including a base material and a pressure-sensitive adhesive layer provided on the base material; and a film for flip chip type semiconductor back surface provided on the pressure-sensitive adhesive layer, in which the film for flip chip type semiconductor back surface has a multilayered structure including a wafer adhesion layer and a laser mark layer, the wafer adhesion layer is formed of a resin composition containing a thermosetting resin component and, as an optional component, a thermoplastic resin component in an amount of less than 30% by weight relative to the whole amount of resin components, and the laser mark layer is formed of a resin composition containing a thermoplastic resin component in an amount of 30% by weight or more relative to the whole amount of resin components and, as an optional component, a thermosetting resin component.

Abstract: An element-group formation substrate (20) having plural semiconductor light emitting elements (21) formed on a substrate front surface (11a) is sequentially irradiated with a laser beam (64) having a first output from a substrate back surface (11b) side in the y direction, and the laser beam (64) is sequentially collected to a part having a first depth D1 from the substrate back surface (11b), thereby forming a first modified region L1. The substrate (20) having the first modified region L1 formed therein is sequentially irradiated with the laser beam (64) having a third output (<the first output) from the substrate back surface 11b side in the y direction, and the laser beam (64) is sequentially collected to a part having a third depth D3 from the substrate back surface (11b) shallower than the first depth D1, thereby forming a third modified region L3.

Abstract: A method of forming a charge pattern on a microchip includes depositing a material on the surface of the microchip, and immersing the microchip in a fluid to develop charge in or on the material through interaction with the surrounding fluid.

Abstract: A device includes a top package bonded to a bottom package. The bottom package includes a molding material, a device die molded in the molding material, a Through Assembly Via (TAV) penetrating through the molding material, and a redistribution line over the device die. The top package includes a discrete passive device packaged therein. The discrete passive device is electrically coupled to the redistribution line.

Abstract: A wafer in accordance with various embodiments may include: at least one metallization structure including at least one opening; and at least one separation line region along which the wafer is to be diced, wherein the at least one separation line region intersects the at least one opening.

Abstract: Methods, systems, and apparatuses for integrated circuit packages are provided. An integrated circuit package, such as a quad flat no-lead (QFN) package, includes a plurality of peripherally positioned leads, a heat spreader, an integrated circuit die, and an encapsulating material. The peripherally positioned leads are attached to a first surface of the heat spreader, and the die is attached to the first surface of the heat spreader within a ring formed by the leads. The encapsulating material encapsulates the die on the heat spreader, encapsulates bond wires, and fills a space between the leads. A second surface of the heat spreader is exposed from the package. End portions of the leads have surfaces that are flush with a surface of the package opposite the second surface of the heat spreader, and that are used as lands for the package.

Abstract: A semiconductor package includes a semiconductor chip, an inductor applied to the semiconductor chip. The inductor includes at least one winding. A space within the at least one winding is filled with a magnetic material.

Abstract: In one embodiment, a method of forming a semiconductor device comprises forming a groove on and/or over a first side of a substrate. A dicing layer is formed from a second side of the substrate using a laser process. The second side is opposite the first side. The dicing layer is disposed under the groove within the substrate. The substrate is singulated through the dicing layer.

Abstract: A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient leads when the resilient leads are in the first position. One or more attachment bumps may also be furnished to facilitate attachment of the device to the printed circuit board.

Abstract: The present invention is aimed to provide an adhesive for bonding a semiconductor which has high transparency and facilitates recognition of a pattern or position indication on the occasion of semiconductor chip bonding. The present invention is an adhesive for bonding a semiconductor containing: an epoxy resin; an inorganic filler; and a curing agent, wherein the amount of the inorganic filler in the adhesive is 30 to 70% by weight, the inorganic filler contains a filler A having an average particle size of less than 0.1 ?m and a filler B having an average particle size of not less than 0.1 ?m and less than 1 ?m, and the weight ratio of the filler A to the filler B is 1/9 to 6/4. The present invention is an adhesive for bonding a semiconductor containing: an epoxy resin; an inorganic filler; and a curing agent, wherein difference in refractive index is not more than 0.1 between the epoxy resin and the inorganic filler.

Abstract: The present invention provides a method for plasma processing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; loading a work piece onto the work piece support, the work piece having a support film, a frame and the substrate; providing a cover ring above the work piece, the cover ring having at least one perforated region, and at least one non-perforated region; generating a plasma using the plasma source; and processing the work piece using the generated plasma.

Abstract: One embodiment for forming a shaped substrate for an electronic device can form a shaped perimeter to define the substrate shape on the surface of a substrate. The shaped perimeter can extend at least part way into the substrate. A subsequent thinning process can remove substrate material and expose the shaped perimeter effectively forming shaped dies from the substrate.

Abstract: In a semiconductor wafer with a supporting tape attached to the back side of the wafer, a coating member having a refractive index close to that of the supporting tape is formed on a pear-skin surface of the supporting tape to thereby planarize the pear-skin surface. Thereafter, a pulsed laser beam is applied from the upper side of the coating member to the semiconductor wafer in the condition where the focal point of the pulsed laser beam is set at a predetermined depth in the semiconductor wafer. Accordingly, the pulsed laser beam can be sufficiently focused inside the semiconductor wafer to thereby well form a modified layer inside the semiconductor wafer.

Abstract: A package structure and fabrication method thereof. The structure includes a substrate having a terminal, a chip overlying the substrate, the chip having an active surface, having a center region and periphery region, the periphery region having an electrode thereon, a patterned cover plate overlying the chip and exposing the electrode, a conductive material electrically connecting the electrode and terminal, and an encapsulant covering the terminal, conductive material, and electrode, but exposing the cover plate overlying the center region of the chip.

Abstract: A wafer includes a plurality of chips, each of the chips being spaced from each other by kerf-line regions including a reduced width.

Abstract: Embodiments relate to IC current sensors fabricated using thin-wafer manufacturing technologies. Such technologies can include processing in which dicing before grinding (DBG) is utilized, which can improve reliability and minimize stress effects. While embodiments utilize face-up mounting, face-down mounting is made possible in other embodiments by via through-contacts. IC current sensor embodiments can present many advantages while minimizing drawbacks often associated with conventional IC current sensors.

Abstract: An integrated circuit is formed by coating a top surface of a wafer that has been processed through all integrated circuit chip manufacturing steps prior to backgrind with photoresist, applying backgrind tape over a top surface of the photoresist, backgrinding a back surface of the wafer to a specified thickness, removing the backgrind tape from the top surface of the photoresist, and removing the photoresist. The surface of the integrated circuit and any devices that may be bonded to the surface of the integrated circuit are protected by the photoresist layer during removal of the backgrind tape.

Abstract: A wafer includes a plurality of chips arranged as rows and columns. A first plurality of scribe lines is between the rows of the plurality of chips. Each of the first plurality of scribe lines includes a metal-feature containing scribe line comprising metal features therein, and a metal-feature free scribe line parallel to, and adjoining, the metal-feature containing scribe line. A second plurality of scribe lines is between the columns of the plurality of chips.

Abstract: A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array (310) designed for direct attachment to an array of integrated circuit die (306) by including a thermal interface adhesion layer (308) to each die (306) and encapsulating the attached heat spreader lid array (310) and array of integrated circuit die (306) with mold compound (321) except for planar upper lid surfaces of the heat spreader lids (312).

Abstract: A wafer is divided by setting the focal point of a laser beam inside the wafer at positions corresponding to division lines, thereby forming modified layers inside the wafer along the division lines. Each modified layer has a thickness ranging from the vicinity of the front side of the wafer to the vicinity of the back side of the wafer. An etching gas or an etching liquid is supplied to the wafer to erode the modified layers, thereby dividing the wafer into individual devices. The modified layers are not crushed, so fine particles are not generated in dividing the wafer. Accordingly, fine particles do not stick to the surface of each device and cause a reduction in quality. Further, since the modified layers are removed by etching, it is possible to prevent a reduction in die strength of each device due to the remainder of the modified layers.

Abstract: A method for manufacturing a semiconductor device includes forming a starting-point crack on a cleavage line on a surface of a semiconductor substrate; forming preliminary cracks intermittently along the cleavage line on the surface of the semiconductor substrate; and cleaving the semiconductor substrate along the cleavage line passing through the preliminary cracks, from the starting-point crack, wherein each of the preliminary cracks has a crack joining the cleavage line from outside of the cleavage line, in a direction of a progress of cleaving.

Abstract: Methods and apparatus for improved electromagnetic interference (EMI) shielding and thermal performance in integrated circuit (IC) packages are described. A die-up or die-down package includes a protective lid, a plurality of ground posts, an IC die, and a substrate. The substrate includes a plurality of ground planes. The IC die is mounted to the substrate. Plurality of ground posts is coupled to plurality of ground planes that surround IC die. Protective lid is coupled to plurality of ground posts. The plurality of ground posts and the protective lid from an enclosure structure that substantially encloses the IC die, and shields EMI from and radiating towards the IC die. The enclosure structure also dissipates heat generated by the IC die during operation.

Abstract: In various embodiments, a method for processing a wafer may include: providing a wafer having at least one die region and at least one metallization disposed over the at least one die region; covering the at least one metallization with a protecting layer; plasma etching the wafer to form at least one die.

Abstract: A method for processing a wafer in accordance with various embodiments may include: forming a passivation over the wafer; forming a protection layer over at least a surface of the passivation facing away from the wafer, wherein the protection layer includes a material that is selectively etchable to a material of the passivation; forming a mask layer over at least a surface of the protection layer facing away from the wafer, wherein the mask layer includes a material that is selectively etchable to the material of the protection layer; etching the wafer using the mask layer as a mask; selectively etching the material of the mask layer to remove the mask layer from the protection layer, after etching the wafer; and selectively etching the material of the protection layer to remove the protection layer from the passivation, after selectively etching the material of the mask layer.

Abstract: A package-on-package (“PoP”) structure and a method of forming are provided. The PoP structure may be formed by forming a first set of electrical connections on a first substrate. A first material may be applied to the first set of electrical connections. A second substrate may be provided having a second set of electrical connections formed thereon. The first set of electrical connections of the first substrate having the epoxy flux applied may be contacted to the second electrical connections of the second substrate. A reflow process may be performed to electrically connect the first substrate to the second substrate. The epoxy flux applied to the first electrical connections of the first substrate may prohibit electrical bridges or shorts from forming during the reflow process.

Abstract: An integrated circuit apparatus is provided with package-level connectivity, between internal electronic circuitry thereof and contact points on a package substrate thereof, without requiring top metal pads or bonding wires.

Abstract: A method to construct configurable systems, the method including: providing a first configurable system including a first die and a second die, where the connections between the first die and the second die include through-silicon-via (“TSV”), where the first die is diced from a first wafer using first dice lines; providing a second configurable system including a third die and a fourth die, where the connections between the third die and the fourth die include through-silicon-via (“TSV”), where the third die is diced from a third wafer using third dice lines; and processing the first wafer and the third wafer utilizing at least 20 masks that are the same; where the first dice lines are substantially different than the third dice lines, and where the second die includes a configurable I/O to connect the first configurable system to external devices.

Abstract: Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.

Abstract: Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.

Abstract: In one embodiment of the present invention, a method of forming a semiconductor device includes forming a device region in a first region of a semiconductor substrate, and forming an opening in a second region of the semiconductor substrate. The method further includes placing a semiconductor die within the opening, and forming a first metallization level over the semiconductor die and the device region.

Abstract: A method (90) entails placing (124) sensor elements (122) in an array (126) arranged to correspond with locations of controller dies (24) in a controller wafer (94) and encapsulating (128) the array (126) in a mold material (74) to form a panel (130) of the sensor elements (122). The sensor elements (122) include bond pads (42) that are concealed by a material section (116, 118) of the sensor elements (122). The controller wafer (94) is bonded (134) to the panel (130) to form a stacked wafer structure (136). After bonding, methodology (90) entails forming (140) conductive elements (60) on the controller wafer (95), removing material sections (100) from the controller wafer (94) and removing the material sections (116, 118) from the sensor elements (122) to expose the bond pads (42), forming (148) electrical interconnects (56), applying (152) packaging material (64), and singulating to produce sensor packages (20, 76).

Abstract: A method for fusing a laser fuse in accordance with various embodiments may include: providing a semiconductor workpiece having a substrate region and at least one laser fuse; fusing the at least one laser fuse from a back side of the substrate region by means of an infrared laser beam.

Abstract: A method of manufacturing a component is disclosed. An embodiment of the method comprises dicing a carrier in a plurality of components, the carrier being disposed on a support carrier, after dicing, placing a connection layer on the carrier and removing the components from the support carrier.

Abstract: [Problems] There are provided a chip separation method and a chip transfer method using features of dry etching. [Means for Solving the Problems] In the chip separation method, a multiple number of semiconductor devices or semiconductor integrated circuits are separated from a wafer 100 on which the multiple number of semiconductor devices or semiconductor integrated circuits are formed. The method includes forming, on a surface of the wafer 100, a mask layer through which a line-shaped pattern to be removed for separating the semiconductor devices or semiconductor integrated circuits is exposed; and etching the exposed pattern to a depth equal to or larger than about ? of a thickness of the wafer. One group of separated semiconductor devices or semiconductor integrated circuits has a distinguishable shape from another group of separated semiconductor devices or semiconductor integrated circuits.

Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and fluid machining the semiconductor wafer to remove the backmetal layer from the singulation lines.

Abstract: One illustrative method disclosed herein includes forming a plurality of die above a crystalline semiconducting substrate, irradiating and cooling an edge region of the substrate to form an amorphous region in the edge region of the substrate and, after forming the amorphous region, performing at least one process operation to reduce the thickness of the substrate.

Abstract: The present invention relates to a thermally releasable sheet-integrated film for semiconductor back surface, which includes: a pressure-sensitive adhesive sheet including a base material layer and a pressure-sensitive adhesive layer, and a film for semiconductor back surface formed on the pressure-sensitive adhesive layer of the pressure-sensitive adhesive sheet, in which the pressure-sensitive adhesive sheet is a thermally releasable pressure-sensitive adhesive sheet whose peel force from the film for semiconductor back surface decreases upon heating.

Abstract: A cavity is etched from a front surface into a semiconductor substrate. After providing an etch stop structure at the bottom of the cavity, the cavity is closed. From a back surface opposite to the front surface the semiconductor substrate is grinded at least up to an edge of the etch stop structure oriented to the back surface. Providing the etch stop structure at the bottom of an etched cavity allows for precisely adjusting a thickness of a semiconductor body of a semiconductor device.

Abstract: A semiconductor device includes an electrically conducting carrier and a semiconductor chip disposed over the carrier. The semiconductor device also includes a porous diffusion solder layer provided between the carrier and the semiconductor chip.