Abstract: A chip embedded package is provided, the chip embedded package including: a plurality of dies; wherein a first die of the plurality of dies is a chip implementing a first sensor technology, and wherein a second die of the plurality of dies is a chip implementing a second sensor technology; and wherein the plurality of dies are molded with an encapsulation material; wherein at least one of the first die and the second die includes a film interconnect.

Abstract: A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second semiconductor die onto the first semiconductor die to form a plurality of singulated stacked die devices on the wafer. A support tape is attached to a bottomside of the second semiconductor die. A dicing tape is attached to the wafer. The wafer is laser irradiated before or after attachment of the dicing tape at intended dicing lanes that align with gaps between the first semiconductor die to mechanically weaken the wafer at the intended dicing lanes, but not cut through the wafer. The dicing tape is pulled to cleave the wafer into a plurality of singulated portions to form a plurality of singulated stacked die devices attached to the singulated wafer portions by the dicing tape. The support tape is removed prior to cleaving.

Abstract: A method and system is provided by which multiple semiconductor die stacks can be assembled in a batch manner, and which also provides for die alignment tolerances required by microelectromechanical systems and other system-in-package applications. The batch process and accuracy is provided, in part, by an intermediate die attach carrier that has multiple die pockets fabricated to hold a set of die with an alignment required for the application. Die are placed in each pocket using a die sorting process. Then a batch process operation is performed in which wafer or strip-level alignment and bonding tools are used to join the die in the intermediate die attach carrier in stacks with a second set of die.

Abstract: A composite wafer includes a molded wafer and a second wafer. The molded wafer includes a plurality of first components, and the second wafer includes a plurality of second components. The second wafer is combined with the molded wafer to form the composite wafer. At least one of the first components is aligned with at least one of the second components to form a multi-component element. The multi-component element is singulatable from the composite wafer.

Abstract: A photoelectrochemical (PEC) etch is performed for chip shaping of a device comprised of a III-V semiconductor material, in order to extract light emitted into guided modes trapped in the III-V semiconductor material. The chip shaping involves varying an angle of incident light during the PEC etch to control an angle of the resulting sidewalls of the III-V semiconductor material. The sidewalls may be sloped as well as vertical, in order to scatter the guided modes out of the III-V semiconductor material rather than reflecting the guided modes back into the III-V semiconductor material. In addition to shaping the chip in order to extract light emitted into guided modes, the chip may be shaped to act as a lens, to focus its output light, or to direct its output light in a particular way.

Abstract: A coating for a microelectronic device comprises a polymer film (131) containing a filler material (232). The polymer film has a thermal conductivity greater than 3 W/m·K and a thickness (133) that does not exceed 10 micrometers. The polymer film may be combined with a dicing tape (310) to form a treatment (300) that simplifies a manufacturing process for a microelectronic package (100) and may be used in order to manage a thermal profile of the microelectronic device.

Abstract: A method for fabricating a group-III nitride semiconductor laser device stably supplies laser cavity mirrors having a low lasing threshold current through the use of a semi-polar plane. A blade 5g is forced down through a first region ER1 to keep the first region ER1 squeezed between a support member H2 and a movable member H1 together with a part of a protective sheet TF in contact with the first region ER1 while the tension generated in the area of the protective sheet TF in contact with the first region ER1 with the movable member H1 increases until the semi-polar principal surface SF at an end face EG1 of the first region ER1 tilts by a deflection angle THETA from the semi-polar principal surface SF of a second region ER2, and a force is thereby generated in the first region ER1 in a direction opposite to the direction of travel of the blade 5g toward the first region ER1.

Abstract: In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.

Abstract: A method of forming a semiconductor device includes preparing a semiconductor substrate having a plurality of chips formed thereon and a scribe lane disposed between the chips, simultaneously forming a groove having a first depth in the scribe lane, and a through hole penetrating the chips and having a second depth. The chips are separated along the groove. The first depth is smaller than the second depth.

Abstract: A back of a dielectric transparent handle substrate is coated with a blanket conductive film or a mesh of conductive wires. A semiconductor substrate is attached to the transparent handle substrate employing an adhesive layer. The semiconductor substrate is thinned in the bonded structure to form a stack of the transparent handle substrate and the semiconductor interposer. The thinned bonded structure may be loaded into a processing chamber and electrostatically chucked employing the blanket conductive film or the mesh of conductive wires. The semiconductor interposer may be bonded to a semiconductor chip or a packaging substrate employing C4 bonding or intermetallic alloy bonding. Illumination of ultraviolet radiation to the adhesive layer is enabled, for example, by removal of the blanket conductive film or through the mesh so that the transparent handle substrate may be detached. The semiconductor interposer may then be bonded to a packaging substrate or a semiconductor chip.

Abstract: A method of producing a chip package includes providing a substrate comprising a first recess having a recess bottom and recess side walls. A chip comprising a chip backside is introduced into the recess such that the chip does not protrude from the recess and such that a gap remains between the recess side walls and the chip, the chip backside being attached to the recess bottom. The gap is filled with a filler material.

Abstract: The described embodiments of mechanisms of forming a package on package (PoP) structure involve bonding with connectors with non-solder metal balls to a packaging substrate. The non-solder metal balls may include a solder coating layer. The connectors with non-solder metal balls can maintain substantially the shape of the connectors and control the height of the bonding structures between upper and lower packages. The connectors with non-solder metal balls are also less likely to result in bridging between connectors or disconnection (or cold joint) of bonded connectors. As a result, the pitch of the connectors with non-solder metal balls can be kept small.

Abstract: The present disclosure is directed to an apparatus for the singulation of a semiconductor substrate or wafer. In some embodiments the singulation apparatus comprises a plurality of cutting devices. The cutting devices are configured to form multiple concurrent cutting lines in parallel on a surface of the semiconductor wafer. In some embodiments, the singulation apparatus comprises at least two dicing saws or laser modules. The disclosed singulation apparatus can dice the semiconductor wafer into individual chips by dicing in a direction across a complete circumferential edge of the wafer, thereby decreasing process time and increasing throughput.

Abstract: A micromechanical systems (MEMs) pressure sensor includes a semiconductor substrate having a deep well located within a first surface and a cavity located within a second, opposing surface. The semiconductor substrate has a first doping type. The deep well has a second doping type, with a gradient doping profile, thereby forming a PN junction within the substrate. The cavity forms a diaphragm, which is a substrate section that is thinner than the surrounding substrate sections, that comprises the deep well. One or more pizeoresistor elements are located within the deep well. The piezoresistors are sensitive to deformations, such as bending, in the diaphragm caused by changes in the pressure of the cavity.

Abstract: Methods of dicing substrates having a plurality of ICs. A method includes forming a multi-layered mask comprising a first mask material layer soluble in a solvent over the semiconductor substrate and a second mask material layer, insoluble in the solvent, over the first mask material layer. The multi-layered mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. The substrate is then plasma etched through the gaps in the patterned mask to singulate the IC with the second mask material layer protecting the first mask material layer for at least a portion of the plasma etch. The soluble material layer is dissolved subsequent to singulation to remove the multi-layered mask.

Abstract: One embodiment of a method of processing a semiconductor wafer having a peripheral portion includes providing external support structure and restraining radially inward displacement of the wafer peripheral portion with the external support structure.

Abstract: A wafer having a front face formed with a functional device is irradiated with laser light while positioning a light-converging point within the wafer with the rear face of the wafer acting as a laser light incident face, so as to generate multiphoton absorption, thereby forming a starting point region for cutting due to a molten processed region within the wafer along a line. Consequently, a fracture can be generated from the starting point region for cutting naturally or with a relatively small force, so as to reach the front face and rear face. Therefore, when an expansion film is attached to the rear face of the wafer by way of a die bonding resin layer after forming the starting point region for cutting and then expanded, the wafer and die bonding resin layer can be cut along the line.

Abstract: A method of dicing a semiconductor wafer comprises scribing at least one dielectric layer along dice lanes to remove material from a surface of the wafer using a laser with a pulse-width between 1 picosecond and 1000 picoseconds and with a repetition frequency corresponding to times between pulses shorter than a thermal relaxation time of the material to be scribed. The wafer is then diced through a metal layer and at least partially through a substrate of the semiconductor wafer.

Abstract: A semiconductor device in which defects in characteristics due to electrostatic discharge is reduced and a method for manufacturing the semiconductor device are provided. The semiconductor device has at least one of these structures: (1) a structure in which a first and second insulating films are in direct contact with each other in a peripheral region of a circuit portion, (2) a structure in which a first and second insulators are closely attached to each other, and (3) a structure in which a first conductive layer and a second conductive layer are provided on outer surfaces of the first insulator and the second insulator, respectively, and electrical conduction between the first and second conductive layers is achieved at a side surface of the peripheral region. Note that the conduction at the side surface can be achieved by cutting a plurality of semiconductor devices into separate semiconductor devices.

Abstract: Embodiments of mechanisms for flattening a packaged structure are provided. The mechanisms involve a flattening apparatus and the utilization of protection layer(s) between the packaged structure and the surface(s) of the flattening apparatus. The protection layer(s) is made of a soft and non-sticking material to allow protecting exposed fragile elements of the packaged structure and easy separation after processing. The embodiments of flattening process involve flattening the warped packaged structure by pressure under elevated processing temperature. Processing under elevated temperature allows the package structure to be flattened within a reasonable processing time.

Abstract: In one embodiment, a method of forming a semiconductor device includes stacking a second wafer with a first wafer and forming a through via extending through the second wafer while the second wafer is stacked with the first wafer. In another embodiment, a method of forming a semiconductor device includes singulating a first wafer into a first plurality of dies and attaching the first plurality of dies over a second wafer having a second plurality of dies. The method further includes forming a through via extending through a die of the first plurality of dies after attaching the first plurality of dies over the second wafer.

Abstract: A wafer sawing method comprises steps as follows: A wafer having a first surface and a second surface is firstly provided. An integrated circuit fabricating process is performed on the first surface of the wafer to define a first integrated circuit region and a periphery region surrounding around the first integrated circuit region, wherein the integrated circuit fabricating process includes an etching process used to form a first deep trench having an aspect ratio larger than 10 as well as a depth substantially ranging from one-third to two-third thickness of the wafer on the periphery region. Subsequently, an adhesive tape is disposed on the first surface at least covering the first integrated circuit region and the periphery region. A tensile stress is then imposed on the adhesive tape in order to make the wafer broken off along the first deep trench.

Abstract: In a method for fabricating a semiconductor device, a carrier and at least one semiconductor chip are provided.

Abstract: Disclosed is a method of fabricating a thin film solar cell. A separation process (‘P4’ process) of insulating a thin film solar cell from the outside is integrally performed with a transparent electrode patterning process (‘P1’ process) and a metallic electrode patterning process (‘P3’ process). This may reduce the fabrication costs and enhance spatial efficiency as the ‘P4’ process and equipment for the ‘P4’ process are not required.

Abstract: A semiconductor device has a semiconductor wafer with a plurality of semiconductor die separated by a non-active region. The semiconductor die can be circular or polygonal with three or more sides. A plurality of bumps is formed over the semiconductor die. A portion of semiconductor wafer is removed to thin the semiconductor wafer. A wafer ring is mounted to mounting tape. The semiconductor wafer is mounted to the mounting tape within the wafer ring. The mounting tape includes translucent or transparent material. A penetrable layer is applied over the bumps formed over the semiconductor wafer. An irradiated energy from a laser is applied through the mounting tape to the non-active region to form a modified region within the non-active region. The semiconductor wafer is singulated along the modified region to separate the semiconductor die.

Abstract: A wafer has a device area where a plurality of devices are formed, and a peripheral marginal area surrounding the device area. These devices are formed on the front side of the wafer so as to be partitioned by a plurality of division lines. A modified layer is formed by applying a laser beam along the division lines with the focal point of the laser beam set inside the wafer, thereby forming a modified layer as a division start point inside the wafer along each division line. The wafer is transported to a position where the next step is to be performed. In the modified layer forming step, the modified layer is not formed in the peripheral marginal area of the wafer to thereby form a reinforcing portion in the peripheral marginal area. Accordingly, breakage of the wafer from the modified layer in the transporting step can be prevented.

Abstract: A light-emitting device manufacturing method comprises the steps of irradiating a substrate 2 having a III-V compound semiconductor layer 17 formed on a front face 2a with laser light L1 along lines to cut 5a, 5b, while locating a converging point P1 within the sapphire substrate 2 and using a rear face 2b thereof as a laser light entrance surface, and thereby forming modified regions 7a, 7b along the lines 5a, 5b within the substrate 2; then forming a light-reflecting layer on the rear face 2b of the substrate 2; and thereafter extending fractures generated from the modified regions 7a, 7b acting as a start point in the thickness direction of the substrate 2, and thereby cutting the substrate 2, the semiconductor layer 17 and the light-reflecting layer along the lines 5a, 5b, and manufacturing a light-emitting device.

Abstract: A first product may be provided that comprises a substrate having a first surface, a first side, and a first edge where the first surface meets the first side; and a device disposed over the substrate, the device having a second side, where at least a first portion of the second side is disposed within 3 mm from the first edge of the substrate. The first product may further comprise a first barrier film that covers at least a portion of the first edge of the substrate, at least a portion of the first side of the substrate, and at least the first portion of the second side of the device.

Abstract: A method for cutting a semiconductor wafer into semiconductor chips that reduces defects at the semiconductor chip corners. The method includes a pre-cutting processing step of trimming the semiconductor chip corners so that mechanical stress is reduced at the corners. The method includes dicing channels on a semiconductor wafer thereby defining the geometrical shape of one of the semiconductor chips, modifying the corners of the one of the semiconductor chips, and cutting the semiconductor wafer to separate the one of the semiconductor chips from other semiconductor chips.

Abstract: In one embodiment a method for manufacturing a semiconductor device comprises arranging a wafer on a carrier, the wafer comprising singulated chips; bonding the singulated chips to a support wafer, and removing the carrier.

Abstract: A method of manufacturing semiconductor wafers, the method including: providing a donor wafer including a semiconductor substrate; performing a lithography step and processing the donor wafer; and performing at least two subsequent steps of layer transfer out of the donor wafer, each layer transfer step producing a transferred layer, where each of the transferred layers had been affected by the lithography step, and where each of the transferred layer includes a plurality of transistors with side gates, and where the layer transfer includes an ion-cut, the ion-cut including an ion implant thru the transistors.

Abstract: A cavity is formed in a working surface of a substrate in which a semiconductor element is formed. A glass piece formed from a glass material is bonded to the substrate, and the cavity is filled with the glass material. For example, a pre-patterned glass piece is used which includes a protrusion fitting into the cavity. Cavities with widths of more than 10 micrometers are filled fast and reliably. The cavities may have inclined sidewalls.

Abstract: Etched trenches in a bond material for die singulation, and associated systems and methods are disclosed. A method for solid state transducer device singulation in accordance with one embodiment includes forming a plurality of trenches by etching through a metallic bond material forming a bond between a carrier substrate and a plurality of the dies and singulating the carrier substrate along the trenches to separate the dies. In particular embodiments, the trenches extend into the carrier substrate. In further particular embodiments, the dies are at least partially encapsulated in a dielectric material.

Abstract: A source material, which is based on a glass, is arranged on a working surface of a mold substrate. The mold substrate is made of a single-crystalline material. A cavity is formed in the working surface. The source material is pressed against the mold substrate. During pressing a temperature of the source material and a force exerted on the source material are controlled to fluidify source material. The fluidified source material flows into the cavity. Re-solidified source material forms a glass piece with a protrusion extending into the cavity. After re-solidifying, the glass piece may be bonded to the mold substrate. On the glass piece, protrusions and cavities can be formed with slope angles less than 80 degrees, with different slope angles, with different depths and widths of 10 micrometers and more.

Abstract: In one embodiment, a method of fabricating a semiconductor package includes forming a first plurality of die openings on a laminate substrate. The laminate substrate has a front side and an opposite back side. A plurality of first dies is placed within the first plurality of die openings. An integrated spacer is formed around each die of the plurality of first dies. The integrated spacer is disposed in gaps between the laminate substrate and an outer sidewall of each die of the plurality of first dies. The integrated spacer holds the die within the laminate substrate by partially extending over a portion of a top surface of each die of the plurality of first dies. Front side contacts are formed over the front side of the laminate substrate.

Abstract: An article of manufacture includes a semiconductor die (110) having an integrated circuit (105) on a first side of the die (110), a diffusion barrier (125) on a second side of the die (110) opposite the first side, a mat of carbon nanotubes (112) rooted to the diffusion barrier (125), a die attach adhesive (115) forming an integral mass with the mat (112) of the carbon nanotubes, and a die pad (120) adhering to the die attach adhesive and (115) and the mat (112) of carbon nanotubes for at least some thermal transfer between the die (110) and the die pad (120) via the carbon nanotubes (112). Other articles, integrated circuit devices, structures, and processes of manufacture, and assembly processes are also disclosed.

Abstract: A method for manufacturing a chip is disclosed. The method comprises forming a material structure in a kerf adjacent the chip on a wafer. The method further comprises selectively removing the material structure in the kerf and dicing the wafer. A semiconductor wafer is disclosed. The semiconductor wafer comprises a plurality of chips and a plurality of kerfs. The kerfs separate the chips from each other. At least one kerf comprises a kerf framing. The kerf framing is arranged directly adjacent a side of the at least on chip.

Abstract: A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs.

Abstract: A processing method for a bump-included device wafer which includes an adhesive providing step of providing an adhesive in an annular groove of a carrier wafer so that the adhesive projects from the upper surface of an annular projection of the carrier wafer; a wafer attaching step of attaching and fixing the front side of the device wafer through the adhesive to the front side of the carrier wafer so as to accommodate bumps in a recess of the carrier wafer after performing the adhesive providing step; and a thickness reducing step of grinding or polishing the back side of the device wafer to reduce the thickness of the device wafer to a predetermined thickness after performing the wafer attaching step.

Abstract: A method for producing a group III nitride crystal in the present invention includes the steps of cutting a plurality of group III nitride crystal substrates 10p and 10q having a main plane from a group III nitride bulk crystal 1, the main planes 10pm and 10qm having a plane orientation with an off-angle of five degrees or less with respect to a crystal-geometrically equivalent plane orientation selected from the group consisting of {20-21}, {20-2-1}, {22-41}, and {22-4-1}, transversely arranging the substrates 10p and 10q adjacent to each other such that the main planes 10pm and 10qm of the substrates 10p and 10q are parallel to each other and each [0001] direction of the substrates 10p and 10q coincides with each other, and growing a group III nitride crystal 20 on the main planes 10pm and 10qm of the substrates 10p and 10q.

Abstract: The invention provides an adhesive sheet which can be stuck to a wafer at low temperatures of 100° C. or below, which is soft to the extent that it can be handled at room temperature, and which can be cut simultaneously with a wafer under usual cutting conditions; a dicing tape integrated type adhesive sheet formed by lamination of the adhesive sheet and a dicing tape; and a method of producing a semiconductor device using them. In order to achieve this object, the invention is characterized by specifying the breaking strength, breaking elongation, and elastic modulus of the adhesive sheet in particular numerical ranges.

Abstract: Disclosed is a method for dicing a semiconductor wafer. The method for dicing a semiconductor wafer prevents a die from being contaminated with silicon dust, generated during the dicing of the wafer, and thus prevents defects in a subsequent wire bonding step, such as defects in bonding wire, contamination of a semiconductor device, etc. The method for dicing a semiconductor wafer comprises the steps of: applying a fluorine-containing polymer coating agent onto one surface of a wafer having a circuit pattern formed thereon to form a polymer coating layer, before dicing the wafer.

Abstract: Heat spreading substrate. In an embodiment in accordance with the present invention, an apparatus includes a first conductive layer, a first insulating layer disposed in contact with the first conductive layer and a thermally conductive layer disposed in contact with the first insulating layer, opposite the first conductive layer. The faces of the first conductive layer, the first insulating layer and the thermally conductive layer are substantially co-planar; and a sum of widths of faces of the first conductive layer, the first insulating layer and the thermally conductive layer is greater than a height of the faces. The first conductive layer and the first insulating layer may include rolled materials.

Abstract: A device includes a package component, and a die over and bonded to the package component. The die includes a substrate. A heat sink is disposed over and bonded to a back surface of the substrate through direct bonding.

Abstract: Embodiments disclose a method including forming at least one compound semiconductor layer on a top r-face of a substrate, forming a line for cleavage on a bottom r-face of the substrate along a length of a guide line, wherein the guide line extends in a (11-20)-plane direction of the substrate, wherein the guide line extends from one portion of an edge to another portion of the edge, and wherein the edge is disposed between the top r-face and the bottom r-face of the substrate, and applying a force to the bottom r-face of the substrate to cleave the substrate along the line for cleavage in the (11-20)-plane direction and to form a cleaved facet along a m-plane of the at least one compound semiconductor.

Abstract: Embodiments disclose a method including forming at least one compound semiconductor layer on a top r-face of a substrate, forming a line for cleavage on a bottom r-face of the substrate along a length of a guide line, wherein the guide line extends in a (11-22)-plane direction of the substrate, wherein the guide line extends from one portion of an edge to another portion of the edge, and wherein the edge is disposed between the top r-face and the bottom r-face of the substrate, and applying a force to the bottom r-face of the substrate to cleave the substrate along the line for cleavage in the (11-22)-plane direction and to form a cleaved facet along a c-plane of the at least one compound semiconductor.

Abstract: A method of processing wafers for saving material and protecting environment is implemented to collect defective or incomplete wafers and perform cutting operation to create a plurality of separate dies. According to the requirement of a specification, the backs of the dies are grinded to allow each die to have a predetermined thickness. Thereafter, the grinded dies with completeness are sequentially placed onto a carrying means. With the method, the defective or incomplete wafers, which would be discarded in general wafer manufacturing, may be reclaimed to go through cutting, grinding, and selecting operations, so that the dies with completeness on the defective wafers can be picked out and processed again, so as to increase the yield, lower the manufacturing cost, reduce the amount of the wafer waste, increase the wafer utilization, and meet the demands of energy saving, carbon reduction, and environmental protection.

Abstract: A recess is formed into a first side of a wafer such that a thinned center portion of the wafer is formed, and such that the central portion is surrounded by a thicker peripheral edge support portion. The second side of the wafer remains substantially entirely planar. After formation of the thinned wafer, vertical power devices are formed into the first side of the central portion of the wafer. Formation of the devices involves forming a plurality of diffusion regions into the first side of the thinned central portion. Metal electrodes are formed on the first and second sides, the peripheral portion is cut from the wafer, and the thin central portion is diced to form separate power devices. In one example, a first commercial entity manufactures the thinned wafers, and a second commercial entity obtains the thinned wafers and performs subsequent processing to form the vertical power devices.

Abstract: A method includes laminating a Non-Conductive Film (NCF) over a first package component, and bonding a second package component on the first package component. The NCF and the second package component are on a same side of the first package component. Pillars of a mold tool are then forced into the NCF to form openings in the NCF. The connectors of the first package component are exposed through the openings.

Abstract: In a semiconductor package, a stamp is provided on at least one of at least a pair of opposed sides on an outer peripheral portion in contact with an edge of the package, which is a blank space up to now. With this configuration, the amount of stamp can be increased even in a narrow stamp area.