Abstract: A method of forming a device stack is presented. The method includes providing a temporary substrate having a temporary mounting surface. A first chip is temporarily mounted to the temporary mounting surface. A first bottom surface of the first chip is temporarily mounted to the temporary mounting surface and a first top surface of the first chip comprises first interconnects. A second chip is stacked on the first chip. The second chip includes second conductive contacts on the second bottom surface. The method also includes bonding the first and second chips together to form the device stack. The second conductive contacts are coupled to the first interconnects. The first bottom surface of the first chip is separated from the substrate to separate the chip stack from the substrate.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first substrate, a second substrate, an interposer substrate, a semiconductor chip, a package body and a first antenna layer. The first substrate comprises a grounding segment. The interposer substrate is disposed between the second substrate and the first substrate. The semiconductor chip is disposed on the second substrate. The package body encapsulates the second substrate, the semiconductor chip and the interposer substrate, and has a lateral surface and an upper surface. The first antenna layer is formed on the lateral surface and the upper surface of the package body, and electrically connected to the grounding segment.

Abstract: A method and apparatus is described for forming and using a stiffener for the production of thinned integrated circuits. In one embodiment, a handle can be bonded to an integrated circuit wafer before the wafer is thinned. Electrical couplings such as mounting balls can be attached to the wafer. Individual dice can be singulated from the wafer by dicing through the wafer and the handle, producing a wafer/handle assembly. The wafer/handle assembly can be mounted to a printed circuit board before the handle is de-bonded.

Abstract: A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings permits a single circuit design and fabrication run to be used to support flexibly packaging different product releases having different numbers of integrated circuit blocks per packaged unit.

Abstract: A packaged integrated device can include a die attach pad having a top surface and a bottom surface. A plurality of leads physically and electrically separated from the die attach pad can be positioned at least partially around the perimeter of the die attach pad. An integrated device die can be mounted on the top surface of the die attach pad. A package body can cover the integrated device die and at least part of the plurality of leads, and at least a portion of the bottom surface of each of the plurality of leads can be exposed through the package body. A plating layer can cover substantially the entire width of an etched lower portion of the outer end of each lead and at least the exposed portion of the bottom surface of each lead.

Abstract: A method of forming a packaged semiconductor device includes loading an array of package sites in position for saw singulation, saw singulating the array of package sites, and performing a non-electrolytic plating operation on exposed lead tips of individual packages from the array of package sites as the array of package sites is saw singulated.

Abstract: A method of manufacturing a semiconductor device includes preparing a semiconductor wafer including a silicon substrate and a laminate having a compound semiconductor layer; etching and removing a part of the laminate in a thickness direction to form trench regions in a grid, each trench region including a plurality of stripe grooves extending in parallel to each other; filling the groove with a material having a lower hardness than the compound semiconductor layer to form a buried region; and dividing the semiconductor wafer into a plurality of chips by dicing using a blade at a dicing line which is defined within the trench region and includes a plurality of the buried regions.

Abstract: The invention relates in a general aspect to a method of making vertically protruding elements on a substrate, said elements having a tip comprising at least one inclined surface and an elongated body portion extending between said substrate and said tip. The method comprises an anisotropic, crystal plane dependent etch forming said inclined surface(s); and an anisotropic, non crystal plane dependent etch forming said elongated body portion; combined with suitable patterning processes defining said protruding elements to have a predetermined base geometry.

Abstract: A semiconductor device includes a carrier, a chip attached to the carrier, and an encapsulation body disposed over the chip and the carrier. An exterior surface of the semiconductor device includes an exposed peripheral edge of at least two of the carrier, the chip, and the encapsulation body.

Abstract: A chip package includes a substrate having a pad region, a device region, and a remained scribe region located at a periphery of the substrate; a signal and an EMI ground pads disposed on the pad region; a first and a second openings penetrating into the substrate to expose the signal and the EMI ground pads, respectively; a first and a second conducting layers located in the first and the second openings and electrically connecting the signal and the EMI ground pads, respectively, wherein the first conducting layer and the signal pad are separated from a periphery of the remained scribe region, and wherein a portion of the second conducting layer and/or the EMI ground pad extend(s) to a periphery of the remained scribe region; and a third conducting layer surrounding the periphery of the remained scribe region to electrically connect the second conducting layer and/or the EMI ground pad.

Abstract: An array of semiconductor components, comprising a first plurality of semiconductor components and a second plurality of semiconductor components held on a carrier, is bonded onto one or more substrates. The first plurality of semiconductor components is first located for pick-up by a transfer device, and each semiconductor component comprised in the first plurality of semiconductor components is picked up with the transfer device and is bonded onto a respective bonding position on the one or more substrates. After the first plurality of semiconductor components have been picked up and bonded, the carrier is rotated and the second plurality of semiconductor components is located for pick-up by the transfer device. Thereafter, each semiconductor component comprised in the second plurality of semiconductor components is picked up with the transfer device and is bonded onto a respective bonding position on the one or more substrates.

Abstract: Methods of processing a device substrate are disclosed herein. In one embodiment, a method of processing a device substrate can include bonding a first surface of a device substrate to a carrier with a polymeric material. The device substrate may have a plurality of first openings extending from the first surface towards a second surface of the device substrate opposite from the first surface. Then, material can be removed at the second surface of the device substrate, wherein at least some of the first openings communicate with the second surface at least one of before or after performing the removal of the material. Then, at least a portion of the polymeric material disposed between the first surface and the carrier substrate can be exposed to a substance through at least some first openings to debond the device substrate from the carrier substrate.

Abstract: A method (70) of forming sensor packages (20) entails providing a sensor wafer (74) having sensors (30) formed on a side (26) positioned within areas (34) delineated by bonding perimeters (36), and providing a controller wafer (82) having control circuitry (42) at one side (38) and bonding perimeters (46) on an opposing side (40). The bonding perimeters (46) of the controller wafer (82) are bonded to corresponding bonding perimeters (36) of the sensor wafer (74) to form a stacked wafer structure (48) in which the control circuitry (42) faces outwardly. The controller wafer (82) is sawn to reveal bond pads (32) on the sensor wafer (74) which are wire bonded to corresponding bond pads (44) formed on the same side (38) of the wafer (82) as the control circuitry (42). The structure (48) is encapsulated in packaging material (62) and is singulated to produce the sensor packages (20).

Abstract: A method includes performing a dicing on a composite wafer including a plurality of dies, wherein the composite wafer is bonded on a carrier when the step of dicing is performed. After the step of dicing, the composite wafer is mounted onto a tape. The carrier is then de-bonded from the composite wafer and the first tape.

Abstract: A semiconductor wafer with an assisting dicing structure. The wafer comprises a substrate having a front surface and a rear surface. The front surface of the substrate comprises at least two device regions separated by at least one dicing lane. The rear surface of the substrate comprises at least one pre-dicing trench formed therein and substantially aligned with the dicing lane. A method for dicing a semiconductor wafer is also disclosed.

Abstract: A system and method for manufacturing a packaged component are disclosed. An embodiment comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions. The method further comprises generating the component by separating the carrier.

Abstract: A laser processing method is disclosed, comprising the steps of: directing a laser beam to a workpiece; and effecting a relative motion between the laser beam and the workpiece. In particular, the step of directing the laser beam to the workpiece comprises focusing the laser beam within the workpiece until an internal damage forms within the workpiece and a crack propagates from the internal damage to at least one surface of the workpiece to form a surface crack on the workpiece. Further, the step of effecting the relative motion between the laser beam and the workpiece is such that the surface crack on the workpiece propagates along a line of separation on the workpiece. A laser processing apparatus is also disclosed.

Abstract: A package structure which includes a non-conductive substrate, a conductive element, a passivation, a jointed side, a conductive layer, a solder and a solder mask is disclosed. The conductive element is disposed on a surface of the non-conductive substrate and consists of a passive element and a corresponding circuit. The passivation completely covers the conductive element and the non-conductive substrate so that the conductive element is sandwiched between the passivation and the non-conductive substrate. The conductive layer covers the jointed side which exposes part of the corresponding circuit, extends beyond the jointed side and is electrically connected to the corresponding circuit. The solder mask which completely covers the jointed side and the conductive layer selectively exposes the solder which is disposed outside the jointed side and electrically connected to the conductive layer.

Abstract: A method of assembling semiconductor devices includes providing a structure that includes an array of conductive frame members beside an array of apertures and an array of conductive vias that are exposed at a first face and extend towards a second face. An array of semiconductor dies is positioned in the array of apertures with their active faces positioned in the first face of the structure. The assembly is encapsulated from the second face of the structure and a redistribution layer is formed on the first face of the structure and the active faces of the die. Material is removed from the back face of the encapsulated array to expose the vias at the back face for connection through a further redistribution layer formed on the back face to electronic components stacked vertically on the further redistribution layer.

Abstract: A semiconductor device has external, exposed electrical contacts at an device active face and a semiconductor die, which has internal, electrical contacts at a die active face. The exposed contacts are offset from the internal contacts laterally of the device active face. A redistribution layer includes a layer of insulating material and redistribution interconnectors within the insulating material, the interconnectors connecting with the exposed contacts. A set of conductors connect the internal contacts and the interconnectors. The conductors have oblong, tear drop shaped cross-sections extending laterally of the die active face beyond the respective internal contacts, and contact the interconnectors at positions spaced further apart than the internal contacts. The redistribution layer may be prefabricated using less costly manufacturing techniques such as lamination.

Abstract: A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.

Abstract: A chip package includes a first die with an active surface having at least one die pad positioned thereon; a first adhesive layer having a first surface coupled to the active surface of the first die and a second surface opposite the first surface; and a first dielectric layer having a top surface. A first portion of the top surface of the first dielectric layer is coupled to the second surface of the first adhesive layer. A second portion of the top surface of the first dielectric layer, distinct from the first portion, is substantially free of adhesive.

Abstract: A method for manufacturing a chip package is provided. The method includes forming a layer over a carrier; forming further carrier material over the layer; selectively removing one or more portions of the further carrier material thereby releasing one or more portions of the layer from the further carrier material; and adhering a chip including one or more contact pads to the carrier via the layer.

Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer by forming trenches along singulation lines and initiating a cracks from within the trenches, which propagate through the semiconductor wafer in a more controlled manner.

Abstract: A dicing die bonding film including a bonding layer; and a pressure-sensitive adhesive layer adjoining the bonding layer, the pressure-sensitive adhesive layer having a storage modulus of about 400 to about 600 kPa at 25° C. and a peel strength of about 200 to about 350 mN/25 mm with respect to the bonding layer as measured according to KS-A-01107 standard.

Abstract: An improved method for singulation of compound electronic devices is presented. Compound electronic devices are manufactured by combining two or more substrates into an assembly containing multiple devices. Presented are methods for singulation of compound electronic devices using laser processing. The methods presented provide fewer defects such as cracking or chipping of the substrates while minimizing the width of the kerf and maintaining system throughput.

Abstract: The various aspects comprise methods and devices for processing a wafer. An aspect of this disclosure includes a wafer. The wafer comprises a plurality of die regions; a plurality of kerf regions between the plurality of die regions; and a metallization area on the plurality of die regions.

Abstract: A wafer level package including a shield connected to a plurality of conductive elements disposed on a silicon wafer. The conductive elements are arranged to individually enclose micro-structure elements located on the silicon wafer within cavities formed by the conductive elements for better shielding performance. The shield and the conductive elements function as the EMI shield.

Abstract: Solder is simultaneously transferred from a mold to a plurality of 3D assembled modules to provide solder bumps on the modules. The mold includes cavities containing injected molten solder or preformed solder balls. A fixture including resilient pressure pads and vacuum lines extending through the pads applies pressure to the modules when they are positioned on the mold. Following reflow and solder transfer to the modules, the fixture is displaced with respect to the mold. The modules, being attached to the fixture by vacuum pressure through the pads, are displaced from the mold with the fixture.

Abstract: Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p+-type isolation layer for obtaining reverse blocking capability is provided at the end of an element. In addition, a concave portion is provided so as to extend from the backside surface of the n-type drift region to the p+-type isolation layer. A p-type region is provided and is electrically connected to the p+-type isolation layer. The p+-type isolation layer is provided so as to include a cleavage plane having the boundary between the bottom and the side wall of the concave portion as one side.

Abstract: The present invention provides a semiconductor structure having a lateral TSV and a manufacturing method thereof. The semiconductor structure includes a chip having an active side, a back side disposed opposite to the active side, and a lateral side disposed between the active side and the back side. The chip further includes a contact pad, a lateral TSV and a patterned conductive layer. The contact pad is disposed on the active side. The lateral TSV is disposed on the lateral side. The patterned conductive layer is disposed on the active side and is electrically connected to the lateral TSV and the contact pad.

Abstract: An object to be processed is reliably cut along a line to cut. An object to be processed is irradiated with laser light while locating a converging point at the object, so as to form a modified region in the object along a line to cut. The object formed with the modified region is subjected to an etching process utilizing an etching liquid exhibiting a higher etching rate for the modified region than for an unmodified region, so as to etch the modified region. This can etch the object selectively and rapidly along the line to cut by utilizing a higher etching rate in the modified region.

Abstract: Aspects and examples include electrical components and methods of forming electrical components. In one example, a method includes selecting a substrate, forming a pattern of a first conductive material on a top surface of the substrate, forming a pattern of a second conductive material on a bottom surface of the substrate, dicing the substrate into one or more die having a first diced surface and a second diced surface, securing the first diced surface of each of the one or more die to a retaining material, encapsulating the one or more die in an encapsulent to form a reconstituted wafer, and forming a pattern of a third conductive material on the second diced surface by metalizing a surface of the reconstituted wafer.

Abstract: A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body.

Abstract: A method for fabricating a semiconductor device, wherein the method comprises steps as follows: Firstly, a device wafer is provided and a patterned bonding layer is then formed within a scribe line region of the device wafer. Subsequently a handle wafer is bonded to the device wafer by the patterned bonding layer. Next, a dicing process is performed along the scribe line region in order to divide the device wafer into a plurality of dices and remove the patterned bonding layer simultaneously, whereby the divided dices can be separated from the handle wafer.

Abstract: A semiconductor device has a semiconductor wafer with an interconnect structure formed over a first surface of the wafer. A trench is formed in a non-active area of the semiconductor wafer from the first surface partially through the semiconductor wafer. A protective coating is formed over the first surface and into the trench. A lamination tape is applied over the protective coating. A portion of a second surface of the semiconductor wafer is removed by backgrinding or wafer thinning to expose the protecting coating in the trench. A die attach film is applied over the second surface of the semiconductor wafer. A cut or modified region is formed in the die attach film under the trench using a laser. The semiconductor wafer is expanded to separate the cut or modified region of the die attach film and singulate the semiconductor wafer.

Abstract: A semiconductor device is manufactured by forming at least one epitaxial structure over a substrate. A portion of the substrate is cut and lifted to expose a partial surface of the epitaxial structure. A first electrode is then formed on the exposed partial surface to result in a vertical semiconductor device.

Abstract: A chip package is described which includes a first chip having a first surface and first sides having a first side-wall angle, and a second chip having a second surface and second sides having a second side-wall angle, which faces and is mechanically coupled to the first chip. The chip package is fabricated using a batch process, and the chips in the chip package were singulated from their respective wafers after the chip package is assembled. This is accomplished by etching the first and second side-wall angles and thinning the wafer thicknesses prior to assembling the chip package. For example, the first and/or the second side walls can be fabricated using wet etching or dry etching. Therefore, the first and/or the second side-wall angles may be other than vertical or approximately vertical.

Abstract: Method for bonding a plurality of chips onto a base wafer.

Abstract: A method of manufacturing a light emitting device: an LED wafer having an array of LEDs formed on a surface thereof, the method comprises: a) fabricating a sheet of phosphor/polymer material comprising a light transmissive polymer material having at least one phosphor material distributed throughout its volume and in which the polymer material is transmissive to light generated by the LEDs and to light generated by the at least one phosphor material; b) selectively making apertures through the phosphor/polymer sheet at positions corresponding to electrode contact pads of the LEDs of the LED wafer; c) attaching the sheet of phosphor/polymer material to the surface of the LED wafer such that each aperture overlies a respective electrode contact pad; and d) dividing the wafer into individual light emitting devices. The method can further comprise, prior to dividing the LED wafer, cutting slots through the phosphor/polymer material that are configured to pass between individual LEDs.

Abstract: A method for manufacturing a chip package is provided. The method including: holding a carrier including a plurality of dies; forming a separation between the plurality of dies by removing from the carrier one or more portions of the carrier between the plurality of dies; forming an encapsulation material in the removed one or more portions between the plurality of dies; separating the dies through the encapsulation material.

Abstract: A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are uncovered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer.

Abstract: Aspects and examples include electrical components and methods of forming electrical components. In one example, a method includes selecting a substrate, forming a pattern of a first conductive material on a top surface of the substrate, forming a pattern of a second conductive material on a bottom surface of the substrate, dicing the substrate into one or more die having a first diced surface and a second diced surface, securing the first diced surface of each of the one or more die to a retaining material, encapsulating the one or more die in an encapsulent to form a reconstituted wafer, and forming a pattern of a third conductive material on the second diced surface by metalizing a surface of the reconstituted wafer.

Abstract: A semiconductor wafer contains a plurality of semiconductor die. The semiconductor wafer is diced to separate the semiconductor die. The semiconductor die are transferred onto a carrier. A die extension region is formed around a periphery of the semiconductor die on the carrier. The carrier is removed. A plurality of through hole vias (THV) is formed in first and second offset rows in the die extension region. A conductive material is deposited in the THVs. A first RDL is formed between contact pads on the semiconductor die and the THVs. A second RDL is formed on a backside of the semiconductor die in electrical contact with the THVs. An under bump metallization is formed in electrical contact with the second RDL. Solder bumps are formed on the under bump metallization. The die extension region is singulated to separate the semiconductor die.

Abstract: A packaged semiconductor device (100) comprising a semiconductor chip (101) of an area having a first surface (101a) including a plurality of bond pads (102) linearly arrayed, adjacent pads having a first pitch (103) center-to-center; an insulating layer (110) on the first chip surface covering the chip area, the layer having a height (116) and a second surface (110a) parallel to the first surface; the second surface including contact nodes (120) in staggered array, the nodes having the same plurality as the pads, adjacent nodes having a second pitch (121) center-to-center greater than the first pitch; and metal wires through the layer height connecting the pads to respective nodes.

Abstract: A wafer having a die area and a scribe street is formed. The die area comprises die circuitry and a plurality of bond pads, and the scribe street comprises a test structure. Circuitry of the test structure is probed, and then a passivation layer overlying the surface of the wafer is formed, the passivation layer overlying the plurality of bond pads and overlying the test structure. Openings in the regions of the passivation layer overlying the plurality of bond pads are then formed to expose the plurality of bond pads while retaining the regions of the passivation layer overlying the test structure until singulation of the wafer. Pad metallizations are formed at the plurality of bond pads via the openings in the regions of the passivation layer and the wafer is singulated. The resulting dies may be packaged and the resulting IC packages may be implemented in electronic devices.

Abstract: Adherence of contaminant residues or particles is suppressed, corrosion of exposed surfaces is substantially reduced or eliminated during the process of dicing a wafer by sawing. A fluoride-free aqueous composition comprising a dicarboxylic acid and/or salt thereof; a hydroxycarboxylic acid and/or salt thereof or amine group containing acid, a surfactant and deionized water is employed.

Abstract: An embodiment is a method and apparatus to induce flaw formation in nitride semiconductors. Regions of a thin film structure are selectively decomposed within a thin film layer at an interface with a substrate to form flaws in a pre-determined pattern within the thin film structure. The flaws locally concentrate stress in the pre-determined pattern during a stress-inducing operation. The stress-inducing operation is performed. The stress-inducing operation causes the thin film layer to fracture at the pre-determined pattern.

Abstract: A method of manufacturing an array of semiconductor devices comprises providing a first carrier having multiple chip alignment regions. Multiple chips are placed over the multiple chip alignment regions. Then, alignment of the chips to the multiple chip alignment regions is obtained. The multiple chips are then placed on a second carrier. The first carrier is detached from the multiple chips. An encapsulation material is applied to the multiple chips to form an encapsulated array of semiconductor chips. The second carrier is then detached from the encapsulated array of semiconductor devices.

Abstract: In one embodiment, a semiconductor package includes a semiconductor chip having a first contact region on a first major surface and a second contact region on an opposite second major surface. The semiconductor chip is configured to regulate flow of a current from the first contact region to the second contact region. An encapsulant is disposed at the semiconductor chip. A first contact plug is disposed within the encapsulant and coupled to the first contact region. A second side conductive layer is disposed under the second major surface and coupled to the second contact region. A through via is disposed within the encapsulant and coupled to the second side conductive layer. The first contact plug and the through via form terminals above the first major surface for contacting the semiconductor package.