With Subsequent Division Of Substrate Into Plural Individual Devices (epo) Patents (Class 257/E21.599)

  • Publication number: 20130119520
    Abstract: A microelectronic element is disclosed that includes a semiconductor chip and a continuous monolithic metallic edge-reinforcement ring that covers each of the plurality of edge surfaces of the semiconductor chip and extending onto the front surface. The semiconductor chip may have front and rear opposed surfaces and a plurality of contacts at the front surface and edge surfaces extending between the front and rear surfaces. The semiconductor chip may also embody at least an active device or a passive device.
    Type: Application
    Filed: November 11, 2011
    Publication date: May 16, 2013
    Applicant: INVENSAS CORP.
    Inventor: Ilyas Mohammed
  • Patent number: 8440487
    Abstract: The present disclosure provides methods for manufacturing a radio frequency (RF) powder including a plurality of RF particles, each of which includes a circuit element. A plurality of circuit elements, each corresponding to a different RF particle, may be formed on a first surface of a substrate. Grooves may be etched into the first surface of the substrate between the plurality of circuit elements. A protection film may be formed on each of the plurality of circuit elements and a portion of the substrate between a second, opposite surface of the substrate and bottoms of the grooves may be removed so that each of the plurality of circuit elements is associated with the remaining portion of the substrate.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: May 14, 2013
    Assignee: Philtech Inc.
    Inventor: Yuji Furumura
  • Patent number: 8440505
    Abstract: An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: May 14, 2013
    Assignee: International Business Machines Corporation
    Inventors: Deepak Kulkarni, Michael W. Lane, Satyanarayana V. Nitta, Shom Ponoth
  • Publication number: 20130115757
    Abstract: A method for separating a plurality of dies is provided, the method including: defining one or more portions to be removed from a carrier including a plurality of dies by chemically changing the properties of the one or more portions to be removed located between the dies; performing a front-end-of-line FEOL process on at least one die to form at least one semiconductor device; and selectively removing the one or more portions of the carrier whose properties were chemically changed for separating the dies along the removed one or more portions.
    Type: Application
    Filed: November 7, 2011
    Publication date: May 9, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Manfred Engelhardt, Petra Fischer
  • Publication number: 20130115756
    Abstract: A semiconductor wafer processing method forms a plurality of wafer dividing grooves respectively along a plurality of crossing streets formed on the front side of a semiconductor substrate of a semiconductor wafer to thereby partition a plurality of regions where a plurality of devices are respectively formed. The semiconductor wafer has a passivation film formed on the front side of the semiconductor substrate so as to cover the devices and the streets. A first laser beam is applied to the passivation film along each street to thereby form a film dividing groove in the passivation film along each street. A second laser beam is applied to the semiconductor substrate along the film dividing groove formed in the passivation film, thereby forming the wafer dividing groove in the semiconductor substrate along each street.
    Type: Application
    Filed: October 29, 2012
    Publication date: May 9, 2013
    Applicant: DISCO CORPORATION
    Inventor: Disco Corporation
  • Publication number: 20130115755
    Abstract: A method for separating semiconductor die includes forming a porous region on a semiconductor wafer and separating the die at the porous region using mechanical or other means.
    Type: Application
    Filed: January 27, 2012
    Publication date: May 9, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Manfred Engelhardt, Petra Fischer
  • Publication number: 20130113110
    Abstract: The present invention provides a semiconductor structure having a lateral TSV and a manufacturing method thereof. The semiconductor structure includes a chip having an active side, a back side disposed opposite to the active side, and a lateral side disposed between the active side and the back side. The chip further includes a contact pad, a lateral TSV and a patterned conductive layer. The contact pad is disposed on the active side. The lateral TSV is disposed on the lateral side. The patterned conductive layer is disposed on the active side and is electrically connected to the lateral TSV and the contact pad.
    Type: Application
    Filed: January 3, 2012
    Publication date: May 9, 2013
    Inventors: Tzung-Han Lee, Chung-Lin Huang, Ron Fu Chu, Dah-Wei Liu
  • Publication number: 20130113092
    Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.
    Type: Application
    Filed: December 21, 2011
    Publication date: May 9, 2013
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Hin Hwa Goh, Yu Gu, Il Kwon Shim, Rui Huang, Seng Guan Chow, Jianmin Fang, Xia Feng
  • Patent number: 8435867
    Abstract: Foreign matter formed over (or adhered to) a surface of a lead is reliably removed. A laser beam is applied to a residual resin (sealing body) which is formed in (or adhered to) a region surrounded by a sealing body (a first sealing body), a lead exposed (projected) from the sealing body, and a dam bar. The foreign matter formed over (or adhered to) the surface of the lead can be reliably removed by washing the surface of the lead after the removal of the residual resin. Thus, in a subsequent plating step, the reliability (wettability, adhesion with the lead) of a plating film to be formed over the surface of the lead can be improved.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: May 7, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Atsushi Fujishima, Haruhiko Harada
  • Publication number: 20130105977
    Abstract: An embodiment electronic device comprises a semiconductor chip including a first main face, a second main face and side faces each connecting the first main face to the second main face. A metal layer is disposed above the second main face and the side faces, the metal layer including a porous structure.
    Type: Application
    Filed: October 27, 2011
    Publication date: May 2, 2013
    Applicant: Infineon Technologies AG
    Inventors: Khalil Hosseini, Frank Kahlmann
  • Publication number: 20130105949
    Abstract: In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions having a semiconductor device formed therein and insulated from each other, and a plurality of wiring electrodes connected to the semiconductor devices respectively formed in the plurality of device regions and extending from the device regions into the inside of the scribe-groove parts. The plurality of wiring electrodes are arranged in a partial arrangement pattern in which the wiring electrodes are arranged along only a part of four boundary sides, corresponding to boundaries between each of the device regions and the scribe-groove parts. Further, the plurality of wiring electrodes extend into the scribe-groove part from only one of two device regions adjacent to each other with the scribe-groove part therebetween.
    Type: Application
    Filed: November 1, 2011
    Publication date: May 2, 2013
    Applicants: SAE MAGNETICS (H.K.) LTD., HEADWAY TECHNOLOGIES, INC.
    Inventors: Yoshitaka SASAKI, Hiroyuki ITO, Shigeki TANEMURA, Kazuki SATO, Atsushi IIJIMA
  • Publication number: 20130105982
    Abstract: A fan-out wafer level package is provided with a semiconductor die embedded in a reconstituted wafer. A redistribution layer is positioned over the semiconductor die, and includes a land grid array on a face of the package. A copper heat spreader is formed in the redistribution layer over the die in a same layer as a plurality of electrical traces configured to couple circuit pads of the semiconductor die to respective contact lands of the land grid array. In operation, the heat spreader improves efficiency of heat transfer from the die to the circuit board.
    Type: Application
    Filed: November 2, 2011
    Publication date: May 2, 2013
    Applicants: STMICROELECTRONICS GRENOBLE2 SAS, STMICROELECTRONICS PTE LTD.
    Inventors: Yonggang Jin, Romain Coffy, Jerome Teysseyre
  • Patent number: 8431442
    Abstract: A method of manufacturing semiconductor chips includes providing a semiconductor substrate including circuit regions, irradiating the semiconductor substrate with a laser beam onto to form a frangible layer, and polishing the semiconductor substrate to separate the circuit regions of the semiconductor substrate from one another into semiconductor chips. The frangible layer may be removed completely during the polishing of the semiconductor substrate.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: April 30, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Wook Park, Tae Gyeong Chung, Ho Geon Song, Won Chul Lim
  • Publication number: 20130099308
    Abstract: According to an embodiment, a method of forming a semiconductor device includes: providing a wafer having a semiconductor substrate with a first side a second side opposite the first side, and a dielectric region arranged on the first side; mounting the wafer with the first side on a carrier system; etching a deep vertical trench from the second side through the semiconductor substrate to the dielectric region, thereby insulating a mesa region from the remaining semiconductor substrate; and filling the deep vertical trench with a dielectric material.
    Type: Application
    Filed: October 24, 2011
    Publication date: April 25, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Hermann Gruber, Thomas Gross, Andreas Peter Meiser, Markus Zundel
  • Publication number: 20130099250
    Abstract: An improved structure of semiconductor chips with enhanced die strength and a fabrication method thereof are disclosed. The improved structure comprises a substrate, an active layer, and a backside metal layer, in which the active layer is formed on the front side of the substrate and includes at least one integrated circuit; the backside metal layer is formed on the backside of the substrate, which fully covers the area corresponding to the area covered by the integrated circuits in the active layer. By using the specific dicing process of the present invention, the backside metal layer and the substrate can be diced tidily. Die cracking on the border between the substrate and the backside metal layer of the diced single chip can be prevented, and thereby the die strength can be significantly enhanced.
    Type: Application
    Filed: January 24, 2012
    Publication date: April 25, 2013
    Inventor: Chang-Hwang HUA
  • Patent number: 8426250
    Abstract: The present invention discloses an apparatus including: a laser beam directed at a wafer held by a chuck mounted on a stage inside a process chamber; a focusing mechanism for the laser beam; a steering mechanism for the laser beam; an optical scanning mechanism for the laser beam; a mechanical scanning system for the stage; an etch chemical induced by the laser beam to etch the wafer and form volatile byproducts; a gas feed line to dispense the etch chemical towards the wafer; and a gas exhaust line to remove any excess of the etch chemical and the volatile byproducts.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: April 23, 2013
    Assignee: Intel Corporation
    Inventors: George Vakanas, George Chen, Yuval Greenzweig, Eric Li, Sergei Voronov
  • Publication number: 20130095613
    Abstract: In aspects of the invention, a holding stage of a pick up system can include a first stage on which a semiconductor chip is mounted with an adhesive sheet put in between, a second stage supporting the first stage, and an evacuation pipe. The first stage can be provided with a plurality of grooves, projections each being formed with side walls of adjacent grooves, and air holes connected to the grooves. The semiconductor chip can be mounted on the first stage so that the whole end portion of the semiconductor chip does not position on one groove. Then, a closed space surrounded by the adhesive sheet and the first and second stages and can be evacuated to make the semiconductor chip held on the projections. Thereafter, the semiconductor chip can be picked up by a collet.
    Type: Application
    Filed: October 12, 2012
    Publication date: April 18, 2013
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Yoko TANAKA
  • Publication number: 20130093094
    Abstract: Methods and apparatus for die assembly. A method includes forming a trench extending from an active surface of a semiconductor substrate comprising a plurality of integrated circuit dies having connector terminals extending from the active surface, the trench extending into, but not through, the semiconductor substrate; forming a protective layer overlying the active surface of the semiconductor substrate and the trench, and covering the lower portion of the connector terminals; opening a pre-dicing opening in the protective layer and within the trench; applying a tape over the active surface of the semiconductor wafer, the protective layer and the connector terminals; and performing an operation on a backside of the semiconductor substrate to remove material until the pre-dicing opening is exposed on the backside of the semiconductor wafer. An apparatus includes a semiconductor substrate with integrated circuits and a protective layer surrounding connector terminals of integrated circuits.
    Type: Application
    Filed: October 18, 2011
    Publication date: April 18, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chung Sung, Yu-Chih Liu, Wei-Ting Lin, Chien-Hsiun Lee
  • Publication number: 20130095586
    Abstract: A method of cutting light emitting element packages includes preparing a ceramic substrate having a surface on which a plurality of light emitting element chips are mounted and a light-transmitting material layer is formed to cover the plurality of light emitting element chips; partially removing the light-transmitting material layer between the plurality of light emitting element chips along a cutting line by using a mechanical cutting method; and separating individual light emitting element packages by cutting the ceramic substrate along the cutting line by using a laser cutting method.
    Type: Application
    Filed: February 29, 2012
    Publication date: April 18, 2013
    Inventors: Eui-seok KIM, Won-soo JI, Choo-ho KIM, Shin-min RHEE, Dong-hun LEE, Hee-young JUN
  • Patent number: 8420445
    Abstract: A method for packing semiconductor components is provided, in which a first side of a first wafer is connected to at least one further wafer, wherein at least one of the wafers has a plurality a semiconductor circuits and wherein trenches are made in the second side of the first wafer opposite to the first side and divide the first wafer into a plurality of parts, which are separated from one another by the trenches, but are connected mechanically to one another by means of the at least one further wafer, and wherein the connecting region between the first wafer and the at least one further wafer has been or will be laterally exposed in the trenches. A coating that covers the connecting region is then applied to the regions of the trenches in which the connecting region is exposed.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: April 16, 2013
    Assignee: Wafer-Level Packaging Portfolio LLC
    Inventor: Juergen Leib
  • Patent number: 8420505
    Abstract: A process to thin semiconductor wafers to less than 50 microns employs a dissolvable photoresist or polyimide or other glue material to hold a thick carrier plate such as a perforated glass to the top surface of a thick processed wafer and to grind or otherwise remove the bulk of the wafer from its rear surface, leaving only the preprocessed top surface, which may include semiconductor device diffusions and electrodes. A thick metal such as copper or a more brittle copper alloy is then conductively secured to the ground back surface and the glue is dissolved and the carrier plate is removed. The wafer is then cleaned and diced into plural devices such as MOSFETs; integrated circuits and the like.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: April 16, 2013
    Assignee: International Rectifier Corporation
    Inventor: Igor Bol
  • Patent number: 8420419
    Abstract: A method of fabricating a III-nitride semiconductor laser device includes: preparing a substrate product, where the substrate product has a laser structure, the laser structure includes a semiconductor region and a substrate of a hexagonal III-nitride semiconductor, the substrate has a semipolar primary surface, and the semiconductor region is formed on the semipolar primary surface; scribing a first surface of the substrate product to form a scribed mark, the scribed mark extending in a direction of an a-axis of the hexagonal III-nitride semiconductor; and after forming the scribed mark, carrying out breakup of the substrate product by press against a second region of the substrate product while supporting a first region of the substrate product but not supporting the second region thereof, to form another substrate product and a laser bar.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: April 16, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shimpei Takagi, Yusuke Yoshizumi, Koji Katayama, Masaki Ueno, Takatoshi Ikegami
  • Publication number: 20130087901
    Abstract: In one aspect of the present invention, an integrated circuit package with an exposed die and a protective housing will be described. The housing extends beyond the exposed back surface of the die to help protect it from damage. The integrated circuit package includes a lead frame and an integrated circuit die. The integrated circuit die is electrically and physically attached to the lead frame. The housing encapsulates the lead frame and the die. The housing also includes a recessed region at the bottom of the package where the back surface of the die is exposed. There is a protruding protective structure at the bottom of the package that helps to protect the die and prevent its exposed back surface from coming in contact with an external object.
    Type: Application
    Filed: October 10, 2011
    Publication date: April 11, 2013
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Lee Han Meng @ Eugene LEE, Kok Leong YEO, Kooi Choon OOI, Chen Seong CHUA
  • Publication number: 20130089954
    Abstract: There is provided a method of fabricating an electronic device having a flexible device, which is fabricated using a support substrate by Joule-heating induced film separation (JIFS). A method of fabricating an electronic device having a flexible device includes providing a support substrate, coating a conductive layer on one surface of the support substrate, forming a plastic substrate on the other surface of the support substrate, forming one or more thin-film transistors (TFTs) on the plastic substrate, forming an electronic device electrically connected to any one of the TFTs, and separating the plastic substrate from the conductive layer by generating Joule-heating through application of an electric field to the conductive layer. Accordingly, the flexible device can be separated from the support substrate without deformation of the support substrate and degradation of the electronic device.
    Type: Application
    Filed: October 6, 2012
    Publication date: April 11, 2013
    Applicant: EnSilTech Corporation
    Inventor: EnSilTech Corporation
  • Publication number: 20130087926
    Abstract: A stacked semiconductor device includes a first, a second, a third, and a fourth semiconductor device. A first major surface of each of the first and second semiconductor devices which includes the active circuitry directly face each other, and a first major surface of each of the third and fourth semiconductor devices which includes the active circuitry directly face each other. A second major surface of the second semiconductor device directly faces a second major surface of the third semiconductor device. The stacked semiconductor device includes a plurality of continuous conductive vias, wherein each continuous conductive via extends from the second major surface of the first device, through the first device, second device, third device, and fourth device to the second major surface of the fourth device. Each of the semiconductor devices may include a beveled edge at the first major surface on at least one edge of the device.
    Type: Application
    Filed: October 7, 2011
    Publication date: April 11, 2013
    Inventors: Perry H. Pelley, Kevin J. Hess, Michael B. McShane
  • Patent number: 8415683
    Abstract: The present invention provides a manufacturing method of an LED chip. First, a device layer is formed on a growth substrate, wherein the device layer has a first surface connected to the growth substrate and a second surface. Next, a plurality of first trenches are formed on the second surface of the device layer. Then, a protection layer is formed on the side walls of the first trenches. After that, the second surface is bonded with a supporting substrate and the device layer is then separated from the growth substrate. Further, a plurality of second trenches corresponding to the first trenches are formed in the device layer to form a plurality of LEDs, wherein the second trenches extend from the first surface to the bottom portions of the first trenches. Furthermore, a plurality of electrodes are formed on the first surface of the device layer.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: April 9, 2013
    Assignee: Lextar Electronics Corp.
    Inventors: Chia-En Lee, Cheng-Ta Kuo, Der-Ling Hsia
  • Patent number: 8415235
    Abstract: In a conventional adhesive sheet laminated with a die attachment film, the die attachment film sometimes drops off from the die chip at the time of pick-up after die chip formation by dicing a wafer. The present invention provides an adhesive including a (meth)acrylate ester polymer, a urethane acrylate oligomer having 4 or more vinyl groups, and silicone microparticles. Another aspect of the invention, provides a process for producing electronic components, the process including: a wafer-pasting step of pasting a wafer on a surface of a die attachment film of an adhesive sheet; a dicing step of dicing the wafer into die chips; and a pick-up step of peeling the die attachment film from the adhesive layer after the dicing step, and picking up the die chip together with the die attachment film.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: April 9, 2013
    Assignee: Denki Kagaku Kogyo Kabushiki Kaisha
    Inventors: Satoru Kawata, Takeshi Saito
  • Publication number: 20130082366
    Abstract: There is provided a semiconductor package including: a substrate having at least one element mounted thereon; a prepreg layer stacked on the substrate to cover the at least one element; a metal shielding layer stacked on the prepreg layer to electrically shield the at least one element; and a via electrode penetrating through the metal shielding layer and the prepreg layer and electrically connected to a ground electrode formed on the substrate.
    Type: Application
    Filed: December 14, 2011
    Publication date: April 4, 2013
    Inventor: Kwang Chun JUNG
  • Publication number: 20130084658
    Abstract: In accordance with an embodiment of the present invention, a semiconductor device is manufactured by arranging a plurality of semiconductor devices on a frame with an adhesive foil. The plurality of semiconductor devices is attached to the adhesive foil. The plurality of semiconductor devices is removed from the frame with the adhesive foil using a carbon dioxide snow jet and/or a laser process.
    Type: Application
    Filed: October 4, 2011
    Publication date: April 4, 2013
    Applicant: Infineon Technologies AG
    Inventors: Mathias Vaupel, Sebastian Bernrieder, Adolf Koller, Stefan Martens
  • Patent number: 8409969
    Abstract: An optical device wafer has a device area where a plurality of optical devices are formed on the front side of a sapphire substrate, and a peripheral marginal area surrounding the device area. The device area projects from the peripheral marginal area. A break start point is formed on the front side of the sapphire substrate by applying a laser beam along the boundary between the device area and the peripheral marginal area. A protective member is attached to the front side of the optical device wafer. The optical device wafer is held on a chuck table of a grinding apparatus so that the protective member comes into contact with a holding surface of the chuck table. The back side of the sapphire substrate is ground to reduce the thickness thereof to a predetermined thickness.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: April 2, 2013
    Assignee: Disco Corporation
    Inventor: Yohei Gokita
  • Publication number: 20130078766
    Abstract: A method for manufacturing a semiconductor apparatus includes: forming a protrusion made of a conductor on each of the electrodes provided on a semiconductor wafer top face side of a plurality of semiconductor devices formed in a semiconductor wafer; making a trench in the top face between the plurality of semiconductor devices; filling an insulator into a gap between the protrusions and into the trench to form a sealing member; grinding a bottom face of the semiconductor wafer opposing the top face until the sealing member being exposed to divide the semiconductor wafer into each of the semiconductor devices; forming a first lead made of a conductor on each of the protrusions, the first lead forming a portion of a first external electrode; and forming a conductive material layer directly to form a second lead on the bottom face of the plurality of semiconductor devices.
    Type: Application
    Filed: November 14, 2012
    Publication date: March 28, 2013
    Inventors: Takao NOGI, Tomoyuki KITANI, Akira TOJO, Kentaro SUGA
  • Patent number: 8404564
    Abstract: There is provided an adhesive film for a semiconductor, which can be attached to a semiconductor wafer at low temperature and which allows semiconductor chips to be obtained at high yield from the semiconductor wafer while sufficiently inhibiting generation of chip cracks and burrs. The adhesive film for a semiconductor comprises a polyimide resin that can be obtained by reaction between a tetracarboxylic dianhydride containing 4,4?-oxydiphthalic dianhydride represented by chemical formula (I) below and a diamine containing a siloxanediamine represented by the following general formula (II) below, and that can be attached to a semiconductor wafer at 100° C. or below.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: March 26, 2013
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Yuuki Nakamura, Tsutomu Kitakatsu, Youji Katayama, Keiichi Hatakeyama
  • Patent number: 8404565
    Abstract: A manufacturing method and a structure of a surface-mounting type diode co-constructed from a silicon wafer and a base plate, in the method, a diffused wafer is stacked with a high temperature durable high strength base plate to have them sintered and molten together for connecting with each other to form a co-constructure; then the diffused wafer is processed by etching and ditching for filling with insulation material, electrodes of the diffused wafer are metalized and all on an identical plane, then production of all functional lines is completed; and then the co-constructure is cut to form a plurality of separated individuals which each forms a surface-mounting type diode to be applied straight. In comparison with the conventional techniques, manufacturing of the present invention is simplified and economic in reducing working hours, size and cost of production and the wafer is not subjected to breaking during manufacturing.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: March 26, 2013
    Assignee: Formosa Microsemi Co., Ltd.
    Inventors: Wen-Ping Huang, Paul Wu
  • Patent number: 8404522
    Abstract: The present invention relates to a dicing tape-integrated film for semiconductor back surface including: a dicing tape including a base material and a pressure-sensitive adhesive layer laminated in this order, and a film for semiconductor back surface provided on the pressure-sensitive adhesive layer of the dicing tape, where the pressure-sensitive adhesive layer has a thickness of from 20 ?m to 40 ?m.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: March 26, 2013
    Assignee: Nitto Denko Corporation
    Inventors: Goji Shiga, Naohide Takamoto, Fumiteru Asai
  • Publication number: 20130069206
    Abstract: A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 21, 2013
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kazutaka Yoshizawa, Taiji Ema, Takuya Moriki
  • Publication number: 20130069225
    Abstract: A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.
    Type: Application
    Filed: September 21, 2011
    Publication date: March 21, 2013
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang
  • Publication number: 20130069205
    Abstract: A semiconductor wafer and a method which are capable of reducing chippings or cracks generated during the die sawing process. The semiconductor wafer comprises a plurality of dies formed on the semiconductor wafer in row and column directions and separated from each other by scribe lane areas, and a passivation layer formed on the plurality of dies and the scribe lane areas, wherein a groove structure is formed in the passivation layer. The groove structure includes grooves formed along the scribe lane areas, and corners of the passivation layer at intersections of the grooves being removed.
    Type: Application
    Filed: December 14, 2011
    Publication date: March 21, 2013
    Applicant: Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: XIANJIE NING
  • Publication number: 20130071970
    Abstract: The present invention makes it possible to inhibit cutting burrs from forming in package dicing. It is possible, in a package dicing step, to: inhibit cutting burrs from forming by cutting a part of a sealing body including leads with a soft resin blade as first step cutting; successively decrease the generation of a remaining uncut part because the progression of the abrasion of a blade main body is slow by cutting only a resin part that is a remaining uncut part with a hard electroformed blade as second step cutting; and resultantly improve the reliability of a semiconductor device.
    Type: Application
    Filed: July 31, 2012
    Publication date: March 21, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Yuji FUJIMOTO
  • Publication number: 20130069227
    Abstract: A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.
    Type: Application
    Filed: May 22, 2012
    Publication date: March 21, 2013
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang
  • Patent number: 8399986
    Abstract: A method of positioning at least 2 chips simultaneously on a substrate by parallel stochastic assembly in a first liquid is disclosed. In one aspect, the chips are directed to target sites on the substrate within the first liquid. The target sites are covered with a second liquid. The second liquid and the first liquid are immiscible. The chips are attracting the first liquid. A predetermined surface is chosen or treated on each chip such that it is selectively attracted by the second liquid and attracting the first liquid.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: March 19, 2013
    Assignees: IMEC, Katholieke Universiteit Leuven
    Inventors: Massimo Mastrangeli, Caroline Whelan, Wouter Ruythooren
  • Patent number: 8399338
    Abstract: The objective is to limit pickup defects when chips with a semi-cured adhesive layer are picked up following dicing by lowering the adhesive strength of an ultraviolet curable adhesive beforehand while improving the cohesive force. Provided is a dicing method for semiconductor wafers with a semi-cured adhesive layer that comprises a process to coat the back surface of semiconductor wafers with a paste-like adhesive and semi-cure the paste-like adhesive in a sheet form using heating or ultraviolet irradiation to form a semi-cured adhesive layer, a gluing process to glue an adhesive sheet, wherein an ultraviolet curable adhesive is laminated on a base film, onto the semi-cured adhesive layer, an ultraviolet irradiation process to apply ultraviolet irradiation to the ultraviolet curable adhesive, and a dicing process to dice the semi-cured adhesive layer glued to the adhesive sheet and the semiconductor wafers.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: March 19, 2013
    Assignee: Denki Kagaku Kogyo Kabushiki Kaisha
    Inventors: Takeshi Saito, Tomomichi Takatsu
  • Publication number: 20130065334
    Abstract: A method of manufacturing a laser diode device includes: forming semiconductor layers on top of one another and supported by a top surface of a semiconductor substrate, the semiconductor layers including an active layer, forming a separation trench by etching and removing portions of the semiconductor layers, from a top semiconductor layer to and including the active layer; scribing a groove in a bottom surface of the semiconductor substrate, directly opposite and along the separation trench; and propagating a crack from the groove, splitting the semiconductor substrate along the groove and forming a cleaved surface extending from the bottom surface of the semiconductor substrate to a bottom surface of the separation trench.
    Type: Application
    Filed: May 17, 2012
    Publication date: March 14, 2013
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Takashi MOTODA
  • Publication number: 20130065336
    Abstract: A method for fabricating a group-III nitride semiconductor laser device stably supplies laser cavity mirrors having a low lasing threshold current through the use of a semi-polar plane. A blade 5g is forced down through a first region ER1 to keep the first region ER1 squeezed between a support member H2 and a movable member H1 together with a part of a protective sheet TF in contact with the first region ER1 while the tension generated in the area of the protective sheet TF in contact with the first region ER1 with the movable member H1 increases until the semi-polar principal surface SF at an end face EG1 of the first region ER1 tilts by a deflection angle THETA from the semi-polar principal surface SF of a second region ER2, and a force is thereby generated in the first region ER1 in a direction opposite to the direction of travel of the blade 5g toward the first region ER1.
    Type: Application
    Filed: August 6, 2012
    Publication date: March 14, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Shimpei TAKAGI
  • Publication number: 20130065362
    Abstract: A flip chip package manufacturing method is provided. A non-conductive film is pressed onto a wafer with multiple conductive bumps. The wafer is cut to multiple single chips. A carrier is provided, and a thermo-compression flip chip bonding process is executed to bond the non-conductive film onto the carrier. The carrier is transferred into a chamber with enclosed, pneumatic pressurized and heatingable characteristics to execute a de-void process to eliminate the bubbles and to execute a high-temperature soldering process to solder the single chip onto the carrier. The sequence of the de-void process and the high-temperature soldering process may exchange.
    Type: Application
    Filed: June 27, 2012
    Publication date: March 14, 2013
    Applicant: ABLEPRINT TECHNOLOGY CO., LTD.
    Inventor: HORNG CHIH HORNG
  • Publication number: 20130065337
    Abstract: A method for fabricating a group-III nitride semiconductor laser device having a semi-polar surface provides a laser cavity mirror which can reduce lasing threshold current. A support plate H tilts at an angle THETA from an m-axis toward a reference plane Ab defined by a direction PR of travel of the blade 5g and an a-axis in a c-m plane while the direction PR is being orthogonal to the front surface Ha of the support plate H. The blade 5g is positioned so as to be aligned to a plane which includes an intersection P1 between the endmost scribe mark 5b1 among a plurality of scribe marks 5b and the front surface 5a of the substrate product 5 and extends along the direction PR. In the case where the angle ALPHA defined ranges either from 71 to 79 degrees or from 101 to 109 degrees, the angle THETA then ranges from 11 to 19 degrees, and thereby the reference plane Ab along the direction PR extends along the c-plane orthogonal to the c-axis.
    Type: Application
    Filed: August 6, 2012
    Publication date: March 14, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Shimpei TAKAGI
  • Publication number: 20130065361
    Abstract: A method for manufacturing a semiconductor package structure is disclosed. In one embodiment, the method includes the steps of forming a plurality of conductive pastes on a matrix lead frame with a groove located within a predetermined distance from each conductive paste on the lead; partially curing the conductive pastes so that the conductive pastes are in a semi-cured state; preparing at least one chip with a plurality of bumps thereon; electrically connecting the chip and the lead by implanting the bumps into the semi-cured conductive pastes, wherein the groove on the lead of the matrix lead frame is configured to receive overflowed semi-cured conductive pastes; curing the semi-cured conductive pastes to completely secure the bumped chip; and forming an encapsulating material covering the lead frame and the chip. The method can also be applied in pre-molded lead frame package.
    Type: Application
    Filed: September 14, 2011
    Publication date: March 14, 2013
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventor: Geng-Shin Shen
  • Publication number: 20130062737
    Abstract: According to one embodiment, a semiconductor device comprises a device substrate, and a supporting substrate. The supporting substrate is joined onto the device substrate. The device substrate has a first groove in an outer circumferential portion on a joint surface side to the supporting substrate.
    Type: Application
    Filed: March 23, 2012
    Publication date: March 14, 2013
    Inventors: Satoshi HONGO, Kazumasa Tanida, Kenji Takahashi
  • Patent number: 8394706
    Abstract: The present invention provides a high yield pathway for the fabrication, transfer and assembly of high quality printable semiconductor elements having selected physical dimensions, shapes, compositions and spatial orientations. The compositions and methods of the present invention provide high precision registered transfer and integration of arrays of microsized and/or nanosized semiconductor structures onto substrates, including large area substrates and/or flexible substrates. In addition, the present invention provides methods of making printable semiconductor elements from low cost bulk materials, such as bulk silicon wafers, and smart-materials processing strategies that enable a versatile and commercially attractive printing-based fabrication platform for making a broad range of functional semiconductor devices.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: March 12, 2013
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Ralph G. Nuzzo, John A. Rogers, Etienne Menard, Keon Jae Lee, Dahl-Young Khang, Yugang Sun, Matthew Meitl, Zhengtao Zhu, Heung Cho Ko, Shawn Mack
  • Publication number: 20130056859
    Abstract: In one embodiment of a method of manufacturing a semiconductor device, a plurality of substantially columnar trenches are formed along a region for forming a dicing line in a semiconductor substrate having first surface and second surfaces opposed to each other, from the first surface. The substrate is subjected to a heat treatment. At least one hollow portion is formed in the substrate by migration of a material which composes the substrate. Semiconductor devices are formed in semiconductor regions of the substrate which are surrounded by the region for forming the dicing line. The semiconductor regions are provided on a side of the first surface. A portion of the substrate is removed from a side of the second surface until the thickness is reduced to a predetermined value. The substrate is divided into chips along a dicing line from at least the one hollow portion as a starting point.
    Type: Application
    Filed: March 13, 2012
    Publication date: March 7, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Akihiro TAKAHASHI
  • Publication number: 20130056857
    Abstract: A manufacturing method for a device chip having a substrate, a device formed on the front side of the substrate, and chip identification information marked inside the substrate includes preparing a device wafer having a base wafer and a plurality of devices formed on the front side of the base wafer so as to be partitioned by division lines, next applying a laser beam having a transmission wavelength to the device wafer from the back side thereof in the condition where the focal point of the laser beam is set inside the base wafer at the positions respectively corresponding to the devices, thereby forming a plurality of modified layer marks as the chip identification information inside the base wafer at the positions respectively corresponding to the devices, and finally dividing the device wafer along the division lines to obtain a plurality of device chips.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 7, 2013
    Applicant: DISCO CORPORATION
    Inventor: Koichi KONDO