Abstract: A semiconductor device which comprises a channel layer formed from a semiconductor channel component material in the form of crystalline micro particles, micro rods, crystalline nano particles, or nano rods, and doped with a semiconductor dopant.

Abstract: A method of providing miniaturized size down to nanoscale electronic materials, which may be easily incorporated into the future ever-scaling down power electronics, microelectronics and nanoelectronics device systems, is disclosed. A linear or nonlinear nanoparticle (nanowire) junction design that allows precise controllability over an electronic device (e.g., a varistor) performance, which is typically difficult for the traditional sintered bulk varistor, is also disclosed. A localized doping and chemical modulation, across junctions allows flexible and tunable design over the nanoscale grain boundary band engineering is further disclosed. Furthermore, a method of operating memory, using electrostatic potential modulated coding and decoding across periodic nanoparticle grain boundary linearly, is also disclosed.

Abstract: Disclosed is a semiconductor device having a p-n junction with reduced junction leakage in the presence of metal silicide defects that extend to the junction and a method of forming the device. Specifically, a semiconductor layer having a p-n junction is formed. A metal silicide layer is formed on the semiconductor layer and a dopant is implanted into the metal silicide layer. An anneal process is performed causing the dopant to migrate toward the metal silicide-semiconductor layer interface such that the peak concentration of the dopant will be within a portion of the metal silicide layer bordering the metal silicide-semiconductor layer interface and encompassing the defects. As a result, the silicide to silicon contact is effectively engineered to increase the Schottky barrier height at the defect, which in turn drastically reduces any leakage that would otherwise occur, when the p-n junction is in reverse polarity.

Abstract: An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes an enhanced well region to effectively increase a voltage at which punch-through occurs when compared to a conventional semiconductor device. The enhanced well region includes a greater number of excess carriers when compared to a well region of the conventional semiconductor device. These larger number of excess carriers attract more carriers allowing more current to flow through a channel region of the semiconductor device before depleting the enhanced well region of the carriers. As a result, the semiconductor device may accommodate a greater voltage being applied to its drain region before the depletion region of the enhanced well region and a depletion region of a well region surrounding the drain region merge into a single depletion region.

Abstract: An electric organic component and a method for the production thereof is disclosed. The component includes a substrate, a first electrode, a first electrically semiconductive layer on the first electrode, an organic functional layer on the first electrically semiconductive layer and a second electrode on the organic functional layer. The first or the second electrode may be arranged on the substrate. The electrically semiconductive layer is doped with a dopant which comprises rhenium compounds.

Abstract: A semiconductor device having an improved negative bias temperature instability lifetime characteristic is manufactured by forming a first insulating layer on a substrate, performing a first nitridation on the first insulating layer to form a second insulating layer, and sequentially performing a first and second anneal on the second insulating layer to form a third insulating layer, wherein the second anneal is performed at a higher temperature and with a different gas than the first anneal. A second nitridation is performed on the third insulating layer to form a fourth insulating layer, and a sequential third and fourth anneal on the fourth insulating layer forms a fifth insulating layer. The third anneal is performed at a higher temperature than the first anneal, and the fourth anneal is performed at a higher temperature than the second anneal and with a different gas than the third anneal.

Abstract: A semiconductor optical device includes a first mode converting core, a light amplification core, a second mode converting core, and a light modulation core disposed in a first mode converting region, a light amplification region, a second mode converting region, and a light modulating region of a semiconductor substrate, respectively, and a current blocking section covering at least sidewalls and a top surface of the light amplification core. The first mode converting core, the light amplification core, the second mode converting core, and the light modulation core are arranged along one direction in the order named, and are connected to each other in butt joints. The current blocking section includes first, second, and third cladding patterns sequentially stacked. The second cladding pattern is doped with dopants of a first conductivity type, and the first and third cladding patterns are doped with dopants of a second conductivity type.

Abstract: By removing an outer spacer of a transistor element, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, employing a wet chemical etch process, it is possible to position a stressed contact liner layer more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region, without affecting circuit elements in the P-type regions.

Abstract: A method for using a metal bilayer is disclosed. First, a bottom electrode is provided. Second, a dielectric layer which is disposed on and is in direct contact with the lower electrode is provided. Then, a metal bilayer which serves as a top electrode in a capacitor is provided. The metal bilayer is disposed on and is in direct contact with the dielectric layer. The metal bilayer consists of a noble metal in direct contact with the dielectric layer and a metal nitride in direct contact with the noble metal.

Abstract: A board on which a wiring having an electrode pad is formed is prepared. A resist film is formed on the board in order to cover the wiring and then the resist film is left on the electrode pad through patterning. An inorganic insulating film is formed on the board in order to cover the wiring and then the resist film is removed, thereby removing the inorganic insulating film provided on the resist film to leave the inorganic insulating film between the wirings. A solder resist layer is formed on the board in order to cover the wiring and then the electrode pad is exposed.

Abstract: The present disclosure provides a single-quantum dot device and a method of manufacturing the same. A transparent dielectric thin film is formed on a cover layer and an energy band of quantum dots is adjusted based on compressive stress due to difference in coefficient of thermal expansion therebetween. Specifically, the dielectric thin film has a lower coefficient of thermal expansion than the cover layer and compressive stress is applied to the cover layer by radiation of laser beams. Then, the quantum dots undergo compressive stress and the energy band of the quantum dots increases with increasing intensity of the laser beams.

Abstract: In a method of doping impurities, an amorphous layer is formed on a substrate. Impurities are implanted through a top surface of the amorphous layer to form a first doping region at an upper portion of the substrate. The first doping region and the amorphous layer are transformed into a second doping region and a recrystallized layer, respectively, by a laser annealing process. The recrystallized layer is removed.

Abstract: Magnetic devices, magnetoresistive structures, and methods and techniques associated with the magnetic devices and magnetoresistive structures are presented. For example, a magnetic device is presented. The magnetic device includes a ferromagnet, an antiferromagnet coupled to the ferromagnet, and a nonmagnetic metal proximate to the ferromagnet. The antiferromagnet provides uniaxial anisotropy to the magnetic device. A resistance of the nonmagnetic metal is dependent upon a direction of a magnetic moment of the ferromagnet.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes first and second stacked body, first and second semiconductor pillars, a connecting portion, a first memory film, and a dividing portion. The stacked bodies include a plurality of electrode films stacked along a first axis and as interelectrode insulating film provided between the electrode films. The first and second semiconductor pillars penetrate through the first and second stacked bodies along the first axis, respectively. The connecting portion electrically connects the first and second semiconductor pillars. The first memory film is provided between the electrode film and the semiconductor pillar. The dividing portion electrically divides the first and second electrode films from each other between the first semiconductor pillar and the second semiconductor pillar, is in contact with the connecting portion, and includes a stacked film including a material used for the first memory film.

Abstract: A Schottky diode optimizes the on state resistance, the reverse leakage current, and the reverse breakdown voltage of the Schottky diode by forming an insulated control gate over a region that lies between the metal-silicon junction of the Schottky diode and the n+ cathode contact of the Schottky diode.

Abstract: There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes: a substrate having a main surface; and a silicon carbide layer formed on the main surface of the substrate and including a side surface inclined relative to the main surface. The side surface substantially includes a {03-3-8} plane. The side surface includes a channel region.

Abstract: A memory device with band gap control is described. A memory cell can include a conductive oxide layer in contact with and electrically in series with an electronically insulating layer. A thickness of the electronically insulating layer is configured to increase from an initial thickness to a target thickness. The increased thickness of the electronically insulating layer can improve resistive memory effect, increase a magnitude of a read current during read operations, and lower barrier height with a concomitant reduction in band gap of the electronically insulating layer. The memory cell can include a memory element that comprises the conductive oxide layer and the electronically insulating layer and can optionally include a non-ohmic device (NOD). The memory cell can be positioned in a two-terminal cross-point array between a pair of conductive array lines across which voltages for data operations are applied. The memory cell and array can be fabricated BEOL.

Abstract: An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon. A Schottky barrier is modified by controlling an overlap of a gate and a source/drain and by controlling implantation, activation and/or gate processes.

Abstract: A method of sodium doping in fabricating CIGS/CIS based thin film solar cells includes providing a shaped substrate member. The method includes forming a barrier layer over the surface region followed by a first electrode layer, and then a sodium bearing layer. A precursor layer of copper, indium, and/or gallium materials having an atomic ratio of copper/group III species no greater than 1.0 is deposited over the sodium bearing layer. The method further includes transferring the shaped substrate member to a second chamber and subjecting it to a thermal treatment process within an environment comprising gas-phase selenium species, followed by an environment comprising gas-phase sulfur species with the selenium species being substantially removed to form an absorber layer.

Abstract: A phase change memory device having multiple metal silicide layers which enhances the current driving capability of switching elements and a method of manufacturing the same are presented. The device also includes switching elements, heaters, stack patterns, top electrodes, bit lines, word line contacts and word lines. The bottom of the switching elements are in electrical contact with the lower metal silicide layer and with an active area of silicon substrate. An upper metal silicide layer is interfaced between the top of the switching elements and the heaters. The stack patterns include phase change layers and top electrodes and are between the heaters and the top electrodes are in electrical contact with the top electrodes. The bit lines contact with the top electrode contacts. The word line contacts to the lower metal silicide film.

Abstract: To provide a semiconductor device capable of write operation to a selected magnetoresistive element without causing a malfunction of a non-selected magnetoresistive element and a manufacturing method of this semiconductor device. The semiconductor device includes a magnetic storage element having a magnetization free layer whose magnetization direction is made variable and formed over a lead interconnect and a digit line located below the magnetic storage element, extending in a first direction, and capable of changing the magnetization state of the magnetization free layer by the magnetic field generated. The digit line includes an interconnect body portion and a cladding layer covering therewith the bottom surface and the side surface of the interconnect body portion and opened upward. The cladding layer includes a sidewall portion covering therewith the side surface of the interconnect body portion and a bottom wall portion covering therewith the bottom surface of the interconnect body portion.

Abstract: The present invention discloses a semiconductor PN junction structure and a manufacturing method thereof. From top view, the PN junction includes a staggered comb-teeth structure. The PN junction forms a depletion region with enhanced breakdown voltage, hence broadening the applications of a semiconductor device having such PN junction.

Abstract: An embodiment of the invention relates to a Seebeck temperature difference sensor that may be formed in a trench on a semiconductor device. A portion of the sensor may be substantially surrounded by an electrically conductive shield. A plurality of junctions may be included to provide a higher Seebeck sensor voltage. The shield may be electrically coupled to a local potential, or left electrically floating. A portion of the shield may be formed as a doped well in the semiconductor substrate on which the semiconductor device is formed, or as a metal layer substantially covering the sensor. The shield may be formed as a first oxide layer on a sensor trench wall with a conductive shield formed on the first oxide layer, and a second oxide layer formed on the conductive shield. An absolute temperature sensor may be coupled in series with the Seebeck temperature difference sensor.

Abstract: A storage node of a magnetic memory device includes: a lower magnetic layer, a tunnel barrier layer formed on the lower magnetic layer, and a free magnetic layer formed on the tunnel barrier. The free magnetic layer has a magnetization direction that is switchable in response to a spin current. The free magnetic layer has a cap structure surrounding at least one material layer on which the free magnetic layer is formed.

Abstract: A method and apparatus for a flash memory is provided. A NAND flash memory array includes a cell body, a first selective gate, and a first edge line. The cell body includes recessed doped source/drain region between the first selective gate and the first edge word line.

Abstract: A method of packaging a pressure sensing die includes providing a lead frame with lead fingers and attaching the pressure sensing die to the lead fingers such that bond pads of the die are electrically coupled to the lead fingers and a void is formed between the die and the lead fingers. A gel material is dispensed via an underside of the lead frame into the void such that the gel material substantially fills the void. The gel material is then cured and the die and the lead frame are encapsulated with a mold compound. The finished package does not include a metal lid.

Abstract: Embodiments of the invention generally relate to optoelectronic semiconductor devices such as photovoltaic devices including solar cells. In one aspect, an optoelectronic semiconductor device includes an absorber layer made of gallium arsenide (GaAs) and having only one type of doping. An emitter layer is located closer than the absorber layer to a back side of the device, the emitter layer made of a different material than the absorber layer and having a higher bandgap than the absorber layer. A heterojunction formed between the emitter layer and the absorber layer, and a p-n junction is formed between the emitter layer and the absorber layer and at least partially within the different material at a location offset from the heterojunction. The p-n junction causes a voltage to be generated in the device in response to the device being exposed to light at a front side of the device.

Abstract: In an example embodiment, an optical device includes an integrated circuit, an array of conductive regions, and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region. In another example embodiment, a method of forming a nanocrystalline film includes fabricating nanocrystals having a plurality of first ligands attached to their outer surfaces, exchanging the first ligands for second ligands of a different chemical composition, forming a film of the ligand-exchanged nanocrystals, removing the second ligands, and fusing the cores of adjacent nanocrystals in the film to form an electrical network of fused nanocrystals. In another example embodiment, a film includes a network of fused nanocrystals with at least portions of the fused nanocrystals being in direct physical contact with adjacent nanocrystals, the film having substantially no defect states in regions where cores of the nanocrystals are fused.

Abstract: An integrated electronic device for detecting gases or biological molecules having a microchip comprising integrated electronics manufactured by the CMOS process. The microchip includes a passivation layer. The passivation layer includes one or more windows configured to cover at least one electronic circuit component of the microchip. The one or more windows leave one or more contacts free. The microchip further includes a sensitive covering coupled with said one or more contacts.

Abstract: Disclosed is a semiconductor device having a p-n junction with reduced junction leakage in the presence of metal silicide defects that extend to the junction and a method of forming the device. Specifically, a semiconductor layer having a p-n junction is formed. A metal silicide layer is formed on the semiconductor layer and a dopant is implanted into the metal silicide layer. An anneal process is performed causing the dopant to migrate toward the metal silicide-semiconductor layer interface such that the peak concentration of the dopant will be within a portion of the metal silicide layer bordering the metal silicide-semiconductor layer interface and encompassing the defects. As a result, the silicide to silicon contact is effectively engineered to increase the Schottky barrier height at the defect, which in turn drastically reduces any leakage that would otherwise occur, when the p-n junction is in reverse polarity.

Abstract: Embodiments related to semiconductor manufacturing and semiconductor devices with semiconductor structure are described and depicted.

Abstract: This wiring layer structure includes: an underlying substrate of a semiconductor substrate or a glass substrate; an oxygen-containing Cu layer or an oxygen-containing Cu alloy layer which is formed on the underlying substrate; an oxide layer containing at least one of Al, Zr, and Ti which is formed on the oxygen-containing Cu layer or the oxygen-containing Cu alloy layer; and a Cu alloy layer containing at least one of Al, Zr, and Ti which is formed on the oxide layer.

Abstract: Some embodiments include methods of forming diodes. A stack may be formed over a first conductive material. The stack may include, in ascending order, a sacrificial material, at least one dielectric material, and a second conductive material. Spacers may be formed along opposing sidewalls of the stack, and then an entirety of the sacrificial material may be removed to leave a gap between the first conductive material and the at least one dielectric material. In some embodiments of forming diodes, a layer may be formed over a first conductive material, with the layer containing supports interspersed in sacrificial material. At least one dielectric material may be formed over the layer, and a second conductive material may be formed over the at least one dielectric material. An entirety of the sacrificial material may then be removed.

Abstract: Disclosed is an asymmetric thermoelectric module, which includes a plurality of first-type thermoelectric semiconductor elements, a plurality of second-type thermoelectric semiconductor elements, a plurality of pairs of assistant layers having different melting points and disposed on the upper and lower surfaces of the first-type and second-type thermoelectric semiconductor elements, and a pair of substrates.

Abstract: An integrated circuit includes a Schottky diode having a cathode defined by an n-type semiconductor region, an anode defined by a cobalt silicide region, and a p-type region laterally annularly encircling the cobalt silicide region. The resulting p-n junction forms a depletion region under the Schottky junction that reduces leakage current through the Schottky diodes in reverse bias operation. An n+-type contact region is laterally separated by the p-type region from the first silicide region and a second cobalt silicide region is formed in the n-type contact region. The silicided regions are defined by openings in a silicon blocking dielectric layer. Dielectric material is left over the p-type region. The p-type region may be formed simultaneously with source/drain regions of a PMOS transistor.

Abstract: According to embodiments of the present invention, a light emitting device is provided. The light emitting device includes: an active region comprising at least one p-i-n junction, the at least one p-i-n junction comprising a p-doped region, an intrinsic region and an n-doped region; a first contact; and a second contact, wherein the active region is disposed between the first contact and the second contact; and wherein a voltage applied to the first contact and the second contact produces a current configured to flow between the first contact and the second contact in a direction substantially parallel to a surface of the intrinsic region of the active region configured to emit a light. According to embodiments of the present invention, the intrinsic region includes a multiple quantum well (MQW) such that a current injected flows laterally in a direction substantially parallel to the surface of the wells of the MQW.

Abstract: In an example embodiment, the method of manufacturing an image sensor includes forming an interlayer dielectric (ILD) on a substrate. The substrate may have a plurality of pixels arranged thereon and each of the pixels includes a photoelectric conversion device configured to sense external light and generate photo charges. Furthermore, the method may include forming a metal on the ILD and removing portions of the metal to form a reflection pattern. Additionally, the method may include removing the ILD to a depth to form a trench adjacent to the reflection pattern and forming an air gap in the trench by forming oxide over the substrate such that the reflection pattern and the upper portion of the trench are covered.

Abstract: A hetero pn junction semiconductor constituted of an electrically conductive polymer as a p-type semiconductor and an inorganic oxide as an n-type semiconductor, which is characterized in that the electrically conductive polymer is filled among nanoparticles of the inorganic oxide so as to satisfy the following Equation 1: Vp/Vn=X×?n/?p(0.

Abstract: A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator.

Abstract: A self-aligned top-gate thin film transistor and a fabrication method thereof. The method includes preparing a substrate having sequentially formed thereon an oxide semiconductor layer, a dielectric layer, and a metallic layer, wherein the oxide semiconductor layer includes first and second connecting regions that are not covered by the dielectric layer and the metallic layer thereon respectively, the first and second connecting regions having a property of a conductor after undergone a heating process or an ultraviolet irradiation; and a source electrode and a drain electrode formed on the substrate and connected to the first and second connecting regions, respectively. Therefore, the contact resistance of the first and second connecting regions can be reduced without the process of ion dopants as required by prior art techniques, thereby simplifying the manufacturing process. Also, the source electrode and the drain electrode can be exactly relocated and further increase performance of the device.

Abstract: Image sensors have photodiodes separated by isolations regions formed from p-well or n-well implants. Isolation regions may be formed that are narrow and deep. Isolation regions may be formed in a multi-step process that selectively places implants at desired depths in a substrate. Complementary photoresist patterns may be used. To form an implant near the surface of a substrate, a photoresist pattern with openings over the desired implant area may be used. Subsequent implantation may use a complementary pattern such that ions pass through photoresist before implanting in desired regions of a substrate.

Abstract: A method of manufacturing an integrated circuit (IC), comprising: defining a plurality of continuous active areas; forming conducting lines extending over the active areas; and using the conducting lines as a mask, introducing dopant into the active areas. Connections are provided between doped regions and conducting lines to form first and second circuit portions, at least one active area being continuous between those portions. In that active area, connections are provided between doped regions and conducting lines to form a pair of diode-connected transistors in reverse bias to one another between the first and second circuit portions, connected so as to leave a shared, unconnected doped region between the pair. The present invention also relates to a corresponding IC.

Abstract: A method of growing polygonal carbon from photoresist and resulting structures are disclosed. Embodiments of the invention provide a way to produce polygonal carbon, such as graphene, by energizing semiconductor photoresist. The polygonal carbon can then be used for conductive paths in a finished semiconductor device, to replace the channel layers in MOSFET devices on a silicon carbide base, or any other purpose for which graphene or graphene-like carbon material formed on a substrate is suited. In some embodiments, the photoresist layer forms both the polygonal carbon layer and an amorphous carbon layer over the polygonal carbon layer, and the amorphous carbon layer is removed to leave the polygonal carbon on the substrate.

Abstract: A method for detaching a first material layer from a second material layer includes following steps: forming a high-magnetic-permeability material layer on a first material layer comprised of low-magnetic-permeability material; removing a portion of the high-magnetic-permeability material layer to expose a portion of the first material layer; epitaxially growing a second material layer comprised of low-magnetic-permeability material on the exposed portion of the first material layer and the high-magnetic-permeability material layer; cooling the first and second material layers; heating the high-magnetic-permeability material layer, thus detaching the first material layer from the second material layer.

Abstract: An image sensor may include a first substrate having circuitry including wires and a silicon layer formed on and/or over the first substrate to selectively contact the wires. The image sensor may include photodiodes bonded to the first substrate while contacting the silicon layer and electrically connected to the wires. Each unit pixel may be implemented having complicated circuitry without a reduction in photosensitivity. Additional on-chip circuitry may also be implanted in the design.

Abstract: The present invention provides an energy converting device, which includes: a base substrate; and a plurality of thermoelectric element structures which are sequentially stacked on the base substrate and electrically interconnected in parallel to one another.

Abstract: A multi-layer superlattice quantum well thermoelectric material comprising at least 10 alternating layers has a layer thickness of each less than 50 nm, the alternating layers being electrically conducting and barrier layers, wherein the layer structure shows no discernible interdiffusion leading to a break-up or dissolution of the layer boundaries upon heat treatment at a temperature in the range from 50 to 150° C. for a time of at least 100 hours and the concentration of doping materials in the conducting layers is 1018 to 1023 cm?3 and in the barrier layers is 1013 to 1018 cm?3.

Abstract: A photoelectric conversion module including an electrolyte inlet allowing an electrolyte to be introduced to at least two neighboring photoelectric cells simultaneously, reducing the number of electrolyte inlets needed to fill photoelectric cells.

Abstract: A method for detaching a first material layer from a second material layer includes following steps: forming a high-magnetic-permeability material layer on a first material layer comprised of low-magnetic-permeability material; removing a portion of the high-magnetic-permeability material layer to expose a portion of the first material layer; epitaxially growing a second material layer comprised of low-magnetic-permeability material on the exposed portion of the first material layer and the high-magnetic-permeability material layer; cooling the first and second material layers; heating the high-magnetic-permeability material layer, thus detaching the first material layer from the second material layer.

Abstract: A method for fabricating a potential barrier for a nitrogen-face (N-face) nitride-based electronic device, comprising using a thickness and polarization induced electric field of a III-nitride interlayer, positioned between a first III-nitride layer and a second III-nitride layer, to shift, e.g., raise or lower, the first III-nitride layer's energy band with respect to the second III-nitride layer's energy band by a pre-determined amount. The first III-nitride layer and second III-nitride layer each have a higher or lower polarization coefficient than the III-nitride interlayer's polarization coefficient.