Abstract: A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes an epitaxy substrate, a nitride pillar layer, a nitride semiconductor layer, and a mask layer. The nitride pillar layer includes a plurality of first patterned arranged pillars and a plurality of second patterned arranged pillars. The nitride pillar layer is formed on the epitaxy substrate. A width of a cross-section of each of the second patterned arranged pillars is smaller than a width of a cross-section of each of the first patterned arranged pillars, and a distance among each of the second patterned arranged pillars is longer than a distance among each of the first patterned arranged pillars. Surfaces of the epitaxy substrate, the first patterned arranged pillars, and the second patterned arranged pillars are covered by the mask layer. The nitride semiconductor layer is formed on the nitride pillar layer.

Abstract: Provided is a biosensor which can detect a specific biomaterial by an interaction between target molecules and probe molecules, and a manufacturing method thereof. The biosensor includes: a first conductive semiconductor substrate; a second conductive doping layer formed on the semiconductor substrate; an electrode formed on top of both opposite ends of the doping layer; and probe molecules immobilized on the doping layer.

Abstract: A method can be adapted for design and preparation of a matrix nanocomposite sensing film for hydrogen sulphide SAW/BAW detection at room temperature. A matrix nanocomposite can be synthesized by incorporating both single-wall and multi-wall thiolated carbon nanotubes into conductive organic polymers or ceramic nanocrystalline in a properly functionalized manner. A thin organic sensing film can be prepared based on the matrix nanocomposite. The matrix nanocomposite sensing film can be prepared on a surface of a SAW/BAW device by an additive process or a direct printing process. Finally, the sensing film can be consolidated by thermal annealing or laser annealing under ambient conditions in order to obtain the stable sensing film with higher sensitivity and electrical properties for a SAW/BAW based H2S sensor.

Abstract: An electric organic component and a method for the production thereof is disclosed. The component includes a substrate, a first electrode, a first electrically semiconductive layer on the first electrode, an organic functional layer on the first electrically semiconductive layer and a second electrode on the organic functional layer. The first or the second electrode may be arranged on the substrate. The electrically semiconductive layer is doped with a dopant which comprises rhenium compounds.

Abstract: A phase controllable field effect transistor device is described. The device provides first and second scattering sites disposed at either side of a conducting channel region, the conducting region being gated such that on application of an appropriate signal to the gate, energies of the electrons in the channel region defined between the scattering centres may be modulated.

Abstract: A transistor-type protection device includes: a semiconductor substrate; a well including a first-conductivity-type semiconductor formed in the semiconductor substrate; a source region including a second-conductivity-type semiconductor formed in the well; a gate electrode formed above the well via a gate insulating film at one side of the source region; a drain region including the second-conductivity-type semiconductor formed within the well apart at one side of the gate electrode; and a resistive breakdown region including a second-conductivity-type semiconductor region in contact with the drain region at a predetermined distance apart from the well part immediately below the gate electrode, wherein a metallurgical junction form and a impurity concentration profile of the resistive breakdown region are determined so that a region not depleted at application of a drain bias when junction breakdown occurs in the drain region or the resistive breakdown region may remain in the resistive breakdown region.

Abstract: A semiconductor electronic device comprises a substrate; a buffer layer formed on said substrate, having two or more layers of composite layers in which a first semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and greater coefficient of thermal expansion than the substrate and a second semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and greater coefficient of thermal expansion than the first semiconductor layer are alternately laminated; a semiconductor operating layer comprising nitride based compound semiconductor formed on said buffer layer; a dislocation reducing layer comprising nitride based compound semiconductor, formed in a location between a location directly under said buffer layer and inner area of said semiconductor operating layer, and comprising a lower layer area and an upper layer area each having an uneven boundary surface, wherein threading dislocation extending from the lower layer area t

Abstract: A method for fabricating an RRAM is provided. First, a bottom electrode is formed. A resistive layer is formed on the bottom electrode. A top electrode is then formed on the resistive layer, wherein the top electrode is selected from the group consisting of indium tin oxide (ITO) and indium zinc oxide (IZO). Finally, the top electrode is irradiated with UV light.

Abstract: A detector device comprises a substrate (50), a source region (S) and a drain region (D), and a channel region (65) between the source and drain regions. A nanopore (54) passes through the channel region, and connects fluid chambers (56,58) on opposite sides of the substrate. A voltage bias is provided between the fluid chambers, the source and drain regions and a charge flow between the source and drain regions is sensed. The device uses a nanopore for the confinement of a sample under test (for example nucleotides) close to a sensor. The size of the sensor can be made similar to the spacing of adjacent nucleotides in a DNA strand. In this way, the disadvantages of PCR based techniques for DNA sequencing are avoided, and single nucleotide resolution can be attained.

Abstract: A method for manufacturing a photoelectric conversion device typified by a solar cell, having an excellent photoelectric conversion characteristic with a silicon semiconductor material effectively utilized. The point is that the surface of a single crystal semiconductor layer bonded to a supporting substrate is irradiated with a pulsed laser beam to become rough. The single crystal semiconductor layer is irradiated with the pulsed laser beam in an atmosphere containing an inert gas and oxygen so that the surface thereof is made rough. With the roughness of surface of the single crystal semiconductor layer, light reflection is suppressed so that incident light can be trapped. Accordingly, even when the thickness of the single crystal semiconductor layer is equal to or greater than 0.1 ?m and equal to or less than 10 ?m, path length of incident light is substantially increased so that the amount of light absorption can be increased.

Abstract: A semiconductor device is provided which includes a semiconductor substrate, a transistor formed on the substrate, the transistor having a gate stack including a metal gate and high-k gate dielectric and a dual first contact formed on the substrate. The dual first contact includes a first contact feature, a second contact feature overlying the first contact feature, and a metal barrier formed on sidewalls and bottom of the second contact feature, the metal barrier layer coupling the first contact feature to the second contact feature.

Abstract: A method for fabricating a component is disclosed. The method includes: providing a member having an effective work function of an initial value, disposing a sacrificial layer on a surface of the member, disposing a first agent within the member to obtain a predetermined concentration of the agent at said surface of the member, annealing the member, and removing the sacrificial layer to expose said surface of the member, wherein said surface has a post-process effective work function that is different from the initial value.

Abstract: An electronic device comprises a body including a single crystal region on a major surface of the body. The single crystal region has a hexagonal crystal lattice that is substantially lattice-matched to graphene, and a at least one epitaxial layer of graphene is disposed on the single crystal region. In a currently preferred embodiment, the single crystal region comprises multilayered hexagonal BN. A method of making such an electronic device comprises the steps of: (a) providing a body including a single crystal region on a major surface of the body. The single crystal region has a hexagonal crystal lattice that is substantially lattice-matched to graphene, and (b) epitaxially forming a at least one graphene layer on that region. In a currently preferred embodiment, step (a) further includes the steps of (a1) providing a single crystal substrate of graphite and (a2) epitaxially forming multilayered single crystal hexagonal BN on the substrate.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. In semiconductor devices of the conventional technologies, the chip size is increased when a breakdown voltage is increased. In the semiconductor device of this invention, an end of a pn junction interface (5) of a collector region (2) and a base region (3) is formed of a mesa groove (6) made of a trench. Thus, the chip size is not increased even when the mesa groove (6) is deeply formed to increase the breakdown voltage.

Abstract: Group III (Al, Ga, In)N single crystals, articles and films useful for producing optoelectronic devices (such as light emitting diodes (LEDs), laser diodes (LDs) and photodetectors) and electronic devices (such as high electron mobility transistors (HEMTs)) composed of III-V nitride compounds, and methods for fabricating such crystals, articles and films.

Abstract: Provided are a silicon nitride layer for a light emitting device, light emitting device using the same, and method of forming the silicon nitride layer for the light emitting device. The silicon nitride layer of the light emitting device includes a silicon nitride matrix and silicon nanocrystals formed in the silicon nitride matrix. A light emitting device manufactured by the silicon nitride layer has a good luminous efficiency and emits light in the visible region including the short-wavelength blue/violet region and the near infrared region.

Abstract: A power semiconductor device that realizes high-speed turnoff and soft switching at the same time has an n-type main semiconductor layer that includes lightly doped n-type semiconductor layers and extremely lightly doped n-type semiconductor layers arranged alternately and repeatedly between a p-type channel layer and an n+-type field stop layer, in a direction parallel to the first major surface of the n-type main semiconductor layer. A substrate used for manufacturing the semiconductor device is fabricated by forming trenches in an n-type main semiconductor layer 1 and performing ion implantation and subsequent heat treatment to form an n+-type field stop layer in the bottom of the trenches. The trenches are then filled with a semiconductor doped more lightly than the n-type main semiconductor layer for forming extremely lightly doped n-type semiconductor layers. The manufacturing method is applicable with variations to various power semiconductor devices such as IGBT's, MOSFET's and PIN diodes.

Abstract: A laser amplification structure comprising an active medium and at least two electrodes disposed on either side of the active medium, the active medium comprising a first layer of a silicon oxide doped with rare earth ions, wherein the first silicon layer is co-doped with silicon nanograins and rare earth ions.

Abstract: Field effect semiconductor diodes and improved processing techniques for forming the field effect semiconductor diodes having semiconductor layers forming a source, a body and a drain of a field effect device, the semiconductor layers forming pedestals having an insulating layer and a gate on sides thereof vertically spanning the body and a part of the source and drain layers, and a conductive contact layer over the pedestals making electrical contact with the drain and the gate, the conductive layer being in contact with the body at least one position on each pedestal. The conductive layer may be in contact with the body through at least one opening in the source layer, or the source layer may be a discontinuous doped layer, the body layer extending between the discontinuous doped layer forming the source layer to be in electrical contact with the conductive layer. Other aspects and variations of the invention are disclosed.

Abstract: The fabrication of integrated circuits comprising resistors having the same structure but different sheet resistances is disclosed herein. In one embodiment, a method of fabricating an integrated circuit comprises: concurrently forming a first resistor laterally spaced from a second resistor above or within a semiconductor substrate, the first and second resistors comprising a doped semiconductive material; depositing a dopant receiving material across the first and second resistors and the semiconductor substrate; removing the dopant receiving material from upon the first resistor while retaining the dopant receiving material upon the second resistor; and annealing the first and second resistors to cause a first sheet resistance of the first resistor to be different from a second sheet resistance of the second resistor.

Abstract: It is provided a hetero epitaxial growth method, a hetero epitaxial crystal structure, a hetero epitaxial growth apparatus and a semiconductor device, the method includes forming a buffer layer formed with the orienting film of an oxide, or the orienting film of nitride on a heterogeneous substrate; and performing crystal growth of a zinc oxide based semiconductor layer on the buffer layer using a halogenated group II metal and an oxygen material. It is provided a homo epitaxial growth method, a homo epitaxial crystal structure, a homo epitaxial growth apparatus and a semiconductor device, the homo epitaxial growth method includes introducing reactant gas mixing zinc containing gas and oxygen containing gas on a zinc oxide substrate; and performing crystal growth of a zinc oxide based semiconductor layer on the zinc oxide substrate.

Abstract: A thin film transistor, a method of manufacturing the thin film transistor, and a flat panel display device including the thin film transistor. The thin film transistor includes: a gate electrode formed on a substrate; a gate insulating film formed on the gate electrode; an activation layer formed on the gate insulating film; a passivation layer including a compound semiconductor oxide, formed on the activation layer; and source and drain electrodes that contact the activation layer.

Abstract: A transistor in which a physical property of its channel is changed according to an applied voltage, and methods of manufacturing and operating the same are provided. The transistor may include a first conductive layer on a substrate, a phase change layer and a second conductive layer which are sequentially stacked on the first conductive layer, a first current direction limiting unit and a second current direction limiting unit formed on the second conductive layer by being separated within a space, a third conductive layer and a fourth conductive layer formed on the first current direction limiting unit and the second current direction limiting unit, respectively, a word line connected to the third conductive layer, a bit line connected to the fourth conductive layer, and a voltage lowering unit connected to the word line.

Abstract: A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.

Abstract: Optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit an array of conductive regions; and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a method of forming a nanocrystalline film includes fabricating a plurality of nanocrystals having a plurality of first ligands attached to their outer surfaces; exchanging the first ligands for second ligands of different chemical composition than the first ligands; forming a film of the ligand-exchanged nanocrystals; removing the second ligands; and fusing the cores of adjacent nanocrystals in the film to form an electrical network of fused nanocrystals.

Abstract: Some embodiments include methods of forming diodes. The methods may include oxidation of an upper surface of a conductive electrode to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of an oxidizable material over a conductive electrode, and subsequent oxidation of the oxidizable material to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of a metal halide layer over a conductive electrode. Some embodiments include diodes that contain a metal halide layer between a pair of diode electrodes.

Abstract: A method of manufacturing a semiconductor device, includes: forming a first and a second trench regions adjacent from each other in a first conductivity type semiconductor base; forming a second conductivity type semiconductor region in the semiconductor base between the first and second trench regions; forming a mask on the second conductivity type semiconductor region, the mask covering a central portion between the first and second trench regions; performing ion implantation of a first conductivity type impurity in the second conductivity type semiconductor region with the mask to form a first conductivity type first region and a first conductivity type second region separated from the first conductivity type first region; and performing heat treatment to diffuse the impurity in the first and second regions and to form a connection region between the first and second regions, connection region being shallower than the first and second regions after the heat treatment.

Abstract: A method of making a sensor comprises substantially laterally growing at least one nanowire having at least two segments between two electrodes, whereby a junction or connection is formed between the at least two segments; and establishing a sensing material adjacent to the junction or connection, and adjacent to at least a portion of each of the at least two segments, wherein the sensing material has at least two states.

Abstract: A semiconductor light emitting device has an n-type layer, a p-type layer, and a light-emitting active layer arranged between the p-type layer and the n-type layer, the active layer having alternating regions of doped and undoped materials. A double heterojunction light emitting device has a bulk active layer having doped portions alternating with undoped portions. A method of manufacturing a light emitting device includes forming a first layer arranged on a substrate, growing an active layer, selectively adding impurities at predetermined times during the growing of the active layer, and forming a second layer arranged on the active layer.

Abstract: A molecular single electron transistor (MSET) detector device (14) is described that comprises at least one organic molecule (87) connecting a drain electrode (84) and a source electrode (82). In use, said at least one organic molecule (87) provides a quantum confinement region. At least one analyte receptor site (90, 92) is provided in the vicinity of said at least one organic molecule (87) that bind molecules of interest (analytes). A fluid analyser (2) is also described that includes the MSET detector, a pre-concentrator (4) and a fluid gating structure (6). The fluid gating structure (6) is arranged to selectively route fluid from the pre-concentrator (4) to either one of the detector (14) and an exhaust port (12). The pre-concentrator (4), fluid gating structure (6) and detector (14) are each formed as substantially planar layers and arranged in a stack or cube.

Abstract: A semiconductor device and a method for forming it are described. The semoiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.

Abstract: A single chip wireless sensor (1) comprises a microcontroller (2) connected by a transmit/receive interface (3) to a wireless antenna (4). The microcontroller (2) is also connected to an 8 kB RAM (5), a USB interface (6), an RS232 interface (8), 64 kB flash memory (9), and a 32 kHz crystal (10). The device (1) senses humidity and temperature, and a humidity sensor (11) is connected by an 18 bit ?? A-to-D converter (12) to the microcontroller (2) and a temperature sensor (13) is connected by a 12 bit SAR A-to-D converter (14) to the microcontroller (2). The device (1) is an integrated chip manufactured in a single process in which both the electronics and sensor components are manufactured using standard CMOS processing techniques, applied to achieve both electronic and sensing components in an integrated process.

Abstract: A semiconductor device and a fabrication method for the semiconductor device which can remove the sacrifice layer deposited on the semiconductor device surface in a short time and whose manufacturing yield can be improved are provided. The semiconductor device and the fabrication method for the semiconductor device includes a field effect transistor 4 including a gate electrode 1, a drain electrode 2, and a source electrode 3 formed on a semiconductor substrate; and a hollow protective film 5 for covering the gate electrode 1, the drain electrode 2, and the source electrode 3, and being provided on the semiconductor substrate 4A.

Abstract: An mold having a sub-micron, or even nano, structure is fabricated. The mold is a porous aluminum oxide mold. With the mold, a sub-micron pattern is easily imprinted on a large surface of a substrate or a LED. No expensive equipment is necessary. The fabricating process is fast and cheap and thus meets the needs of producers.

Abstract: A display substrate includes a gate wiring, a data wiring, a switching element, an organic layer, and a pixel electrode. The gate wiring contacts a first transparent conductive layer formed on the gate wiring. The data wiring crosses the gate wiring. The data wiring contacts a second transparent conductive layer formed on the data wiring. The switching element is connected to the gate and data wirings. The organic layer is formed on a base substrate having the switching element formed thereon. The organic layer has first and second trenches corresponding to the first and second transparent conductive layers, respectively. The pixel electrode is formed in a pixel area of the organic layer.

Abstract: An array of pixels is formed using a substrate, where each pixel has a substrate having a backside and a frontside that includes metalization layers, a photodiode formed in the substrate, frontside P-wells formed using frontside processing that are adjacent to the photosensitive region, and an N-type region formed in the substrate below the photodiode. The N-type region is formed in a region of the substrate below the photodiode and is formed at least in part in a region of the substrate that is deeper than the depth of the frontside P-wells.

Abstract: An active matrix substrate according to one aspect of the present invention is a TFT array substrate including a TFT. The active matrix substrate includes a gate signal line electrically connected to a gate electrode of the TFT, a first insulating film formed above the gate signal line, an auxiliary capacitance electrode formed above the first insulating film and supplied with a common potential, a second insulating film formed above the auxiliary capacitance electrode, a source signal line formed above the second insulating film and electrically connected to a source electrode of the TFT, a third insulating film formed above the source signal line, and a pixel electrode formed above the third insulating film so that the pixel electrode overlaps with a part of the auxiliary capacitance electrode.

Abstract: A semiconductor device having a source electrode and a drain electrode formed over a semiconductor substrate, a gate electrode formed over the semiconductor substrate and disposed between the source electrode and the drain electrode, a protection film made of an insulating material and formed between the source electrode and the gate electrode and between the drain electrode and the gate electrode, and a gate side opening formed at least in one of a portion of the protection film between the source electrode and the gate electrode and a portion of the protection film between the drain electrode and the gate electrode and disposed away from all of the gate electrode, the source electrode and the drain electrode.

Abstract: A light-emitting diode includes a sapphire substrate, an n-type semiconductor, a light-emitting layer, a p-type semiconductor layer, an anode and a conductive material. The n-type semiconductor layer is formed on the sapphire substrate and has a side surface, a center section and an edge around the center portion. The light-emitting layer is formed on the n-type semiconductor layer. The p-type semiconductor layer is formed on the light-emitting layer. The anode is formed on the p-type semiconductor layer. The conductive material is formed on the bottom surface of the sapphire substrate and is in contact with the n-type semiconductor layer.

Abstract: A method of fabricating a semiconductor device for reducing a thermal burden on impurity regions of a peripheral circuit region includes preparing a substrate including a cell active region in a cell array region and peripheral active regions in a peripheral circuit region. A cell gate pattern and peripheral gate patterns may be formed on the cell active region and the peripheral active regions. First cell impurity regions may be formed in the cell active region. A first insulating layer and a sacrificial insulating layer may be formed to surround the cell gate pattern and the peripheral gate patterns. Cell conductive pads may be formed in the first insulating layer to electrically connect the first cell impurity regions. The sacrificial insulating layer may be removed adjacent to the peripheral gate patterns. First and second peripheral impurity regions may be sequentially formed in the peripheral active regions adjacent to the peripheral gate patterns.

Abstract: A method of manufacturing a semiconductor device, includes: forming a first and a second trench regions adjacent from each other in a first conductivity type semiconductor base; forming a second conductivity type semiconductor region in the semiconductor base between the first and second trench regions; forming a mask on the second conductivity type semiconductor region, the mask covering a central portion between the first and second trench regions; performing ion implantation of a first conductivity type impurity in the second conductivity type semiconductor region with the mask to form a first conductivity type first region and a first conductivity type second region separated from the first conductivity type first region; and performing heat treatment to diffuse the impurity in the first and second regions and to form a connection region between the first and second regions, connection region being shallower than the first and second regions after the heat treatment.

Abstract: The invention relates to a method for producing a layer structure in an electronic device, especially in an organic light emitting device, the method comprising a step of producing the layer structure as a composite layer structure with free charge carriers generated by charge transfer between a first material and a second material, wherein the composite layer structure is provided as a stack of at least three non-mixed sub-layers made of the first material and the second material, respectively, wherein within the stack of the at least three non-mixed sub-layers each first material sub-layer is followed by an adjacent second material sub-layer and each second material sub-layer is followed by an adjacent first material sub-layer, and wherein the first material and the second material are selected to form a host-dopant material system for the electrical doping. The invention also relates to an electronic device.

Abstract: A power semiconductor component and a method for producing such a component. The component comprises a semiconductor base body having a first doping. A pn junction is formed in the base body by a contact region having a second doping with a first doping profile. A field ring structure has a second doping with a second doping profile. The contact region and the field ring structure are arranged at respectively assigned first and second partial areas of a first surface of the base body. Both extend into the base body, wherein the base body has, for the field ring structure, a trench-type cutout assigned to each respective field ring, the surface of said cutout following the contour of the assigned doping profile.

Abstract: An image sensor may include a first substrate having circuitry including wires and a silicon layer formed on and/or over the first substrate to selectively contact the wires. The image sensor may include photodiodes bonded to the first substrate while contacting the silicon layer and electrically connected to the wires. Each unit pixel may be implemented having complicated circuitry without a reduction in photosensitivity. Additional on-chip circuitry may also be implanted in the design.

Abstract: A manufacturing method of an image sensor includes forming lower electrodes over a semiconductor substrate having metal wires and an interlayer insulating film formed thereover; removing a photoresist polymer produced by the formation of the lower electrodes by performing a primary treatment using a first substance; and then removing an electrode polymer produced by the formation of the lower electrodes by performing a secondary treatment using a second substance.

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.

Abstract: A light-emitting device of Group III nitride-based semiconductor comprises a substrate, a first Group III nitride layer and a second Group III nitride layer. The substrate comprises a first surface and a plurality of convex portions protruding from the first surface. Each convex portion is surrounded by a part of the first surface. The first Group III nitride layer is jointly formed by lateral growth starting at top surfaces of the convex portions. The second Group III nitride layer is formed on the first surface, wherein a thickness of the second Group III nitride layer is less than a height of the convex portion. Moreover, the first Group III nitride layer and the second Group III nitride layer are made of a same material.

Abstract: A ferroelectric stacked-layer structure is fabricated by forming a first polycrystalline ferroelectric film on a polycrystalline or amorphous substrate, and after planarizing a surface of the first ferroelectric film, laminating on the first ferroelectric film a second thin ferroelectric film having the same crystalline structure as the first ferroelectric film. A field effect transistor or a ferroelectric capacitor includes the ferroelectric stacked-layer structure as a gate insulating film or a capacitor film.

Abstract: The present disclosure relates to increasing the external efficiency of light emitting diodes, and specifically to increasing the outcoupling of light from an organic light emitting diode utilizing a diffraction grating.

Abstract: The present invention describes a method including: providing a substrate; forming a buffer layer epitaxially over the substrate with a manufacture-friendly process; forming a bottom electrode epitaxially over the buffer layer; and forming a ferroelectric layer epitaxially over the bottom electrode.