Abstract: An optical semiconductor, includes a semiconductor substrate having a (100) principal surface, a waveguide mesa stripe formed on a first region of the semiconductor substrate, the waveguide mesa stripe guiding a light therethrough; a plurality of dummy mesa patterns formed on the semiconductor substrate in a second region at a forward side of the first region, and a semi-insulating buried semiconductor layer formed on the semiconductor substrate so as to cover the first and second regions continuously, the semi-insulating buried semiconductor layer filling a right side and a left side of the waveguide mesa stripe in the first region and a gap between the plurality of dummy mesa patterns in the second region.

Abstract: A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm.

Abstract: Embodiments of the invention provide a semiconductor device including a collector in an active region; a first and a second sub-collector, the first sub-collector being a heavily doped semiconductor material adjacent to the collector and the second sub-collector being a silicided sub-collector next to the first sub-collector; and a silicided reach-through in contact with the second sub-collector, wherein the first and second sub-collectors and the silicided reach-through provide a continuous conductive pathway for electrical charges collected by the collector from the active region. Embodiments of the invention also provide methods of fabricating the same.

Abstract: A process for manufacturing an interaction system of a microelectromechanical type for a storage medium, the interaction system provided with a supporting element and an interaction element carried by the supporting element, envisages the steps of: providing a wafer of semiconductor material having a substrate with a first type of conductivity (P) and a top surface; forming a first interaction region having a second type of conductivity (N), opposite to the first type of conductivity (P), in a surface portion of the substrate in the proximity of the top surface; and carrying out an electrochemical etch of the substrate starting from the top surface, the etching being selective with respect to the second type of conductivity (N), so as to remove the surface portion of the substrate and separate the first interaction region from the substrate, thus forming the supporting element.

Abstract: A heterojunction bipolar transistor structure with self-aligned sub-lithographic extrinsic base region including a self-aligned metal-semiconductor alloy and self-aligned metal contacts made to the base is disclosed. The lateral dimension of the extrinsic base region is defined by the footprint of a sacrificial spacer, and its thickness is controlled by selective epitaxy. A self-aligned semiconductor-metal alloy and self-aligned metal contacts are made to the extrinsic base using a method compatible with conventional silicon processing.

Abstract: A high voltage semiconductor device, such as a RESURF transistor, having improved properties, including reduced on state resistance. The device includes a semiconductor substrate; a source region and a drain region provided in the substrate; wherein the source region and the drain region are laterally spaced from each other; and a drift region in the substrate between the source region and the drain region. The drift region includes a structure having at least two spaced trench capacitors extending between the source region and the drain region; and further includes a stack having at least a first region of a first conductivity type, a second region of a second conductivity type, and a third region of the first conductivity type, wherein the stack extends between the source region and the drain region and between the at least first and second trench capacitors and in electrical connection to the first and second trench capacitors.

Abstract: A method for forming a semiconductor device includes forming a gate dielectric over a substrate, forming a metal electrode over the gate dielectric, forming a first sacrificial layer which includes polysilicon or a metal over the metal electrode, removing the first sacrificial layer, and forming a gate electrode contact over and coupled to the metal electrode.

Abstract: The invention is directed to a method for manufacturing a semiconductor. The method comprises steps of providing a substrate having a gate structure formed thereon and forming a source/drain extension region in the substrate adjacent to the gate structure. A spacer is formed on the sidewall of the gate structure and a source/drain region is formed in the substrate adjacent to the spacer but away from the gate structure. A bevel carbon implantation process is performed to implant a plurality carbon atoms into the substrate and a metal silicide layer is formed on the gate structure and the source/drain region.

Abstract: A method for making a semiconductor device is provided by (a) providing a substrate (203) having first (205) and second (207) gate structures thereon; (b) forming an underlayer (231) over the first and second gate structures; (c) removing the underlayer from the first gate structure; (d) forming a first stressor layer (216) over the first and second gate structures; and (e) selectively removing the first stressor layer from the second gate structure through the use of a first etch which is selective to the underlayer.

Abstract: A CMOS image sensor comprising an epitaxial layer formed on a semiconductor layer, a device isolating layer formed on the epitaxial layer in order to divide the isolating layer into an active region and a device isolating region, the active region including a photo diode region and a transistor region, a drive transistor including a gate electrode formed on the epitaxial layer and a gate spacer formed on both side walls of the gate electrode, a floating diffusion region formed on the epitaxial layer, a trench hole formed in the device isolating layer and epitaxial layer in an area between the photo diode region and the floating diffusion region, a poly wiring formed in the trench hole which extends from the gate electrode to the drive transistor, and an impurity diffusion region formed by ion implanting the epitaxial layer on the side of the gate spacer.

Abstract: An image sensor can include a gate insulation layer, a gate electrode, a photodiode, and a floating diffusion region. The gate insulation layer can be formed on and/or over a semiconductor substrate for a transfer transistor. The gate insulation layer includes a first gate insulation layer having a central opening and a second gate insulation layer formed on and/or over an uppermost surface of the first gate insulation layer including the opening. The gate electrode can be formed on and/or over the gate insulation layer. The photodiode can be formed in the semiconductor substrate at one side of the gate electrode so as to generate an optical charge. The floating diffusion region can be formed in the semiconductor at the other side of the gate electrode opposite to the photodiode. The floating diffusion region can be electrically connected to the photodiode through a channel so as to store the optical charge generated from the photodiode.

Abstract: A CMOS image sensor may include a gate electrode on a gate insulating layer in an active region of a semiconductor substrate; a photodiode region in the semiconductor substrate on one side of the gate electrode; a floating diffusion region in the semiconductor substrate on another side of the gate electrode; and a complementary impurity region in the semiconductor substrate on the other side of the gate electrode, overlapping with the floating diffusion region.

Abstract: According to one embodiment, a collector electrode including metal is used for a sink region for connecting an n+ type buried layer, so that the sink region can be narrowly formed. Further, an interval between a base region and the collector electrode can be reduced, thereby considerably decreasing the size of the transistor. Furthermore, collector resistance is reduced, so that the performance of the transistor can be improved.

Abstract: An image sensor includes a first photodiode formed in a semiconductor substrate at a depth reachable by red light, a second photodiode disposed on or over the first photodiode in the semiconductor substrate at a depth reachable by blue light, a third photodiode disposed adjacent to the second photodiode, a plug connected to the first photodiode, transistor structures on the semiconductor substrate and electrically connected with the first, second and third diodes, an insulating layer covering the transistor structures, and microlenses on the insulating layer.

Abstract: An image sensor and a method for manufacturing the same are provided. The image sensor includes a photodiode region, an insulation layer structure, a light leakage preventing unit, color filters, and microlenses. The photodiode region in a pixel area of a semiconductor substrate generates an electric signal corresponding to entered light. The photodiode region includes a first photodiode, a second photodiode, and a third photodiode. The insulation layer structure includes trenches corresponding to boundaries between the first to third photodiodes. The light leakage preventing unit is formed in the trenches between the photodiodes and prevents light from passing through the trenches. The color filters are formed on the insulation layer structure corresponding to the first to third photodiodes, and the microlenses are disposed on the color filter corresponding to each of the color filters.

Abstract: An active layer having a p-type quantum dot structure is disposed over a lower cladding layer made of semiconductor material of a first conductivity type. An upper cladding layer is disposed over the active layer. The upper cladding layer is made of semiconductor material, and includes a ridge portion and a cover portion. The ridge portion extends in one direction, and the cover portion covers the surface on both sides of the ridge portion. A capacitance reducing region is disposed on both sides of the ridge portion and reaching at least the lower surface of the cover portion. The capacitance reducing region has the first conductivity type or a higher resistivity than that of the ridge portion, and the ridge portion has a second conductivity type. If the lower cladding layer is an n-type, the capacitance reducing region reaches at least the upper surface of the lower cladding layer.

Abstract: Techniques for reducing contamination during ion implantation is disclosed. In one particular exemplary embodiment, the techniques may be realized by an apparatus for reducing contamination during ion implantation. The apparatus may comprise a platen to hold a workpiece for ion implantation by an ion beam. The apparatus may also comprise a mask, located in front of the platen, to block the ion beam and at least a portion of contamination ions from reaching a first portion of the workpiece during ion implantation of a second portion of the workpiece. The apparatus may further comprise a control mechanism, coupled to the platen, to reposition the workpiece to expose the first portion of the workpiece for ion implantation.

Abstract: Flash memory devices and methods for fabricating the same are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises the steps of fabricating a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack and a first impurity doped region is formed within the substrate underlying the trench. The trench is filled at least partially with a conductive material.

Abstract: A vertical type CMOS image sensor and a method of manufacturing the same including a P+-type red photodiode formed in a semiconductor substrate, a first silicon epilayer formed over the semiconductor substrate and including a P+-type green photodiode formed therein, a second silicon epilayer formed over the first silicon epilayer and including a P+-type blue photodiode formed therein; a first P+-type plug formed in the first silicon epilayer and electrically connected to the P+-type red photodiode, and a second P+-type plug in the second silicon epilayer which is electrically connected to the P+-type green photodiode.

Abstract: A method for manufacturing an image sensor that can include forming a pad electrode over a semiconductor substrate; forming a protective layer over the pad electrode; forming a via hole through the protective layer to expose a portion of the uppermost surface of the pad electrode; and then forming a gold layer over the exposed portion of the uppermost surface of the pad electrode.

Abstract: A method for fabricating a semiconductor device, such as a trench MOSFET device, is provided. The method includes: forming a hard mask on an upper surface of a semiconductor substrate; forming an opening in the hard mask to expose a portion of the semiconductor substrate; forming a trench in the semiconductor substrate by etching the semiconductor substrate using the hard mask as an etch mask; forming a gate insulating film on inner walls of the trench; forming a conductive film on the gate insulating film and at least a portion of the hard mask, the conductive film filling the trench; forming a patterned conductive film in the trench by etching the conductive film; removing the hard mask; and forming a gate electrode by polishing the patterned conductive film until an upper surface of the patterned conductive film aligns with the upper surface of the semiconductor substrate.

Abstract: The high-withstand voltage MOSFET comprises a trench portion formed at the high-withstand voltage active region on a semiconductor substrate, two polysilicon layers formed on the high-withstand voltage active region on both sides of the trench portion by implanting an impurity of the conductivity type opposite to the high-withstand voltage active region, two impurity diffusion drift layers formed on both sides of the trench portion by implanting an impurity of the conductivity type opposite to the high-withstand voltage active region in the surface of the high-withstand voltage active region under the polysilicon layers, and a gate electrode formed through a gate oxide film on bottom and side surfaces of the trench portion and end surfaces and upper surfaces of adjacent regions of the polysilicon layers close to the trench portion, and source and drain regions are formed in the two polysilicon layers excluding the adjacent regions covered with the gate electrode.

Abstract: Provided are a thin film transistor, a method of fabricating the thin film transistor, and an organic light emitting diode display device (OLED display device) including the thin film transistor having improved characteristics of the thin film transistor. The thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate; a gate insulating layer disposed on the semiconductor layer, and formed of a thermal oxide layer patterned to correspond to the semiconductor layer; a gate electrode disposed on the gate insulating layer, and disposed to correspond to a predetermined region of the semiconductor layer; an interlayer insulating layer disposed on an entire surface of the substrate; and source and drain electrodes electrically connected to the semiconductor layer.

Abstract: Light-emitting devices and/or systems are described. In some embodiments, light-emitting devices and/or systems can recycle at least some light generated by a light-generating region of the light-emitting device. In one embodiment, a light-emitting system comprises a light-emitting device including a light-generating region, a polarization manipulation region that alters a polarization state of at least some light from a first polarization state to a second polarization state, wherein the polarization manipulation region comprises a plurality of features, and a feedback element that returns, to the polarization manipulation region, at least some light having the first polarization state and outputs at least some light having the second polarization state, wherein the polarization manipulation region is disposed at least partially between the light-generating region and the feedback element.

Abstract: A flash memory device including a lower tunnel insulation layer on a substrate, an upper tunnel insulation layer on the lower tunnel insulation layer, and a P-type gate on the upper tunnel insulation layer, wherein the upper tunnel insulation layer includes an amorphous oxide layer.

Abstract: A semiconductor structure and its method of fabrication include multiple finFETs with different vertical dimensions for the semiconductor fins. An implant species is implanted in a bottom portion of selected semiconductor fins on which reduced vertical dimension is desired. The bottom portion of the selected semiconductor fins with implant species is etched selective to the semiconductor material without the implanted species, i.e., the semiconductor material in the top portion of the semiconductor fin and other semiconductor fins without the implanted species. FinFETs with the full vertical dimension fins and a high on-current and finFETs with reduced vertical dimension fins with a low on-current thus results on the same semiconductor substrate. By adjusting the depth of the implant species, the vertical dimension of the semiconductor fins may be adjusted in selected finFETs.

Abstract: A transistor comprises a gate (110) comprising a gate electrode (111) and a gate dielectric (112), an electrically insulating cap (120, 720) over the gate, and a source/drain contact (130) adjacent to the gate. The electrically insulating cap prevents electrical contact between the gate and the source/drain contact. In one embodiment, the electrically insulating cap is formed in a trench (160, 660) that is self-aligned to the gate and that is created by the removal of a sacrificial cap using an aqueous solution comprising a carboxylic acid and a corrosion inhibitor.

Abstract: A semiconductor substrate including a plurality of insulating elements formed of an insulating material in the substrate, a semiconductor device having the same, and methods of manufacturing the substrate and the device are provided. The semiconductor device includes isolation regions formed in a semiconductor substrate, transistors formed on the semiconductor substrate, source/drain regions formed between the transistors and the isolation regions in the semiconductor substrate, and a plurality of the elements formed of insulating material being formed within the semiconductor substrate a predetermined distance beneath a top surface of the substrate.

Abstract: A semiconductor process is provided. The semiconductor process includes providing a substrate. Then, a surface treatment is performed to the substrate to form a buffer layer on the substrate. Next, a first pre-amorphous implantation is performed to the substrate.

Abstract: A semiconductor device and a method for forming it are described. The semoiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.

Abstract: A semiconductor device includes a substrate having a trench, a liner layer pattern on sidewalls and a bottom surface of the trench, the liner layer pattern including a first oxide layer pattern and a second oxide layer pattern, a diffusion blocking layer pattern on the liner layer pattern, and an isolation layer pattern in the trench on the diffusion blocking layer pattern.

Abstract: Disclosed herein are improved fin-type field effect transistor (FinFET) structures and the associated methods of manufacturing the structures. In one embodiment FinFET drive current is optimized by configuring the FinFET asymmetrically to decrease fin resistance between the gate and the source region and to decrease capacitance between the gate and the drain region. In another embodiment device destruction at high voltages is prevented by ballasting the FinFET. Specifically, resistance is optimized in the fin between the gate and both the source and drain regions (e.g., by increasing fin length, by blocking source/drain implant from the fin, and by blocking silicide formation on the top surface of the fin) so that the FinFET is operable at a predetermined maximum voltage.

Abstract: A method of manufacturing a semiconductor device, in which a stress film having a large stress can be formed with high accuracy over a transistor. The method comprises the steps of: depositing a tensile stress film over the whole surface of a substrate having formed thereon an n-MOSFET; removing by etching the deposited stress film while leaving it on the n-MOSFET; and performing UV irradiation to the remaining stress film. By the UV irradiation, a tensile stress of the stress film is improved. Further, although the stress film is cured by the UV irradiation, occurrence of etching defects caused by the curing is prevented because the UV irradiation is performed after the etching. Thus, speeding-up and high quality of the n-MOSFET can be attained.

Abstract: Novel nanodot and nanowire based MOSFET device structures and their fabrication processes are invented. These devices can be fabricated with the processes that do not need the extremely high lithographic resolution. The MOSFET devices remain functional even the nanodots and nanowires with varying sizes are randomly distributed. The activated number of nanodots and its total effective channel length/width are affected by the polished thickness of the insulation material in the CMP process. Therefore it is important to have a highly accurate control of CMP polishing rate to ensure a reliable process.

Abstract: The present invention offers the semiconductor device which can solve each problem, such as Fermi level pinning, formation of gate electrode depletion, and a diffusion phenomenon, can adopt a material suitable for each gate electrode of the MOS structure from which threshold voltage differs, and can adjust (control) threshold voltage appropriately by the manufacturing process simplified more and which has a MOS structure. In the semiconductor device which has a MOS structure concerning the present invention, a PMOS transistor has the structure in which the gate insulating film, first metal layer, second metal layer, and polysilicon layer was formed in the order concerned. An NMOS transistor has the structure by which a gate insulating film and polysilicon were formed in the order concerned.

Abstract: A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming an intergate dielectric layer over the nanodots, where the intergate dielectric layer encases the nanodots. To form sidewalls of the memory cell, a portion of the intergate dielectric layer is removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the intergate dielectric layer and the nanodots can be removed with an etch selective to the intergate dielectric layer.

Abstract: A transistor with a carbon nanotube channel and a method of manufacturing the same. At least two gate electrodes are formed on a gate insulating layer formed on a carbon nanotube channel and are insulated from each other. Thus, the minority carrier may be reduced or prevented from flowing into the carbon nanotube channel. Accordingly, it is possible to reduce or prevent a leakage current that is generated when both the majority carrier and the minority carrier flow into the carbon nanotube channel. Therefore, characteristics of the transistor may not be degraded due to the leakage current.

Abstract: A method for fabricating a pixel structure of an OELD includes the following steps. First, a first gate, a scan line and a second gate are formed on a substrate. Next, a gate insulation layer is formed on the substrate to cover the first gate, the scan line and the second gate. Then, on the gate insulation layer, a first channel layer and a second first channel layer are formed, which are located over the first gate and the second gate, respectively. Afterwards, a first source and a first drain beside the first channel layer and a data line are formed; meanwhile, a second source and a second drain beside the second channel layer, and a cathode electrically connected to the second drain are formed. Further, an organic functional layer is formed on the cathode. Finally, an anode is formed on the organic functional layer.

Abstract: A semiconductor device includes a substrate (20), a source region (58) formed over the substrate, a drain region (62) formed over the substrate, a first gate electrode (36) over the substrate adjacent to the source region and between the source and drain regions, and a second gate electrode (38) over the substrate adjacent to the drain region and between the source and drain regions.

Abstract: A field effect transistor (FET) device includes a bulk substrate, a gate insulating layer formed over the bulk substrate, source and drain regions formed in an active device area associated with the bulk substrate, the source and drain regions each defining a p/n junction with respect to a body region of the active device area, and a conductive plug formed within a cavity defined in the source region, across the p/n junction of the source region and into the body region, wherein the conductive plug facilitates a discharge path between the body region and the source region.

Abstract: Quantum well charge trap transistors are disclosed featuring an ion implanted region below a stack of high-low-high bandgap materials arranged in a sandwich structure. Source and drain electrodes on either side of implanted region, as well as a control gate above the stack allow for electrical control. The implanted region, functioning to provide an offset to the threshold for conduction, is less than feature size F using a technique with spacer masks created for implantation, then removed. The quantum well charge trap stack is built in the area where the spacers were removed with a polysilicon gate atop the stack. Edges of the polysilicon gate are used for self-aligned placement of source and drain.

Abstract: Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits.

Abstract: A CMOS image sensor array and method of fabrication. The CMOS imager sensor array comprises a substrate; an array of light receiving pixel structures formed above the substrate, the array having formed therein “m” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer; a dense logic wiring region formed adjacent to the array of light receiving pixel structures having “n” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer, where n>m. A microlens array having microlenses and color filters formed above the interlevel dielectric material layer, a microlens and respective color filter in alignment with a respective light receiving structure formed at a surface of the substrate. A top surface of the interlevel dielectric material layer beneath the microlens array is recessed from a top surface of the interlevel dielectric material layers of the dense logic wiring region.

Abstract: An improved coupling stability between the source region and the source electrode of the transistor is achieved. In the method for manufacturing the MOSFET, the p-type base region is formed in a semiconductor layer, and after the p-type base region is formed in the surface portion of the n+ type source region, the higher concentration source region extending from the side edge of the n+ type source region to the lateral side of the n+ type source region is formed in the surface portion of the p-type base region. Then, the source electrode coupled to the higher concentration source region is formed. This allows providing an improved coupling stability between the source electrode and the source region when a misalignment is occurred in the location for forming the source electrode during the formation of the source electrode to be coupled to the first source region.

Abstract: The present invention allows the growth of InGaN with greater compositions of Indium than traditionally available now, which pushes LED and LD wavelengths into the yellow and red portions of the color spectrum. The ability to grow with Indium at higher temperatures leads to a higher quality AlInGaN. This also allows for novel polarization-based band structure designs to create more efficient devices. Additionally, it allows the fabrication of p-GaN layers with increased conductivity, which improves device performance.

Abstract: An electronic device can include a first transistor having a first channel region further including a heterojunction region that, in one aspect, is at most approximately 5 nm thick. In another aspect, the first transistor can include a p-channel transistor including a gate electrode having a work function mismatched with the associated channel region, and the heterojunction region can lie along a surface of a semiconductor layer closer to a substrate than an opposing surface of the substrate. The electronic device can also include an n-channel transistor, and the subthreshold carrier depth of the p-channel and n-channel transistors can have approximately a same value as compared to each other. A process of forming the electronic device can include forming a compound semiconductor layer having an energy band gap greater than approximately 1.2 eV.

Abstract: Disclosed relates to a ferroelectric memory device that is manufactured easily, operates at low voltage and has excellent data preservation period, and a method of manufacturing the same. In the present invention, a ferroelectric layer (60) is formed on a part corresponding to a channel region (4) on the silicon substrate (1). The ferroelectric layer (60) made of an organic material such as PVDF, etc. shows polarization characteristics at low voltage below 1V, and such polarization characteristics continue over a specific time period, not changed as time goes by. Accordingly, it is possible to manufacture a ferroelectric memory device that operates at low voltage and is manufactured with a simplified structure in a simplified method.

Abstract: An image sensor and a method of forming the same includes a semiconductor substrate including a light receiving area and an optical black area defined by a boundary between them; photodiodes in at least one of the light receiving area and the optical black area of the semiconductor substrate; an interlayer dielectric provided on the semiconductor substrate; an upper light shielding pattern on the interlayer dielectric to cover the optical black area; and a light shielding pattern provided in the interlayer dielectric proximal to the boundary between the optical black area and the light receiving area.

Abstract: Provided are a multiple reflection layer electrode, a compound semiconductor light emitting device having the same and methods of fabricating the same. The multiple reflection layer electrode may include a reflection layer on a p-type semiconductor layer, an APL (agglomeration protecting layer) on the reflection layer so as to prevent or retard agglomeration of the reflection layer, and a diffusion barrier between the reflection layer and the APL so as to retard diffusion of the APL.

Abstract: A method for improving sensitivity of backside illuminated image sensor. A substrate having a first conductivity type and a first potential. A depletion region having a second conductivity type is formed within the substrate. The depletion region is extended. The thickness of the substrate is reduced. First type conductivity ions having a second potential are implanted at backside surface of the substrate to form a doping layer. Laser annealing on the doping layer is performed to activate the first type conductivity ions.