Abstract: A method of making a FinFET device structure, includes: providing a semiconductor-on-insulator (SOI) substrate having a semiconductor layer on an insulating layer on a base (e.g., semiconductor) layer; forming a cap layer (e.g.

Abstract: A first exemplary aspect of an exemplary embodiment of the present invention is a semiconductor integrated device comprising a semiconductor substrate, a first impurity layer of a first conductivity type formed in the semiconductor substrate, a second impurity layer of a second conductivity type formed on the first impurity layer, a first well of the first conductivity type formed on the second impurity layer and supplied with potential from the first impurity layer via an impurity region of the first conductivity type selectively formed in a part of the second impurity layer, and a second well of the second conductivity type formed on the second impurity layer and supplied with potential from the second impurity layer, wherein the impurity concentrations of the first impurity layer and the impurity region are higher than that of the first well, and the impurity concentration of the second impurity layer is higher than that of the second well.

Abstract: Carbon nanotube, method for positioning the same, field effect transistor made using the carbon nanotube, method for making the field-effect transistor, and a semiconductor device are provided. The carbon nanotube includes a bare carbon nanotube and a functional group introduced to at least one end of the bare carbon nanotube.

Abstract: The present invention relates to a method of forming an ohmic electrode in a semiconductor light emitting element, comprising: forming a semiconductor layer having a light emitting structure on a substrate, sequentially laminating a bonding layer, a reflective layer and a protective layer on the semiconductor layer, and forming an ohmic electrode by performing a heat treatment process to form ohmic bonding between the semiconductor layer and the bonding layer and to form an oxide film on at least a portion of the protective layer; and a semiconductor light emitting element using the ohmic electrode. According to the present invention, since a reflective layer is formed of Ag, Al and an alloy thereof with excellent light reflectivity, the light availability is enhanced. Further, since contact resistance between a semiconductor layer and a bonding layer is small, it is easy to apply large current for high power.

Abstract: A nonvolatile semiconductor memory device comprises a memory cell array of plural memory cells arranged in matrix. Each memory cell includes a first gate insulator layer formed on a semiconductor substrate, a floating gate formed on the semiconductor substrate with the first gate insulator layer interposed therebetween, a second gate insulator layer formed on the floating gate, and a control gate formed on the floating gate with the second gate insulator layer interposed therebetween. The first gate insulator layer is a first cavity layer.

Abstract: A photoelectric element 10 includes a substrate 12 that transmits incident light, an intermediate layer 14 made of HfO2, an under layer 16, and a photoelectron emitting layer 18 containing an alkali metal. That is, the photoelectric element 10 includes the intermediate layer 14 formed between the substrate 12 and the photoelectron emitting layer 18. Thereby, a photoelectric element that can exhibit a high value of effective quantum efficiency, an electron tube including the same, and a method for producing a photoelectric element are realized.

Abstract: A transistor is defined to include a substrate portion and a diffusion region defined in the substrate portion so as to provide an operable transistor threshold voltage. An implant region is defined within a portion of the diffusion region so as to transform the operable transistor threshold voltage of the diffusion region portion into an inoperably high transistor threshold voltage. A gate electrode is defined to extend over both the diffusion region and the implant region. A first portion of the gate electrode defined over the diffusion region forms a first transistor segment having the operable transistor threshold voltage. A second portion of the gate electrode defined over the implant region forms a second transistor segment having the inoperably high transistor threshold voltage. Therefore, a boundary of the implant region defines a boundary of the operable first transistor segment.

Abstract: The collector resistance of a bipolar junction transistor that is formed in a CMOS process is substantially reduced by forming a heavily-doped collector extension region that extends from a heavily-doped collector contact region down to a deep well of the same conductivity type to a point that lies close to the base of the transistor.

Abstract: A photodiode structure including a semiconductor of a first conductivity type, the semiconductor having a main surface, a first well formed in the semiconductor at the main surface thereof, the first well being of a second conductivity type opposite to the first conductivity type. A second well formed in the semiconductor at the main surface thereof laterally outside the first well, the second well being of the second conductivity type, and a first terminal electrically connecting the first well and the second well, and a second terminal connecting the semiconductor such that a depletion region of laterally varying distance to the main surface results from applying a reverse voltage to the first and second terminals.

Abstract: A CMOS image sensor is formed utilizing a through-poly implantation process. First, a substrate including a photo-sensing region and a transistor region is provided. Subsequently, at least a gate structure is formed on a surface of the substrate within the transistor region. Thereafter, an ion implantation process is performed on the substrate to form a first conductive type well in the substrate through the gate structure. Since the ion implantation process implants ions into the substrate to a channel region of the transistor through the gate structure, the implant depth of the uncovered parts of the substrate is deeper than the implant depth of the parts of the substrate covered by the gate structure, and defects caused by the energy of the ion implantation process are prevented within the channel region.

Abstract: A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed over sides of the gate electrode and containing a halogen element. With this semiconductor device, a silicon nitride film which contains the halogen element is formed over the sides of the gate electrode when an SiGe layer is formed over the Si substrate. Therefore, the SiGe layer epitaxial-grows over the Si substrate with high selectivity. As a result, an OFF-state leakage current which flows between, for example, the gate electrode and source/drain regions is suppressed and a manufacturing process suitable for actual mass production is established.

Abstract: A method of forming a split gate memory device using a semiconductor layer includes patterning an insulating layer to leave a pillar thereof. A gate dielectric is formed over the semiconductor layer. A charge storage layer is formed over the gate dielectric and along first and second sides of the pillar. A gate material layer is formed over the gate dielectric and pillar. An etch is performed to leave a first portion of the gate material laterally adjacent to a first side of the pillar and over a first portion of the charge storage layer that is over the gate dielectric to function as a control gate of the memory device and a second portion of the gate material laterally adjacent to a second side of the pillar and over a second portion of the charge storage layer that is over the gate dielectric to function as a select gate.

Abstract: A light-emitting diode comprising AlnInmGa1-m-nNcAsvSbkP1-c-v-k where 0.001<c<0.1 and 0?n, m, v, k?1 adapted to emit light in a wavelength range of about 540 nm to about 700 nm.

Abstract: Embodiments of methods for improving electrical leakage performance and minimizing electromigration in semiconductor devices are generally described herein. Other embodiments may be described and claimed.

Abstract: Disclosed is a producing method of a semiconductor device, including: loading a silicon substrate into a processing chamber, the silicon substrate having a silicon nitride film or a silicon oxide film on at least a portion of a surface thereof and a silicon surface being exposed from the surface; and alternately repeating a first introducing at least a silane-compound gas into the processing chamber and a second introducing at least etching gas a plurality of times to selectively grow an epitaxial film on the silicon surface, wherein the alternate repeating is started with the second introducing prior to the first introducing.

Abstract: A method of manufacturing a semiconductor light emitting device employs a substrate formed by successively stacking an n-type semiconductor layered portion including an AlGaN layer, a light emitting layer containing In and a p-type semiconductor layered portion on a group III nitride semiconductor substrate having a larger lattice constant than AlGaN. This method includes the steps of selectively etching the substrate from the side of the p-type semiconductor layered portion along a cutting line to expose the AlGaN layer along the cutting line, forming a division guide groove along the cutting line on the exposed AlGaN layer, and dividing the substrate along the division guide groove.

Abstract: A nonvolatile memory device includes a semiconductor substrate, a charge-trap structure disposed on the semiconductor substrate, which includes an insulating film and a plurality of carbon nanocrystals embedded in the insulating film, and a gate disposed on the charge-trap structure. The nonvolatile memory device may exhibit memory hysteresis characteristics with improved reliability.

Abstract: A device comprises a plurality of fence layers of a semiconductor material and a plurality of alternating layers of quantum dots of a second semiconductor material embedded between and in direct contact with a third semiconductor material disposed in a stack between a p-type and n-type semiconductor material. Each quantum dot of the second semiconductor material and the third semiconductor material form a heterojunction having a type II band alignment. A method for fabricating such a device is also provided.

Abstract: This invention provides methods for fabricating substantially continuous layers of a group III nitride semiconductor material having low defect densities and optionally having a selected crystal polarity. The methods include epitaxial growth nucleating and/or seeding on the upper portions of a plurality of pillars/islands of a group III nitride material that are irregularly arranged on a template structure. The upper portions of the islands have low defect densities and optionally have a selected crystal polarity. The invention also includes template structures having a substantially continuous layer of a masking material through which emerge upper portions of the pillars/islands. The invention also includes such template structures. The invention can be applied to a wide range of semiconductor materials, both elemental semiconductors, e.g., combinations of Si (silicon) with strained Si (sSi) and/or Ge (germanium), and compound semiconductors, e.g.

Abstract: A method for fabricating a thin film transistor (TFT) is provided. A substrate having a gate, a dielectric layer, a channel layer and an ohmic contact layer formed thereon is provided. Next, a metal layer is formed over the substrate covering the ohmic contact layer. Next, the metal layer and the ohmic contact layer are simultaneously etched by a wet etching process to form a source/drain and expose the channel layer. Because the wet etching process can be used to selectively etch the ohmic contact layer, damage to the underlying channel layer may be negligible. Thus, the reliability of the device may be promoted. Furthermore, the process may be simplified, the production yield and the throughput of TFT may be increased.

Abstract: This bonded SOI substrate includes: an SOI layer having a low density impurity layer in which dopants are present at low density and a high density impurity layer in which dopants are present at high density; a wafer for a support substrate which supports said SOI layer; and a buried insulating film, wherein said SOI layer and said wafer for a support substrate are bonded with said buried insulating film therebetween, and gettering sites are formed in said high density impurity layer.

Abstract: Embodiments of the invention are related to micromachine structures. In one embodiment, a micromachine structure comprises a first electrode, a second electrode, and a sensing element. The sensing element is mechanically movable and is disposed intermediate the first and second electrodes and adapted to oscillate between the first and second electrodes. Further, the sensing element comprises a FinFET structure having a height and a width, the height being greater than the width.

Abstract: Semiconductor structures and methods are provided for a semiconductor device (54-11, 54-12) employing a superjunction structure (81). The method comprises, forming (52-6) first spaced-apart regions (70-1, 70-2, 70-3, 70-4, etc.) of a first semiconductor material (70) of a first conductivity type, forming (52-9) second spaced-apart regions (74-1, 74-2, 74-3, etc.) of a second semiconductor material (74) of opposite conductivity type interleaved with the first space-apart regions (70-1, 70-2, 70-3, 70-4, etc.) with PN junctions therebetween, thereby forming a superjunction structure, wherein the second regions have higher mobility than the first regions for the same carrier type. Other regions (88) are provided in contact with the superjunction structure (81) to direct control current flow therethrough. In a preferred embodiment, the first material (70) is relaxed SiGe and the second material (74) is strained silicon.

Abstract: A pinned photodiode, which is a double pinned photodiode having increased electron capacitance, and a method for forming the same are disclosed. The invention provides a pinned photodiode structure comprising a substrate base over which is a first layer of semiconductor material. There is a base layer of a first conductivity type, wherein the base layer of a first conductivity type is the substrate base or is a doped layer over the substrate base. At least one doped region of a second conductivity type is below the surface of said first layer, and extends to form a first junction with the base layer. A doped surface layer of a first conductivity type is over the at least one region of a second conductivity type and forms a second junction with said at least one region of a second conductivity type.

Abstract: The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more electrodes having a selectively conductive media between the electrodes forming individual cells, while utilizing a partitioning component to enable stacking of additional memory cells on top of or in association with previously formed cells. Memory stacks can be formed by adding additional layers—respective layers separated by additional partitioning components, wherein multiple stacks can be formed in parallel to provide a high-density memory device.

Abstract: A photodetector and method for making the same are disclosed. The photodetector includes a photodetector die mounted on a substrate, an infrared filter, and an encapsulating layer. The infrared filter is positioned over the photodetector, the infrared filter blocking light in an infrared region of the optical spectrum while allowing light in a visible region of the optical spectrum to reach the photodetector die. The encapsulating layer surrounds the photodetector and the substrate, the infrared filter being embedded in the encapsulating layer, which is transparent to light in the visible region.

Abstract: A method for fabricating an AMOLED pixel includes forming a transparent semiconductor layer on a substrate and forming a first channel layer of the switch TFT, a lower electrode of a storage capacitor and a second channel layer of a driving TFT. A first dielectric layer is formed over the substrate. A first opaque metal gate of the switch TFT, a second opaque metal gate of the driving TFT and a scan line are formed on the first dielectric layer. A first source and a first drain of the switch TFT are formed in the first channel layer and a second source and a second drain of the switch TFT are formed in the second channel layer. A patterned transparent metal layer is formed on the first dielectric layer. A data line is formed over the substrate. An OLED is formed over the substrate.

Abstract: An ultra high-resolution radiation detector and method for fabrication thereof, has a detector chip, comprising the so-called drift rings and an amplifier integrated with the diode component, centrally located n-type anode on one surface, the depletion region. The detector chip has a circular field of view, the depletion region which also has a circular field of view by ion implanting symmetrical p-n junctions on the surface of the radiation entrance side of the detector chip, said centrally n-type anode located on the opposite surface of the depletion region, and its position is in the region which outer of the depletion region, said centrally n-type anode was surrounded by a plurality of p-type drift electrode rings, which have an gibbous circularity topology; wherein the focus of said p-type drift electrode rings is the position of the anode, said FET (Field-Effect Transistor) was integrated in the position of the detector's anode and directly coupled to the detector's anode.

Abstract: A uniform silicon carbide single crystal with either an n-type or a p-type conductivity. The crystal has a net carrier concentration less than 1015 cm?3 and a carrier lifetime of at least 50 ns at room temperature.

Abstract: The invention relates to a microchip assembly that is particularly applicable for biosensors. According to the invention, short-distance interactions between coupling circuits (11, 12) on a thin substrate (13) and an object (2) take place through the substrate (13) of reduced thickness (d). The coupling circuits may particularly comprise wires (11) for the generation of a magnetic field (B) and a GMR (12) for the detection of the stray fields (B?) generated by magnetizing beads (2) on labeled biological molecules (1).

Abstract: A method of forming a split gate memory device using a semiconductor layer includes patterning an insulating layer to leave a pillar thereof. A gate dielectric is formed over the semiconductor layer. A charge storage layer is formed over the gate dielectric and along first and second sides of the pillar. A gate material layer is formed over the gate dielectric and pillar. An etch is performed to leave a first portion of the gate material laterally adjacent to a first side of the pillar and over a first portion of the charge storage layer that is over the gate dielectric to function as a control gate of the memory device and a second portion of the gate material laterally adjacent to a second side of the pillar and over a second portion of the charge storage layer that is over the gate dielectric to function as a select gate.

Abstract: A single-photon avalanche detector is disclosed that is operable at wavelengths greater than 1000 nm and at operating speeds greater than 10 MHz. The single-photon avalanche detector comprises a thin-film resistor and avalanche photodiode that are monolithically integrated such that little or no additional capacitance is associated with the addition of the resistor.

Abstract: A pixel area for generating an image signal corresponding to incident light is formed on a semiconductor substrate. A light-shielding layer is formed on the semiconductor substrate around the pixel area. The light-shielding layer has a slit near the pixel area and shields the incident light. A passivation film is formed in the pixel area, on the light-shielding layer, and in the slit. A coating layer is formed in the slit of the light-shielding layer and on the passivation film in the pixel area. Microlenses are formed on the coating layer in the pixel area.

Abstract: Provision of a process capable of preferably etching particularly PtMn used for a pin layer of an MRAM is an object: a dry etching method for performing dry etching on a layer including platinum and/or manganese by using pulse plasma and a production method of an MRAM, wherein the dry etching method is applied to processing of the pin layer. The MRAM is configured to have a memory portion comprising a magnetic memory element composed of tunnel magnetoresistive effect element formed by stacking a magnetic fixed layer having a fixed magnetization direction, a tunnel barrier layer and a magnetic layer capable of changing the magnetization direction.

Abstract: A photo detector is disclosed. The photo detector has a substrate, a semiconductor layer disposed on the substrate, an insulating layer covered on the semiconductor layer, an interlayer dielectric layer covered on the insulating layer, and two electrodes formed on a portion of the interlayer dielectric layer. The semiconductor layer has a first doping region, a second doping region, and an intrinsic region located between the first doping region and the second doping region. The interlayer dielectric layer has at least three holes to expose a portion of the insulating layer, a portion of the first doping region, and the second doping region. The electrodes are connected to the first doping region and the second doping region through two of the holes.

Abstract: The present invention relates to a flash memory device and its fabrication method, in more detail, it relates to a novel device structure for improving a scaling-down characteristic/performance and increasing memory capacity of the MOS-based flash memory device. A new device structure according to the present invention is compatible with existing fabrication process and is based on a recessed channel, which is capable of easily implementing highly-integrated/high-performance and 2-bit/cell. The proposed device has a structure suppressing the short channel effect while largely reducing the cell area and enabling 2-bit/cell by forming the charge storage node as a spacer inside the recessed channel. Moreover, if selectively removing the dielectric films around the recessed silicon surface, the sides as well as the surface of the recessed channel is exposed.

Abstract: A method for forming a thin film of a semiconductor device is provided. The method includes forming a TaN film on a semiconductor substrate, and converting a portion of the TaN film into a Ta film by reacting the TaN film with NO2. The Ta film is formed to have a thickness which is about half of the thickness of the TaN film.

Abstract: A semiconductor device which includes both an E-FET and a D-FET and can facilitate control of the Vth in an E-FET and suppress a decrease in the Vf, and a manufacturing method of the same are provided. A semiconductor device which includes both an E-FET and a D-FET on the same semiconductor substrate includes: a first threshold adjustment layer for adjusting threshold of the E-FET; a first etching stopper layer formed on the first threshold adjustment layer; the second threshold adjustment layer formed on the first etching stopper layer for adjusting threshold of the D-FET; a second etching stopper layer formed on the second threshold adjustment layer; a first gate electrode penetrating through the first etching stopper layer, the second threshold adjustment layer, and the second etching stopper layer, which is in contact with the first threshold adjustment layer; and the second gate electrode penetrating through the second etching stopper layer, which is in contact with the second threshold adjustment layer.

Abstract: A method for forming a semiconductor structure includes forming a gate dielectric layer over a substrate. A top surface of the gate dielectric layer is treated so as to at least partially nitridize the gate dielectric layer. The treated gate dielectric layer is thermally treated with an oxygen-containing precursor such that the at least partially nitridized gate dielectric layer has a nitrogen concentration between about 0.5 atomic percentage (at. %) and about 20 at %.

Abstract: A method for forming a thin film of a semiconductor device is provided. The method includes forming a TaN film on a semiconductor substrate by employing an atomic layer deposition method; and converting a part of the TaN film into a Ta by reacting the TaN film with NO2 to form a Ta film. The NO2 is formed by reacting NH3 with O2.

Abstract: In a memory cell area of a semiconductor device, first, second, and third inter-layer insulating films respectively cover a cell transistor, a bit wiring line, and a capacitor which are connected to each other. In an adjacent peripheral circuit area, a peripheral-circuit transistor is covered with the first inter-layer insulating film, a first-layer wiring line connected to the peripheral-circuit transistor is provided on the first inter-layer insulating film and covered with the second inter-layer insulating film, and a second-layer wiring line is provided on the third inter-layer insulating film. In the memory cell area, a landing pad is provided on the second inter-layer insulating film and between the capacitor and a contact plug for connecting the capacitor to the cell transistor. An assist wiring line connected to the first-layer wiring line is provided on the main surface of the second inter-layer insulating film, on which the landing pad is provided.

Abstract: An active matrix organic electroluminescent substrate includes a substrate having a controlling element region and a luminescent region, a thin film transistor, a first passivation layer, a conductive layer electrically connected to the thin film transistor, and a second passivation layer disposed on the first passivation layer and the conductive layer. The second passivation layer has an opening partially exposing the conductive layer, and a step-shaped structure located between the controlling element region and the luminescent region.

Abstract: In a method of fabricating a non-volatile memory device, a semiconductor substrate includes an isolation layer formed in an isolation region, a tunnel insulating layer and a first conductive layer for a floating gate formed in an active region, and a dielectric layer, a second conductive layer for a control gate, and a gate hard mask formed over the first conductive layer including the isolation layer. The second conductive layer is patterned using the gate hard mask as an etch mask. The dielectric layer is patterned so that the first conductive layer, which is exposed as the dielectric layer is etched, is also etched. The first conductive layer is patterned along a pattern of the gate hard mask. Accordingly, at the time of gate patterning, micro bridges between the floating gates can be prevented and a 2-bit failure between neighboring cells is less likely.

Abstract: A method for fabricating a hybrid orientation substrate includes steps of providing a direct silicon bonding (DSB) wafer having a first substrate with (100) crystalline orientation and a second substrate with (110) crystalline orientation directly bonded on the first substrate, forming and patterning a first blocking layer on the second substrate to define a first region not covered by the first blocking layer and a second region covered by the first blocking layer, performing an amorphization process to transform the first region of the second substrate into an amorphized region, and performing an annealing process to recrystallize the amorphized region into the orientation of the first substrate and to make the second region stressed by the first blocking layer.

Abstract: A method of making an inorganic light-emitting diode display having a plurality of light-emitting elements including providing a substrate, and forming a plurality of patterned electrodes over the substrate. A raised area is formed around each patterned electrode to provide a well before depositing a dispersion containing inorganic, light-emissive core/shell nano-particles into each well. The dispersion is dried to form a light-emitting layer including the inorganic, light-emissive core/shell nano-particles. An unpatterned, common electrode is formed over the light-emitting layer. The light-emitting layer emits light by the recombination of holes and electrons supplied by the electrodes.

Abstract: In one embodiment, the present invention includes a method for forming a dielectric layer on a semiconductor wafer and patterning at least one opening in the dielectric layer, depositing a barrier layer over the dielectric layer, depositing a conductive layer over the barrier layer, and electropolishing the conductive layer while ultrasonically agitating the semiconductor wafer until a predetermined amount of the conductive layer remains over the barrier layer. Other embodiments are described and claimed.

Abstract: The present invention relates to a novel process for producing (Al, Ga)InN and AlGaInN single crystals by means of a modified HVPE process, and also to (Al, Ga)InN and AlGaInN bulk crystals of high quality, in particular homogeneity. The III-V compound semiconductors produced by the process according to the invention are used in optoelectronics, in particular for blue, white and green LEDs and also for high-power, high-temperature and high-frequency field effect transistors.

Abstract: By removing an outer spacer of a transistor element, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, employing a wet chemical etch process, it is possible to position a stressed contact liner layer more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region, without affecting circuit elements in the P-type regions.

Abstract: According to an aspect of the present invention, there is provided a liquid crystal display that includes a gate electrode and line formed on a transparent insulating substrate, a gate insulating film covering the gate electrode and line, a semiconductor layer formed on the gate insulating film, a source electrode, a source line, and a drain electrode formed on the semiconductor layer, and a pixel electrode connected to the drain electrode. The semiconductor layer is integrally formed of three portions which are a crossover portion of the source line and the drain line, a TFT portion, and a connecting portion connecting the crossover portion to the TFT portion. A part of the crossover portion on the connecting portion side and the whole connecting portion are covered by the source electrode and the source line.

Abstract: A semiconductor device, wherein: the first MIS transistor includes a first fully-silicided gate electrode formed on a first gate insulating film and made of a first metal silicide film; and the second MIS transistor includes a second fully-silicided gate electrode formed on a second gate insulating film and made of a second metal silicide film whose silicide composition is different from that of the first metal silicide film. The semiconductor device further includes an L-shaped insulating film, the L-shaped insulating film being integral with the second gate insulating film and extending from a top of an isolation region formed between a first active region and a second active region of a semiconductor substrate along a side surface of the second fully-silicided gate electrode in a gate width direction; and the first fully-silicided gate electrode and the second fully-silicided gate electrode are electrically connected with each other.