Abstract: A driver system with emphasis or de-emphasis control of optic signal generator comprising an input configured to receive an input signal that is to be transmitted as an optic signal. Also part of this system is a rising edge delay creating a first delay signal relative to the input signal and a falling edge delay creating a second delay signal relative to the input signal. A multiplexer receives the first delay signal and the second delay signal and selectively outputs either the first delay signal and the second delay signal to an amplifier. A first amplifier amplifies the input signal to create an amplified input and a second amplifier amplifies the multiplexer output signal to create a de-emphasis signal. A summing junction subtracts the de-emphasis signal from the amplified input to create a driver output signal. The rising and falling edge delays may each comprise two more delays.

Abstract: A network controller includes: a first acquisition unit configured to acquire, based on a signal quality amount of each of wavelength paths set in a network of an optical wavelength-multiplexed transmission system, a signal quality amount of each of spans in each of the wavelength paths; an arithmetic unit configured to calculate a signal quality amount of each of spans in a wavelength path of an estimation target, based on the signal quality amount acquired by the first acquisition unit; and an estimation unit configured to estimate a signal quality amount of the wavelength path of the estimation target, based on the signal quality amount calculated by the arithmetic unit.

Abstract: Maximum likelihood bit-stream generation and detection techniques are provided using the M-algorithm and Infinite Impulse Response (IIR) filtering. The M-Algorithm is applied to a target input signal X to perform Maximum Likelihood Sequence Estimation on the target input signal X to produce a digital bit stream B, such that after filtering by an IIR filter, the produced digital stream Y produces an error signal satisfying one or more predefined requirements. The predefined requirements comprise, for example, a substantially minimum error. In an exemplary bit detection implementation, the target input signal X comprises an observed analog signal and the produced digital stream Y comprises a digitized output of a receive channel corresponding to a transmitted bit stream. In an exemplary bit stream generation implementation, the target input signal X comprises a desired transmit signal and the produced digital stream Y comprises an estimate of the desired transmit signal.

Abstract: A charge pump circuit includes N boosting circuits, (N?2) switching circuits and a control circuit. A kth boosting circuit includes a unidirectional component and a capacitor. A positive terminal of the unidirectional component of the kth boosting circuit is electrically connected to a negative terminal of a unidirectional component of a (k?1)th boosting circuit. A first terminal of the capacitor of the kth boosting circuit is electrically connected to a negative terminal of the unidirectional component of the kth boosting circuit. A (2i?1)th switching circuit selectively conducts a current path from a (2i?1)th boosting circuit to a first clock terminal or to a ground terminal according to a control signal of the control circuit. A (2i)th switching circuit selectively conducts a current path from a (2i)th boosting circuit to a second clock terminal or to the ground terminal according to the control signal of the control circuit.

Abstract: A receiver includes a bias current source, a comparator and an output circuit. The bias current source is powered by a first voltage source, and generates a bias current according to a second voltage source. The first voltage source is higher than the second voltage source. The comparator, coupled to the bias current source, compares two input signals to generate a comparison signal according to the bias current. The output circuit is powered by the second voltage source, and generates an output signal according to the comparison signal. The output signal and the second voltage source belong to the same power domain.

Abstract: An integrated circuit includes a degeneration network configured to improve group delay across one or more variations, wherein the degeneration network includes a transimpedance amplifier with one or more degeneration inductors. The transimpedance amplifier further includes one or more transistors, and the one or more degeneration inductors are connected after at least one emitter of the one or more transistors.

Abstract: A phase shifter unit cell or a connected set of such cells that can be well isolated from external circuitry and which do not introduce insertion loss into an RF signal path, exhibit good return loss, and further provides additional advantages when combined with bracketing attenuator circuits. More particularly, embodiments integrate a high-isolation function within a phase shifter circuit by breaking the complimentary nature of the control signals to a phase shifter cell to provide greater control of switch states internal to the phase shifter cell and thus enable a distinct high-isolation state, and by including a switchable shunt termination resistor for use in the high-isolation state. Some embodiments are serially coupled to attenuator circuits to enable synergistic interaction that reduces overall die size and/or increases isolation. One such embodiment positions a high-isolation phase shifter cell in accordance with the present invention between bracketing programmable attenuators.

Abstract: A system includes an audio amplifier, a duty cycle detector, a channel equalizer, and a sample-and-hold circuit. The audio amplifier is configured to amplify an analog audio signal to produce an amplified audio signal. The duty cycle detector is configured to generate a saturation detect signal at a first state upon detection that the amplified audio signal produced by the audio amplifier is clipped. The channel equalizer is configured to generate an initial estimate of a speaker terminal voltage. The sample-and-hold circuit is configured to sample and hold the initial estimate of the speaker terminal voltage as a final estimate of the speaker voltage when the saturation detect signal is in the first state.

Abstract: A method for communicating using polynomial-based signals. In such a method, a set of basis polynomial functions used to generate waveforms may be identified, wherein each of the basis polynomial functions in the set of basis polynomial functions is orthogonal to each of the other basis polynomial functions in the set of basis polynomial functions in a coordinate space. The set of basis polynomial functions may be combined into a message polynomial. The message polynomial may be convolved with a reference polynomial to produce a transmission polynomial. From the transmission polynomial, a sequence of amplitude values may be generated. Finally, a signal may be transmitted based on the sequence of amplitude values, which may be further modified based on, for example, instantaneous spectral analysis. In some embodiments, orthogonal polynomials may include Chebyshev or Cairns polynomials.

Abstract: In a related-art semiconductor device, there is a problem that a second-order harmonic distortion originating in a power amplifier driven by a rectangular-wave signal cannot be effectively suppressed. According to an embodiment, a semiconductor device generates a transmission signal RF_OUT for driving an antenna by receiving first transmission pulses INd_P and second transmission pulses INd_N having a duty ratio lower than 50%, adjusting a phase difference between the first and second transmission pulses INd_P and INd_N to a predefined phase difference, and supplying the phase-difference-adjusted first and second transmission pulses INd_P and INd_N to a power amplifier 54.

Abstract: A line receiver including an analog-to-digital converter is described. The line receiver may include an input stage, a first sampling stage, an integration stage, and a second sampling stage. The input stage may be configured to receive an input voltage representative of a signal transmitted by a transmitter, and to convert the input voltage to a current. The input stage may include a trans-conductance stage. The current may be sampled using the first sampling stage. The sampled current may be converted to a voltage using the integration stage. The integration stage may include a trans-impedance stage. The voltage obtained using the integration stage may be sampled using the second sampling stage.

Abstract: A magnetic spectrometer is integrated in a semiconductor substrate and provides high sensitivity without using an external magnet field. The spectrometer includes one or more highly stable on-chip oscillator and LC resonator. A current caused to pass through the inductor generates a magnetic field and polarizes the nanoparticles placed in its proximity, thereby changing the effective inductance of the inductor, and in turn, modifying the oscillation frequency of the LC resonator. The shift in the oscillation frequency is used to characterize the nanoparticles and measure their magnetic susceptibility frequency profile. The spectrometer operates at multiple frequencies over a diverse range without using a reference sensor thereby effectively increasing its spatial multiplexing density.

Abstract: A phase-frequency detector (PFD) is electrically coupled to a charge pump of a phase-locked-loop (PLL). The PFD includes a first differential latch electrically coupled to the charge pump. The first differential latch drives a differential pair of increment signals to the charge pump in response to differential pairs of both reference clock signals and reset signals. The PFD also includes a second differential latch electrically coupled to the charge pump. The second differential latch drives a differential pair of decrement signals to the charge pump in response to differential pairs of both feedback clock signals and reset signals. The PFD also includes a differential AND gate electrically coupled to both the first differential latch and the second differential latch. The differential AND gate drives the differential pair of reset signals to both of the differential latches in response to the differential pairs of both increment signals and decrement signals.

Abstract: An integrated circuit comprises a power supply input pin receiving an off-chip supply voltage having a variable current, an on-chip power source powered by the off-chip supply voltage and providing a regulated current, a memory array, and a set of one or more circuits coupled to the memory array and powered by the regulated current from the on-chip power source. The IC can include control circuitry performing memory operations on the memory array, said control circuitry powered by at least the off-chip supply voltage from the power supply pin.

Abstract: Provided is a system for regulating temperature change of semiconductor components within a converter. The system includes a temperature regulator in communication with at least one semiconductor within the converter and a power source, the temperature regulator comprising a controller. Also included is a peak detector in communication with at least one of the semiconductors and configured to identify a maximum temperature of each semiconductor when the semiconductor conducts high current.

Abstract: A wireless communication device includes an antenna, a DPDC, an amplifier, a coupler, and a bias output unit. The DPDC performs distortion compensation on a transmission signal based on a feedback signal. The amplifier amplifies the transmission signal subjected to the distortion compensation by the DPDC. The coupler splits the transmission signal amplified by the amplifier into a transmission signal output to the antenna and the feedback signal input to the DPDC. The DPDC measures an index based on a reflected wave obtained by reflection of the transmission signal split by the coupler from the antenna. The bias output unit applies a bias voltage for controlling an efficiency of an amplifier to the amplifier in accordance with the index measured by the DPDC.

Abstract: A laminated body includes: a substrate portion composed of silicon carbide; and a graphene film disposed on a first main surface of the substrate portion, the graphene film having an atomic arrangement oriented with respect to an atomic arrangement of the silicon carbide of the substrate portion. A region in which a value of G?/G in Raman spectrometry is not less than 1.2 is not less than 10% in an area ratio in an exposed surface of the graphene film, the exposed surface being a main surface of the graphene film opposite to the substrate portion.

Abstract: A tunable multi-path filter, a method for filtering a radio frequency signal with the tunable multi-path filter, and a communication device including the tunable multi-path filter. In one embodiment, the tunable multi-path filter includes a voltage controlled current source, an oscillator source, and at least two filter paths. The voltage controlled current source for receiving a radio frequency (RF) signal and generating a current signal. The oscillator source for generating a tunable clock signal. Each of the at least two filter paths are coupled to the voltage controlled current source and the oscillator source, and are configured to generate an output voltage signal based at least in part on the current signal and the tunable clock signal. In some embodiments, the tunable multi-path filter further includes a carrier signal rejection component that is configured to reduce the carrier feedthrough in the output voltage signals.

Abstract: A hybrid system-on-chip provides a plurality of memory and processor die mounted on a semiconductor carrier chip that contains a fully integrated power management system that switches DC power at speeds that match or approach processor core clock speeds, thereby allowing the transfer of data between off-chip physical memory and processor die.

Abstract: In one example, a device includes a transformer configured to electrically isolate one or more components of the device from a communication bus, and a controller configured to receive and transmit data via the communication bus, wherein the controller is operable to communicate via a plurality of communication standards that include at least one analog unidirectional communication standard and at least one digital bidirectional communication standard, and wherein both the received data and the transmitted data pass through the transformer.

Abstract: A Schmitt trigger circuit according to an embodiment includes a voltage dividing circuit that divides an input voltage and outputs a divided voltage, and a basic Schmitt trigger circuit that includes a transistor as a current controlling element and controls current flowing through a light emitting diode (LED) included in an external photocoupler on the basis of the output voltage of the voltage dividing circuit proportional to the input voltage. The voltage dividing circuit has a positive temperature coefficient.

Abstract: A system and method use an inverse square root function (ISQR) function, in part, to compand and decompand signals. A system includes a companding processor and a transmitter. The companding processor compands input signals into companded signals using a compander function, C{x(n)}. The compander function compands the input signals based, at least in part, on an inverse square root (ISQR) function over at least a portion of a signal amplitude probability density function. The transmitter then transmits the companded signals as electromagnetic wave signals.

Abstract: A switch-mode power supply is provided that includes a comparator for producing a pulse-width modulated (PWM) controller clock signal for controlling a power switch in the switch-mode power supply. The switch-mode power supply is configured to superimpose a DC-free version of a ramp voltage with an error voltage to produce a combined voltage. The comparator compares the combined voltage to a reference voltage to produce the PWM controller clock signal.

Abstract: A signal-processing system has an amplifier that generates an amplified (RF) output signal based on an (RF) input signal. The amplifier receives a supply voltage that can be selectively set to an appropriate level between a lower power supply level and a higher power supply level. With one power supply permanently connected to the supply voltage node, a control unit executes software to toggle a supply switch to periodically connect and disconnect the other power supply thereby generating a weighted average value for the supply voltage between the two power supply levels. When a sudden and large increase occurs in the (input) power level, hardware-interrupt circuitry interrupts and supersedes the software-based control of the supply-voltage switch to quickly switch the supply voltage towards the higher power supply level. The hardware-interrupt circuitry handles such situations faster than the software-based control in order to prevent a limit violation of spectrum emission requirements.

Abstract: A system for dynamically calibrating operational parameters of a Device Under Test (DUT) includes a signal generator for generating a data pattern, a DUT structured to generate a clock signal, an oscilloscope structured to measure margins of the generated clock signal compared to an eye-diagram produced on the oscilloscope from the data pattern, and a calibration unit. The calibration unit can produce a candidate a jitter value for the signal generator, receive a determination from the oscilloscope whether the data pattern generated with the candidate jitter value causes the DUT to produce the generated clock signal within a pre-determined tolerance level, and modify the jitter value accordingly. The calibration unit may also be further structured to generate voltage swing values.

Abstract: A frequency conversion circuit having a plurality of N signal channels, each being fed an input signal and a train of pluses having a period T and a duty cycle T/N. Each channel includes: a sampler coupled the input signal and being responsive to sampling signals; and a controllable time delay for producing the train of sampling signals in response to the train of pulses, the time delay imparting a time delay to the pulses in accordance with a time delay command signal fed to the time delay. Each one of the sampling signals is produced by the time delay in each one of the channels with the period T and the duty cycle T/N with the sampling signals in one of the trains of the sampling signals being delayed with respect to the sampling signals in another one of the trains the sampling signals a time T/N.

Abstract: Systems and methods for sensing voltage on a chip are described herein. In one embodiment, a voltage sensor comprises a voltage-controlled oscillator coupled to a voltage being sensed, and a plurality of transition detectors, wherein each of the transition detectors is coupled to a different location on the oscillator, and wherein each of the transition detectors is configured to count a number of transitions at the respective location over a time period. The voltage sensor also comprises an adder configured to add the numbers of transitions from the transition detectors to generate an output value that is approximately proportional to the voltage.

Abstract: A circuit structured to drive an isolated high speed voltage metal-oxide-semiconductor field-effect transistor (MOSFET) switch, including a first MOSFET and a second MOSFET configured to operate as a switch, a capacitor, a charging component in parallel with the capacitor, a first switch in series with the charging component, and a second switch in parallel with the charging component and the capacitor. The stored voltage in the capacitor is sent to the gates of the first MOSFET and the second MOSFET when a second switch is open and a first switch is closed.

Abstract: A high-speed input circuit for industrial control provides an optoisolator protected by a series current regulator and shunting voltage regulator. The combined effect of the regulators is to allow the input circuit to work over a wide range of voltages while providing extremely fast response time.

Abstract: Embodiments provide a receiver comprising an input coupled to a communication channel for receiving an input signal from the communication channel, a first processing filter coupled to the input, and a first level estimation module coupled to the first processing filter to estimate a first level of the input signal based upon the first processing filter. The receiver further comprises a second processing filter coupled to the input, a second level estimation module coupled to the second processing filter to estimate a second level of the input signal based upon the second processing filter, and a control module coupled to (i) the first level estimation module and (ii) the second level estimation module, wherein the control module includes logic configured to select an analog pre-filter for the input signal based upon (i) the first level of the input signal and (ii) the second level of the input sign.

Abstract: The present invention relates to a protective device for protection of an electrical circuit equipped with a smoothing capacitor against reversal of polarity of the input voltage, with an input via which the protective device can be connected to a voltage supply for coupling in an input voltage, with an output via which the protective device an be connected to the electrical circuit to be protected, with a controllable switch which is arranged between an input terminal of the input and an output terminal of the output having the same polarity and which is designed to interrupt a current flow between the input terminal and the output terminal which are connected to one another, and with a control unit which is designed to control the controllable switch, when an applied input voltage with reverse polarity is detected, in such a way that the interruption of the current flow takes place with a time lag relative to a time of the application of the input voltage with reverse polarity.

Abstract: A bidirectional universal serial bus (USB) adapter port that can be integrated into a rechargeable battery operated flashlight or other rechargeable battery operated device. The invention utilizes a micro-controller to convert a single USB adapter port into either an input device or an output device. A high power rechargeable flashlight with bidirectional USB adapter port is capable of recharging external electronic devices, as well as recharging itself through the same port.

Abstract: To provide a DCDC converter achieving low power consumption. A clock generation circuit, an error amplifier, a comparator, and a timer are included in a control circuit. The clock generation circuit, the error amplifier, and the comparator each include a bias circuit and a potential hold portion for intermittently holding a constant potential generated in the bias circuit. The potential hold portion includes a capacitor and a switch. The on or off of the switch is intermittently controlled using the timer. Even in a period in which the supply of voltage is stopped, a signal based on a constant potential generated in the bias circuit is continuously output.

Abstract: A method and circuit for testing an analog-to-digital converter (ADC) are provided. The method comprises: coupling a single-ended output of an analog signal source to a differential input of an amplifier; coupling a differential output of the amplifier to a differential input of the ADC; alternately providing first and second test signals from the single-ended output of the analog signal source to first and second input terminals of the differential input of the amplifier; amplifying the first and second test signals to generate amplified differential signals at the differential output of the amplifier; providing the amplified differential signals to the differential input of the ADC; and determining if an output of the ADC is as expected. An offset may also be provided to the differential output of the amplifier. The method allows an ADC having a differential input to be tested using a digital-to-analog converter (DAC) having a single-ended output.

Abstract: Disclosed is a passive intermodulation (PIM) test system having a pulsed signal generator configured to generate and apply a pulsed stimulus signal to a device under test. The PIM test system is further configured to measure a power of at least one PIM product generated by a PIM source in the device under test using the pulsed stimulus signal. Also disclosed in a method for Cevaluating PIM in a device under test, the method includes using a pulsed stimulus signal to measure a power of at least one PIM product generated by a PIM source in the device under test.

Abstract: An electrical supply apparatus is provided. The apparatus has an input for connecting the electrical supply apparatus to a power supply system, an output for connecting the electrical supply apparatus to a load, a rectifier for rectifying the input voltage into a rectified input voltage, and a PFC module for smoothing the rectified input voltage. The PFC module also has an active power factor correction device for shaping a time-dependent supply current, such that a time-dependent input current into the PFC module is matched to a time-dependent current waveform signal. A control module is provided for generating the current waveform signal. The control module generates the current waveform signal during the operation of the electrical supply apparatus independently of the input voltage and temporally synchronizes the current waveform signal with the input voltage or a derivative of the input voltage.

Abstract: A hybrid system-on-chip provides a plurality of memory and processor die mounted on a semiconductor carrier chip that contains a fully integrated power management system that switches DC power at speeds that match or approach processor core clock speeds, to enable transfer of data between off-chip physical memory and processor die.

Abstract: An integrated circuit including a plurality of internal clock generator circuits from which an internal clock is selected based on an external time reference. A number of cycles of internal clock signals from each of the internal clock generator circuits, or from at least one of those circuits where a frequency relationship is known, is counted relative to a system clock signal based on the external time reference. The lowest frequency internal clock signal providing at least a minimum number of cycles within the system clock period, the minimum number assuring completion of a function within a time constraint, is selected as the internal clock. Robust performance over a wide range of fabrication process parameters and operating conditions is assured.

Abstract: A anti-wiretapping device includes a power input, a power output for energizing anti-wiretapping electronic equipment, at least two dischargeable power storage units, and a control unit for selectively connecting the power storage units to the power input and to the power output, such that when one of the power storage units is connected to the power output it is switched off from the power input. At least one power storage unit is connected to the power input for charging during a connection of the other power storage unit to the power output for energizing the electronic equipment.

Abstract: An analog-to-digital converter has a sampler to hold a sampled signal, an input signal predictor to generate a prediction signal at predetermined timing before a signal level of a ramp signal that monotonically increases or monotonically decreases with time crosses a signal level of the sampled signal, a comparator to compare signal levels of the ramp signal and the sampled signal to output a comparison signal showing whether the signal level of the ramp signal is larger than the signal lever of the sampled signal, a first counter to perform a count operation in synchronism with a first clock signal within a period from start of a comparison operation by the comparator to generation of the prediction signal, and a second counter to perform a count operation in synchronism with a second clock signal.

Abstract: An RF transmitter comprises a capacitive energy storage, an output stage and a switching circuit with an open state and a closed state. The capacitive energy storage forms with the antenna when connected thereto a resonance circuit with a resonance frequency and a quality factor. The output stage provides an electric transmission signal to the resonance circuit. The switching circuit comprises a first transistor for switching between the open state and the closed state and is connected to an antenna output terminal through a capacitance formed by the capacitive energy storage such that the maximum signal voltage occurring across the switching circuit in its open state is lower than the maximum signal voltage occurring across the antenna output terminals. The transmitter is adapted to alter the quality factor by changing the series resistance of the switching circuit in its closed state.

Abstract: Sample-and-hold (S/H) circuitry operating in track and hold phases and having a first S/H circuit with a first hold capacitor at which a first voltage value is maintained in the hold phase, and a dielectric absorption (DA)-suppressing circuit connectable to the first hold capacitor for operating the S/H circuitry in an additional phase after completing the hold phase and before entering the track phase. The DA-suppressing circuit is configured to supply the first hold capacitor, during an operation in the additional phase, with a second voltage value that is negatively correlated with the first voltage value.

Abstract: A system for performing diagnostic checks on a data message transmitted from a sensor and received by a receiver includes a receiver clock tick counter, a prescaler counter, a calibration pulse detector, a nibble counter, and a calculator. The system receives first and second data messages transmitted from the sensor. Pulse widths of first and second calibration pulses of the first and second data messages, respectively, and lengths of the first and second data messages are measured using the receiver clock tick, prescaler, and nibble counters based on a compensated receiver clock signal. Thereafter, the pulse widths of the first and second calibration pulses and the lengths of the first and second data messages are compared using the calculator to perform the diagnostic checks.

Abstract: Various embodiments provide a method for processing a stimulation signal. The method may include monitoring an output voltage on an electrode, the electrode being provided with the stimulation signal; determining whether the output voltage is lower than a threshold voltage; if it is determined that the output voltage is lower than the threshold voltage, modifying the waveform of the stimulation signal; and providing the modified stimulation signal to an object via the electrode.

Abstract: An RF pulse signal generation switching circuit for controlling an output of a power FET for amplifying a high frequency signal to generate an RF pulse signal that is the high frequency signal pulse formed into a pulse-wave shape is provided. The circuit includes first and third n-type FETs of which gates are inputted with a control pulse that supplies a rise timing and a fall timing of a pulse, and a second n-type FET of which a gate is connected with a drain of the first FET. A source of the first FET and a source of the third FET are grounded, respectively. The drain of the first FET is applied with a first drive voltage via a resistor. A drain of the second FET is applied with a second drive voltage. A source of the second FET is connected with a drain of the third FET and the connection point therebetween is connected with the power FET. A capacitor is connected between the connection point and an end of the resistor from which the first drive voltage is applied.

Abstract: Implementations of the present disclosure involve an apparatus and/or method for providing a constant frequency timer signal for a microprocessor that operates with varying core clock signals. The apparatus and/or method utilizes a code generator, such as a gray code generator, operating on a reference clock signal that allows the constant frequency timer signal to be either faster or slower than the core clock frequency. More particularly, the apparatus and/or method may compute a difference between previous gray code samples and add the calculated difference to a software visible reference clock signal such that constant frequency timer signal may be faster or slower than the core clock signal. Through the use of the apparatus and/or method, a core clock signal may be reduced as needed to provide operational power savings to the microprocessor and the computing system employing the techniques described herein, while maintaining synchronization between the executing programs of the computing system.

Abstract: Aspects of the present disclosure relate to floating point timers and counters that are used in a variety of contexts. In some implementations, a floating point counter can be used to generate a wave form made up of a series of pulses with different pulse lengths. An array of these floating point counters can be used to implement a pool of delays. In other implementations, an array of floating point counters can be used to analyze waveforms on a number of different communication channels. Analysis of such waveforms may be useful in automotive applications, such as in wheel speed measurement for example, as well as other applications.

Abstract: A semiconductor device includes a reference current generator suitable for generating a reference current, a current-voltage converter suitable for generating a first reference voltage and a second reference voltage in response to the reference current, and an analog-digital converter suitable for generating a digital code value based on a voltage difference between the first and second reference voltages, wherein the reference current generator includes a current control unit for controlling the reference current in response to the digital code value.

Abstract: A signal sampling circuit includes: a signal output unit configured to output a level signal to an output node in response to a control signal; a signal sampling unit coupled to the output node and configured to sample the level signal in a sampling period; a first current sinking unit configured to sink a constant current from the output node; and a second current sinking unit configured to sink a current from the output node after a time point where the control signal is deactivated.

Abstract: A PWM signal generation circuit according to the present invention includes a duty setting unit (10) configured to generate a duty control signal designating a duty ratio corresponding to each period of a PWM signal on the basis of an initial duty setting signal, a target duty setting signal, a slope setting signal, and a clock signal, a period setting unit (20) configured to output a period setting value, and an output control unit (30) configured to generate the PWM signal having a period corresponding to the period setting value and having a duty ratio corresponding to a value of the duty control signal. The duty setting unit (10) increases the value of the initial duty ratio to the value of the target duty ratio each time the number of a clock pulse of the clock signal reaches the period setting value reaches the slope setting value.