Abstract: There is provided an etching method which can form trenches or via holes having desired aspect ratios and shapes in a to-be-processed object made of silicon. The etching method includes: a hydrogen halide-containing gas-based etching step of etching a silicon substrate by introducing a hydrogen halide-containing gas into a vacuum chamber; a fluorine-containing gas-based etching step of etching the silicon substrate by introducing a fluorine-containing gas into the vacuum chamber; a protective film formation step forming a protective film on the silicon substrate by sputtering a solid material; and a protective film removal step of removing part of the protective film by applying radio frequency bias power to a substrate electrode. The fluorine-containing gas-based etching step, the protective film formation step, and the protective film removal step are repeatedly performed in this order.

Abstract: Etch stabilizing ions (37) are introduced, e.g., by ion implantation (34), into a portion (36) of a substrate (20) underlying an etch window (24) in a masking layer (22) covering the substrate (20), where a trench (26) is desired to be formed. When the portion (36) of the substrate (20) containing the etch stabilizing ions (37) is etched to form the trench (26), the etch stabilizing ions (37) are progressively released at the etch interface (28?) as etching proceeds, substantially preventing gas micro-bubbles or other reaction products at the etch interface (28?) from disrupting etching. Using this method (700), products containing trenches (26) are much more easily formed and such trenches (26) have much smoother interior surface (28).

Abstract: A substrate polishing method, a semiconductor device and a fabrication method for a semiconductor device are disclosed by which high planarization polishing can be achieved. In the substrate polishing method, two or more different slurries formed from ceria abrasive grains having different BET values from each other are used to carry out two or more stages of chemical-mechanical polishing processing of a polishing object oxide film on a substrate to flatten the polishing object film.

Abstract: A method for forming a chip package includes: providing a substrate having a first and a second surfaces; removing a portion of the substrate to form openings in the substrate, wherein the openings extend from the first surface towards the second surface or from the second surface towards the first surface; after forming the openings, at least a first portion of the substrate serves as a first movable bulk, and at least a second portion of the substrate serves as a second movable bulk, wherein the first movable bulk and the second movable bulk are respectively located between the openings; disposing a protecting substrate on the second surface of the substrate; forming a through-hole in the protecting substrate; and forming a conducting layer on the protecting substrate, wherein the conducting layer extends from a surface of the protecting substrate into the through-hole to electrically connect the second movable bulk.

Abstract: One illustrative method disclosed herein includes forming a patterned hard mask layer comprised of a plurality of discrete openings above a structure, wherein the patterned hard mask layer is comprised of a plurality of intersecting line-type features, forming a patterned etch mask above the patterned hard mask layer that exposes at least one, but not all, of the plurality of discrete openings, and performing at least one etching process through the patterned etch mask and the at least one exposed opening in the patterned hard mask layer to define an opening in the structure.

Abstract: A semiconductor device includes: a trimming object circuit configured to use a trimming circuit to adjust an output based on a trimming value; and a trimming value setting circuit configured to set the trimming value. The trimming value setting circuit includes: a register configured to volatilely store a pseudo-trimming value set with reference to a trimming table such that an output value of the trimming object circuit becomes equal to a target value; a trimming value storage configured to non-volatilely store a final trimming value, wherein the final trimming value is set by correcting the pseudo-trimming value with reference to a trimming value correction table such that the output value of the trimming object circuit, which is obtained based on the pseudo-trimming value, becomes equal to the target value; and a selector configured to select one of the pseudo-trimming value and the final trimming value as the trimming value.

Abstract: A method for removing material from surfaces of at least a portion of at least one recess or at least one aperture extending into a surface of a substrate includes pressurizing fluid so as to cause the fluid to flow into the at least one recess or the at least one aperture. The fluid may be pressurized by generating a pressure differential across the substrate, which causes the fluid to flow into or through the at least one aperture or recess. Apparatus for pressurizing fluid so as to cause it to flow into or through recesses or apertures in a substrate are also disclosed.

Abstract: A method of processing a semiconductor substrate in forming scribe line alignment marks includes forming pitch multiplied non-circuitry features within scribe line area of a semiconductor substrate. Individual of the features, in cross-section, have a maximum width which is less than a minimum photolithographic feature dimension used in lithographically patterning the substrate. Photoresist is deposited over the features. Such is patterned to form photoresist blocks that are individually received between a respective pair of the features in the cross-section. Individual of the features of the respective pairs have a laterally innermost sidewall in the cross-section. Individual of the photoresist blocks have an opposing pair of first pattern edges in the cross-section that are spaced laterally inward of the laterally innermost sidewalls of the respective pair of the features.

Abstract: A method for separating a layer for transfer includes forming a crack guiding layer on a substrate and forming a device layer on the crack-guiding layer. The crack guiding layer is weakened by exposing the crack-guiding layer to a gas which reduces adherence at interfaces adjacent to the crack guiding layer. A stress inducing layer is formed on the device layer to assist in initiating a crack through the crack guiding layer and/or the interfaces. The device layer is removed from the substrate by propagating the crack.

Abstract: A semiconductor light emitting device includes a substrate having a wiring pattern formed thereon, and a semiconductor light emitting element mounted on one main surface of the substrate and electrically connected to the wiring pattern. The substrate has, on the one main surface, a serrated structure reflecting at least part of light emitted from said semiconductor light emitting element to the substrate, to a direction perpendicular to the one main surface.

Abstract: A method for fabricating a device is disclosed. An exemplary method includes providing a substrate and forming a plurality of fins over the substrate. The method further includes forming a first opening in the substrate in a first longitudinal direction. The method further includes forming a second opening in the substrate in a second longitudinal direction. The first and second longitudinal directions are different. The method further includes depositing a filling material in the first and second openings.

Abstract: There is disclosed methods of making photosensitive devices, such as flexible photovoltaic (PV) devices, through the use of epitaxial liftoff. Also described herein are methods of preparing flexible PV devices comprising a structure having a growth substrate, wherein the selective etching of protective layers yields a smooth growth substrate that us suitable for reuse.

Abstract: An edge terminated semiconductor device is described including a GaN substrate; a doped GaN epitaxial layer grown on the GaN substrate including an ion-implanted insulation region, wherein the ion-implanted region has a resistivity that is at least 90% of maximum resistivity and a conductive layer, such as a Schottky metal layer, disposed over the GaN epitaxial layer, wherein the conductive layer overlaps a portion of the ion-implanted region. A Schottky diode is prepared using the Schottky contact structure.

Abstract: A method of modifying stress characteristics of a membrane in one embodiment includes providing a membrane layer, determining a desired stress modification, and forming at least one trough in the membrane layer based upon the determined desired stress modification.

Abstract: Provided is a producing of a surface-emitting laser capable of aligning a center axis of a surface relief structure with that of a current confinement structure with high precision to reduce a surface damage during the producing. The producing of the laser having the relief provided on a laminated semiconductor layer and a mesa structure, the process comprising the steps of: forming, on the layer, one of a first dielectric film and a first resist film having a first pattern for defining the mesa and a second pattern for defining the relief and then forming the other one of the films; forming a second resist film to cover the second pattern and expose the first pattern; and forming the mesa by removing the layer under the first pattern using the second resist film.

Abstract: A method of forming a semiconductor device is provided, comprising forming a plurality of hard masks on a substrate by patterning an insulating layer; forming a plurality of trenches in the substrate, each trench having trench walls disposed between two adjacent masks and extending vertically from a bottom portion to an upper portion; forming an insulating layer on the hard masks and the trench walls; forming a conductive layer on the insulating layer; etching the conductive layer to form conductive layer patterns to fill the bottom portions of the trenches; depositing a buffer layer on the conductive layer patterns and the trench walls; and filling the upper portions of the trenches with a capping layer.

Abstract: A semiconductor device has memory cell portions and compensation capacitance portions on a single substrate. The memory cell portion and the compensation capacitance portion have mutually different planar surface areas. The memory cell portion and the compensation capacitance portion include capacitance plate electrodes of the same structure. The capacitance plate electrode has a laminated structure including a boron-doped silicon germanium film and a metal film.

Abstract: Fabricating of one or more semiconductor devices with critical gate dimension control is facilitated by: providing a multilayer stack structure over a substrate; etching through the multilayer stack structure, with critical gate dimension control, to define multiple gate lines; providing a protective layer over the multiple gate lines; and patterning and cutting one or more gate lines of the multiple gate lines to facilitate defining multiple gate structures of the one or more semiconductor devices. Etching through the multilayer stack structure is facilitated by lithographically patterning the multilayer stack structure, and critical dimension feedback control is provided to at least one of the lithographically patterning or the etching through the multilayer stack structure.

Abstract: A mechanism is provided for a spin torque transfer random access memory device. A tunnel barrier is disposed on a reference layer, and a free layer is disposed on the tunnel barrier. The free layer includes an iron layer as a top part of the free layer. A metal oxide layer is disposed on the iron layer, and a cap layer is disposed on the metal oxide layer.

Abstract: A method of forming a light conversion element includes providing a semiconductor construction having a first photoluminescent element epitaxially grown together with a second photoluminescent element. A first region is etched in the first photoluminescent element from a first side of the semiconductor construction and a second region is etched in the second photoluminescent element from a second side of the semiconductor construction. In some embodiments the wavelength converter is attached to an electroluminescent element, such as a light emitting diode (LED).

Abstract: A method of manufacturing a color filter substrate includes forming a plurality of trenches having a predetermined depth by etching a surface of a transparent substrate, disposing a color filter material in the plurality of trenches to form a color filter layer, and forming a transparent electrode on the transparent substrate including the color filter layer therein.

Abstract: A crack prevention structure that reduces integrated circuit corner peeling and reduces cracking is disclosed. The crack prevention structure comprises a semiconductor substrate; a first plurality of dielectric layers of a first material disposed over the semiconductor substrate; a second plurality of dielectric layers of a second material different than the first material, disposed on the first plurality of dielectric layers, wherein the first plurality of dielectric layers and the second plurality of dielectric layers meet at an interface; and a plurality of metal structures and a plurality of via structures formed through the interface of the first plurality of dielectric layers and the second plurality of dielectric layers.

Abstract: A plug structure including a first dielectric layer, a second dielectric layer, a barrier layer and a second plug is provided. The first dielectric layer having a first plug therein is located on a substrate, wherein the first plug physically contacts a source/drain in the substrate. The second dielectric layer having an opening exposing the first plug is located on the first dielectric layer. The barrier layer conformally covers the opening, wherein the barrier layer has a bottom part and a sidewall part, and the bottom part is a single layer and physically contacts the first plug while the sidewall part is a dual layer. The second plug fills the opening and on the barrier layer. Moreover, a process of forming a plug structure is also provided.

Abstract: The present invention reduces the time required to manufacture a solar cell. After etching main surfaces (10B1, 10B2) of a crystalline silicon substrate (10B) using one etching solution, the main surfaces (10B1, 10B2) of the crystalline silicon substrate (10B) are etched at a lower etching rate than the etching performed using the one etching solution by using another etching solution that has a higher concentration of etching components than the one etching solution. In this way, a textured structure is formed in the main surfaces (10B1, 10B2) of the crystalline silicon substrate (10B).

Abstract: For modulating laser light for forming a modified region SD3 at an intermediate position between a position closer to a rear face 21 and a position closer to a front face 3 with respect to an object 1, a quality pattern J having a first brightness region extending in a direction substantially orthogonal to a line 5 and second brightness regions located on both sides of the first brightness region in the extending direction of the line 5 is used. After forming modified regions SD1, SD2 at positions closer to the rear face 21 but before forming modified regions SD4, SD5 at positions closer to the rear face 21 while using the front face 3 as a laser light entrance surface, the modified region SD3 is formed at the intermediate position by irradiation with laser light modulated according to a modulation pattern including the quality pattern J.

Abstract: A method for manufacturing a semiconductor device having a cooling mechanism comprises a modified region forming step of converging a laser light at a sheet-like object to be processed made of silicon so as to form a modified region within the object along a line to form a modified region, an etching step of anisotropically etching the object after the modified region forming step so as to advance the etching selectively along the first modified region and form a flow path for circulating a coolant as a cooling mechanism within the object, and a functional device forming step of forming a functional device on one main face side of the object.

Abstract: A substrate processing chamber includes a lift actuator that moves a pedestal between a substrate loading position and a substrate processing position. An adjustable seal defines an expandable sealed volume between a bottom surface of the pedestal and a bottom surface of the substrate processing chamber and is moveable between the substrate loading position and the substrate processing position. When the pedestal is in the substrate processing position, the pedestal and the adjustable seal define a first inert volume and a first process volume. When the pedestal is in the substrate loading position, the pedestal and the adjustable seal define a second inert volume and a second process volume. The second inert volume is less than the first inert volume and the second process volume is greater than the first process volume.

Abstract: A stack of a first hard mask portion and a second hard mask portion is formed over a semiconductor material layer by anisotropically etching a stack, from bottom to top, of a first hard mask layer and a second hard mask layer. The first hard mask portion is laterally recessed by an isotropic etch. A dielectric material layer is conformally deposited and planarized. The dielectric material layer is etched employing an anisotropic etch that is selective to the first hard mask portion to form a dielectric material portion that laterally surrounds the first hard mask portion. After removal of the second and first hard mask portions, the semiconductor material layer is etched employing the dielectric material portion as an etch mask. Optionally, portions of the semiconductor material layer underneath the first and second hard mask portions can be undercut at a periphery.

Abstract: Disclosed herein are various methods of forming conductive structures, such as conductive lines and via, on an integrated circuit device using a spacer erosion technique. In one example, the method includes forming a patterned hard mask layer above a layer of insulating material, the patterned hard mask having a hard mask opening, forming an erodible spacer in the hard mask opening to thereby define a spacer opening and performing at least one etching process through the spacer opening on the layer of insulating material to define a trench therein for a conductive structure, wherein the erodible spacer is substantially eroded away during the at least one etching process.

Abstract: A power semiconductor device has a semiconductor body which includes an active area and a peripheral area which both define a horizontal main surface of the semiconductor body. The semiconductor body further includes an n-type semiconductor layer, a pn junction and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral area. The pn junction is arranged between the n-type semiconductor layer and the main surface in the active area. The at least one trench extends in the peripheral area from the main surface into the n-type semiconductor layer and includes a dielectric layer with fixed negative charges. In the vertical direction, the dielectric layer is arranged both below and above the pn junction. The dielectric layer with fixed negative charges typically has a negative net charge. Further, a method for forming a semiconductor device is provided.

Abstract: Uniformity of a plasma process on a surface of a substrate is to be improved. In a plasma processing apparatus that processes a substrate by generating plasma from a processing gas introduced in a processing container, a ratio between an introducing amount of the processing gas introduced to a center portion of the substrate received in the processing container and an introducing amount of the processing gas introduced to a peripheral portion of the substrate received in the processing container is changed during a plasma process. Accordingly, a variation in an etching rate or the like between the center portion and the peripheral portion of the substrate may be reduced. Therefore, uniformity of the plasma process on the surface of the substrate is improved.

Abstract: Methods of epitaxy of gallium nitride, and other such related films, and light emitting diodes on patterned sapphire substrates, and other such related substrates, are described.

Abstract: Monocrystalline semiconductor substrates are textured with alkaline solutions to form pyramid structures on their surfaces to reduce incident light reflectance and improve light absorption of the wafers. The alkaline baths include hydantoin compounds and derivatives thereof in combination with alkoxylated glycols to inhibit the formation of flat areas between pyramid structures to improve the light absorption.

Abstract: An object to be processed 1 comprising a substrate 4 and a plurality of functional devices 15 formed on a front face 3 of the substrate 4 is irradiated with laser light L while locating a converging point P within the substrate 4, so as to form at least one row of a divided modified region 72, at least one row of a quality modified region 71 positioned between the divided modified region 72 and the front face 3 of the substrate 4, and at least one row of an HC modified region 73 positioned between the divided modified region 72 and a rear face 21 of the substrate 4 for one line to cut 5. Here, in a direction along the line to cut, a forming density of the divided modified region 72 is made lower than that of the quality modified region 71 and that of the HC modified region 73.

Abstract: A method for the removal of copper oxide from a copper and dielectric containing structure of a semiconductor chip is provided. The copper and dielectric containing structure may be planarized by chemical mechanical planarization (CMP) and treated by the method to remove copper oxide and CMP residues. Annealing in a hydrogen (H2) gas and ultraviolet (UV) environment removes copper oxide, and a pulsed ammonia plasma removes CMP residues.

Abstract: A method for processing a wafer in accordance with various embodiments may include: forming a passivation over the wafer; forming a protection layer over at least a surface of the passivation facing away from the wafer, wherein the protection layer includes a material that is selectively etchable to a material of the passivation; forming a mask layer over at least a surface of the protection layer facing away from the wafer, wherein the mask layer includes a material that is selectively etchable to the material of the protection layer; etching the wafer using the mask layer as a mask; selectively etching the material of the mask layer to remove the mask layer from the protection layer, after etching the wafer; and selectively etching the material of the protection layer to remove the protection layer from the passivation, after selectively etching the material of the mask layer.

Abstract: A power semiconductor device has a semiconductor body which includes an active area and a peripheral area which both define a horizontal main surface of the semiconductor body. The semiconductor body further includes an n-type semiconductor layer, a pn junction and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral area. The pn junction is arranged between the n-type semiconductor layer and the main surface in the active area. The at least one trench extends in the peripheral area from the main surface into the n-type semiconductor layer and includes a dielectric layer with fixed negative charges. In the vertical direction, the dielectric layer is arranged both below and above the pn junction. The dielectric layer with fixed negative charges typically has a negative net charge. Further, a method for forming a semiconductor device is provided.

Abstract: A method for fabricating an edge termination, which can be used in conjunction with GaN-based materials, includes providing a substrate of a first conductivity type. The substrate has a first surface and a second surface. The method also includes forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The substrate, the first GaN epitaxial layer and the second GaN epitaxial layer can be referred to as an epitaxial structure.

Abstract: A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a first gate electrode is formed on the first gate insulating film. A second isolation is formed on the semiconductor substrate, and a second element region is isolated via the second isolation. A second gate insulating film is formed on the second element region, and a second gate electrode is formed on the second gate insulating film. A first oxide film is formed between the first isolation and the first element region. A second oxide film is formed between the second isolation and the second element region. The first isolation has a width narrower than the second isolation, and the first oxide film has a thickness thinner than the second oxide film.

Abstract: A method for manufacturing a semiconductor optical modulator includes forming a p-type semiconductor layer on a main surface of a p-type semiconductor substrate; forming a pair of stripe-shaped masks on the p-type semiconductor layer, the stripe-shaped masks extending in a first direction along the main surface of the p-type semiconductor substrate and being spaced apart from each other; simultaneously forming a hole and a pair of stripe structures extending in the first direction by etching the p-type semiconductor layer through the stripe-shaped masks, the pair of stripe structures defining the hole; after removing the stripe-shaped masks, forming a buried layer in the hole; forming a core layer on the buried layer and the stripe structures; and forming an upper cladding layer on the core layer. The buried layer is made of a semiconductor material with a lower optical absorption loss than that of the p-type semiconductor layer.

Abstract: A first wiring is disposed over a semiconductor substrate. A first via is disposed over the first wiring. Further, the bottom surface of the first via is in contact with the first wiring. A first insulation layer is disposed over the semiconductor substrate, and is in contact with at least the top surface of the first wiring and the side surface of the first via. At least a part of each side surface of the first wiring and the first via cuts off each metal crystal grain.

Abstract: A method for making a structure comprising an active part comprising at least two layers from a first single crystal silicon substrate, said method comprising the steps of: a) making at least one porous silicon zone in the first substrate, b) making an epitaxial growth deposition of a single crystal silicon layer on the entire surface of the first substrate and the surface of the porous silicon zone, c) machining the epitaxially grown single crystal layer at the porous silicon zone to make a first suspended zone, d) removing or oxidizing the porous silicon, e) depositing a sacrificial layer being selective towards silicon, f) machining the first substrate, g) releasing the suspended zones by withdrawing the sacrificial layer.

Abstract: A micropattern is joined to a substrate (W1) by: a first group of covering step and micropattern forming step by etching in a transfer step; and a second group of covering step and micropattern forming step by etching in the transfer step.

Abstract: A method and device are provided for etching and replacing silicon fins in connection with a FinFET integration process. Embodiments include providing a first plurality and a second plurality of silicon fins on a silicon wafer with an oxide between adjacent silicon fins; forming a first nitride liner on an upper surface of the first plurality of silicon fins and the oxide therebetween; etching the second plurality of silicon fins, forming trenches; removing the first nitride liner; depositing a second nitride liner on an upper surface of the first plurality of silicon fins and the oxide therebetween and in the trenches; removing the second nitride liner down to the upper surface of the first plurality of silicon fins; and recessing the oxide.

Abstract: A method comprises: forming a first array of fins and a second array of fins on a substrate; masking off the first array of fins from the second array of fins with a first mask; depositing a dielectric layer on the second array of fins and on the first mask on the first array of fins; masking off the dielectric layer deposited on the second array of fins with a second mask; removing the dielectric layer and the first mask from the first array of fins; removing the second mask from the second array of fins to expose the dielectric layer on the second array of fins; and depositing a chemox layer on the first array of fins. The chemox layer is thinner than the dielectric layer on the second array of fins.

Abstract: A method of manufacturing a semiconductor device comprises: forming a protective film so as to cover at least a side edge of a substrate; forming a trench, which is annular in shape when viewed oppositely to a first principal surface of the substrate, on the first principal surface by etching using a photoresist pattern; and forming an insulating film so as to fill the trench, to form an insulating ring.

Abstract: A method for forming a pattern according to an embodiment, includes forming a first film pattern having a wide width dimension above a processed film; forming a second film pattern covering a portion of the first film pattern and a third film pattern connected to the second film pattern together above the processed film, the third film pattern having a width dimension narrower than the first film pattern, and to be a line pattern of a line and space pattern; forming a fourth film pattern on a side face of the first film pattern and a plurality of film patterns by the fourth film to be a line pattern of a line and space pattern on both side faces of the third film pattern; and removing the second film pattern and the third film pattern.

Abstract: A method includes providing a substrate with a patterned second layer over a first layer. The second layer includes a second layer opening having a first CD equal to the CD produced by a lithographic system (CDL). CDL is larger than a desired CD (CDD). A third layer is formed to fill the opening, leaving a top surface of the second layer exposed. The second layer is removed to produce a mesa formed by the third layer. The CD of the mesa is equal to about the first CD. The mesa is trimmed to produce a mesa with a second CD equal to about CDD. A fourth layer is formed to cover the first layer, leaving a top of the mesa exposed. The substrate is etched to remove the mesa and a portion of the first layer below the mesa to form an opening in the first layer with CDD.

Abstract: Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin to the first set of fins. The adjacent fin and a nearest fin of the first set of fins have a second pitch larger than the first pitch. The first set of fins and the adjacent fin are sub-lithographic features formed using a sidewall image transfer process.

Abstract: Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises performing at least one etching process to reduce a thickness of a P-active region of a semiconducting substrate to thereby define a recessed P-active region, performing a process in a process chamber to selectively form an as-deposited layer of a semiconductor material on the recessed P-active region, wherein the step of performing the at least one etching process is performed outside of the process chamber, and performing an etching process in the process chamber to reduce a thickness of the as-deposited layer of semiconductor material.