Abstract: A pattern generating method includes: extracting, from a shape of a pattern generated on a substrate, a contour of the pattern shape; setting evaluation points as verification points for the pattern shape on the contour; calculating curvatures on the contour in the evaluation points; and verifying the pattern shape based on whether the curvatures satisfy a predetermined threshold set in advance.

Abstract: A sensor including: a backplate of electrically conductive or semi-conductive material, the backplate including a plurality of backplate holes; a diaphragm of electrically conductive or semi-conductive material that is connected to, and insulated from the backplate, the diaphragm defining a flexible member and an air gap associated with the flexible member; a bond pad formed on an area of the backplate surrounding the cavity; and a bond pad formed on an area of the diaphragm surrounding the air gap; wherein the flexible member and air gap defined by the diaphragm extend beneath the plurality of backplate holes.

Abstract: A single crystal semiconductor layer is formed over a substrate having an insulating surface by the following steps: forming an ion doped layer at a given depth from a surface of a single crystal semiconductor substrate; performing plasma treatment to the surface of the single crystal semiconductor substrate; forming an insulating layer on the single crystal semiconductor substrate to which the plasma treatment is performed; bonding the single crystal semiconductor substrate to the substrate having the insulating surface with an insulating layer interposed therebetween; and separating the single crystal semiconductor substrate using the ion doped layer as a separation surface. As a result, a semiconductor substrate in which a defect in an interface between the single crystal semiconductor layer and the insulating layer is reduced can be provided.

Abstract: Disclosed herein are flash memory devices and methods of making the same. According to one embodiment, a flash memory device includes first trenches formed in a semiconductor substrate and arranged in parallel, second trenches discontinuously formed in the semiconductor substrate and arranged between the first trenches, first isolation structures respectively formed within the first trenches, second isolation structures respectively formed within the second trenches, and active regions defined by the first isolation structures and the second isolation structures.

Abstract: The invention relates to a method for detecting defects, more particularly emergent dislocations of an element having at least one crystalline germanium-base superficial layer. The method comprises an annealing step of the element in an atmosphere having a base that is a mixture of at least an oxidizing gas and a neutral gas enabling selective oxidizing of the emergent dislocations of the crystalline germanium-base superficial layer.

Abstract: The present inventions relate to methods and apparatus for detecting and mechanically removing defects and a surrounding portion of the photovoltaic layer and the substrate in a thin film solar cell such as a Group IBIIIAVIA compound thin film solar cell to improve its efficiency.

Abstract: A method of fabricating materials by epitaxy by epitaxially growing at least one layer of a material upon a composite structure that has at least one thin film bonded to a support substrate and a bonding layer of oxide formed by deposition between the support substrate and the thin film. The thin film and the support substrate have a mean thermal expansion coefficient of 7×10?6 K?1 or more. The bonding layer is formed by low pressure chemical vapor deposition (LPCVD) of a layer of silicon oxide on the bonding face of the support substrate or on the bonding face of the thin film. The thin film has a thickness of 5 micrometers or less while the thickness of the layer of oxide is equal to or greater than the thickness of the thin film. The method also includes a heat treatment carried out at a temperature that is higher than the temperature for deposition of the layer of oxide of silicon and for a predetermined period.

Abstract: An organic EL device includes an insulative film, a first pixel electrode and a second pixel electrode which are disposed on the insulative film, a first light emission layer which is commonly disposed above the first pixel electrode and the second pixel electrode, a second light emission layer which is disposed above the first light emission layer, a counter-electrode which is disposed above the second light emission layer, and an exciton block layer which is disposed between the first light emission layer and the second light emission layer.

Abstract: A photovoltaic cell device, e.g., solar cell, solar panel, and method of manufacture. The device has an optically transparent substrate comprises a first surface and a second surface. A first thickness of material (e.g., semiconductor material, single crystal material) having a first surface region and a second surface region is included. In a preferred embodiment, the surface region is overlying the first surface of the optically transparent substrate. The device has an optical coupling material provided between the first surface region of the thickness of material and the first surface of the optically transparent material.

Abstract: A solar cell includes a substrate layer and a plurality of nanowires grown outwardly from the substrate layer, at least two of the nanowires including a plurality of sub-cells. The solar cell also includes one or more light guiding layers formed of a transparent, light scattering material and filling the area between the plurality of nanowires.

Abstract: Enhanced efficiency solar cells and methods of manufacture of such cells are described herein. In an illustrative example, the solar cell includes at least one or more collector lens bars each of which extend on sides of front contacts and positioned over a respective active area of one or more active areas in such as position as to guide light onto the one or more active areas. A protective layer covers the at least one or more collector lens bars.

Abstract: In order to provide a technique capable of executing an etching process using a dry etching method and a wet etching method in combination with high processing dimensional accuracy, an interlayer insulating film 13, an etching stopper film 14, interlayer insulating films 15 and 18 and a surface protection film 19 are sequentially deposited on a sensor film 12. As the etching stopper film 14, a material different in etching selectivity from the interlayer insulating films 13, 15 and 18 is selected. Next, the surface protection film 19 and the interlayer insulating films 18 and 15 are sequentially dry-etched with using the etching stopper film 14 as an etching stopper, and subsequently, the etching stopper film 14 is dry-etched with using the interlayer insulating film 13 as an etching stopper. Thereafter, the interlayer insulating film 13 is wet-etched with using the sensor film 12 as an etching stopper.

Abstract: Provided are a novel method and a novel structure for bringing a Ge or SiGe compound and a metal into ohmic contact with each other. A semiconductor device is provided with a portion composed of only i) Ge or SiGe compound, ii) a metal, and iii) an insulator or a semiconductor arranged between the material i) and the metal ii). In the semiconductor device, A) the material i) and the metal ii) have Schottky junction in the case where the holes of the material i) are majority carriers, and/or B) the material i) and the metal ii) are in an ohmic contact when the electrons of the material i) are majority carriers.

Abstract: A photoelectric conversion device includes a photoelectric conversion unit which is arranged in a semiconductor substrate, a charge holding portion which is arranged in the semiconductor substrate and temporarily holds a charge generated by the photoelectric conversion unit, a first transfer electrode which is arranged at a position above the semiconductor substrate to transfer a charge generated by the photoelectric conversion unit to the charge holding portion, a charge-voltage converter which is arranged in the semiconductor substrate and converts a charge into a voltage, and a second transfer electrode which is arranged at a position above the semiconductor substrate to transfer a charge held by the charge holding portion to the charge-voltage converter, and the first transfer electrode is arranged to cover the charge holding portion, and not to overlap the second transfer electrode when viewed from a direction perpendicular to the upper surface of the semiconductor substrate.

Abstract: A two-terminal mesa phototransistor and a method for making it are disclosed. The photo transistor has a mesa structure having a substantially planar semiconductor surface. In the mesa structure is a first semiconductor region of a first doping type, and a second semiconductor region of a second doping type opposite to that of the first semiconductor region, forming a first semiconductor junction with the first region. In addition, a third semiconductor region of the first doping type forms a second semiconductor junction with the second region. The structure also includes a dielectric layer. The second semiconductor region, first semiconductor junction, and second semiconductor junction each has an intersection with the substantially planar semiconductor surface. The dielectric covers, and is in physical contact with, all of the intersections.

Abstract: P type semiconductor well regions 8 and 9 for device separation are provided in an upper and lower two layer structure in conformity with the position of a high sensitivity type photodiode PD, and the first P type semiconductor well region 8 at the upper layer is provided in the state of being closer to the pixel side than an end portion of a LOCOS layer 1A, for limiting a dark current generated at the end portion of the LOCOS layer 1A. In addition, the second P type semiconductor well region 9 at the lower layer is formed in a narrow region receding from the photodiode PD, so that the depletion layer of the photodiode PD is prevented from being obstructed, and the depletion is secured in a sufficiently broad region, whereby enhancement of the sensitivity of the photodiode PD can be achieved.

Abstract: A silicide element separates a single crystal silicon node from an underlying silicon substrate, and is capable of acting as a conductive element for interconnecting devices on the device. The single crystal silicon node can act as one terminal of a diode, and a second semiconductor node on top of it can act as the other terminal of the diode. The single crystal silicon node can act as one of the terminals of the transistor, and second and third semiconductor nodes are formed in series on top of it, providing a vertical transistor structure, which can be configured as a field effect transistor or bipolar junction transistor. The silicide element can be formed by a process that consumes a base of a protruding single crystal element by silicide formation processes, while shielding upper portions of the protruding element from the silicide formation process.

Abstract: A semiconductor device comprising a plurality of regions of semiconductor material forming a junction at an interface there-between, the junction including a depletion region having a width which varies spatially in at least one direction along the depletion region. Without limitation, the spatial variation in depletion region width is provided by ionised dopants having a concentration which varies spatially along said at least one direction. Alternatively, or in addition, the spatial variation in depletion region width is achieved by varying the thickness of the region(s) of semiconductor spatially along said at least one direction, for example by creating a plurality of cells within said region(s) devoid of said semiconductor material. A method of fabricating a semiconductor device comprising the step of varying the width of the depletion region spatially there-within in at least one direction along the depletion region.

Abstract: A monolithically integrated MEMS pressure sensor and CMOS substrate using IC-Foundry compatible processes. The CMOS substrate is completed first using standard IC processes. A diaphragm is then added on top of the CMOS. In one embodiment, the diaphragm is made of deposited thin films with stress relief corrugated structure. In another embodiment, the diaphragm is made of a single crystal silicon material that is layer transferred to the CMOS substrate. In an embodiment, the integrated pressure sensor is encapsulated by a thick insulating layer at the wafer level. The monolithically integrated pressure sensor that adopts IC foundry-compatible processes yields the highest performance, smallest form factor, and lowest cost.

Abstract: Disclosed are embodiments of semiconductor wafer structures and associated methods of forming the structures with balanced reflectance and absorption characteristics. The reflectance and absorption characteristics are balanced by manipulating thin film interferences. Specifically, thin film interferences are manipulated by selectively varying the thicknesses of the different films. Alternatively, reflectance and absorption characteristics can be balanced by incorporating an additional reflectance layer into the wafer structure above the substrate.

Abstract: A method reduces a threshold voltage distribution in transistors of a semiconductor memory device, where each transistor includes a nitride liner. The method includes injecting electrons into a charge trap inside and outside the nitride liner of the transistors, and partially removing the electrons injected into the charge trap inside and outside the nitride liner to equalize trapped charges in the transistors.

Abstract: A display apparatus includes a gate electrode, a first insulating layer pattern formed over the gate electrode, a second insulating layer pattern formed over the first insulating layer pattern, exposing a portion of the first insulating layer, a semiconductor film pattern formed over the second insulating layer pattern and over the first insulating layer pattern, an impurity-doped semiconductor film pattern formed on the semiconductor film pattern, wherein the impurity-doped semiconductor film pattern contacts the top surface of the semiconductor film pattern and exposes a portion of the semiconductor film pattern formed over the gate electrode, a source electrode and a drain electrode each formed over a portion of the impurity doped semiconductor film pattern, a protection film pattern formed over the source electrode and the drain electrode in a TFT area, the protection film pattern having a contact hole over the drain electrode, a pixel electrode pattern formed on the protection film pattern and_electrical

Abstract: A semiconductor substrate shaped to have a curved surface profile by anodization. Prior to being anodized, the substrate is finished with an anode pattern on its bottom surface so as to be consolidated into a unitary structure in which the anode pattern is precisely reproduced on the substrate. The anodization utilizes an electrolytic solution which etches out an oxidized portion as soon as it is formed as a result of the anodization, to thereby develop a porous layer in a pattern in match with the anode pattern. The anode pattern brings about an in-plane distribution of varying electric field intensity by which the porous layer develops into a shape complementary to a desired surface profile. Upon completion of the anodization, the curves surface is revealed on the surface of the substrate by etching out the porous layer and the anode pattern from the substrate.

Abstract: An apparatus for deploying two fluids separately into a reaction chamber is provided. The apparatus includes a first distribution network that is formed on a plate having a distribution face and a dispensing face. The first distribution network is defined by a plurality of recessed channels on the distribution face. The plurality of recessed channels includes a plurality of thru-ports that extend from the plurality of recessed channels to the dispensing face. The apparatus further includes a second distribution network that has passages formed below the plurality of recessed channels and above the dispensing face. A first set of ports extends from the passages to the distribution face and a second set of ports extends from a top surface of the distribution face to the dispensing face.

Abstract: Disclosed are a back side illumination image sensor and a method for manufacturing the same. The back side illumination image sensor includes an isolation region and a pixel area on a front side of a first substrate; a photo detector and a readout circuitry on the pixel area; an interlayer dielectric layer and a metal line on the front side of the first substrate; a second substrate bonded to the front side of the first substrate formed with the metal line; a pixel division ion implantation layer on the isolation region at a back side of the first substrate; and a micro-lens on the photo detector at the back side of the first substrate.

Abstract: A thin film type solar cell and a method for manufacturing the same is disclosed, which is capable of providing a wide light-transmission area without lowering cell efficiency and increasing processing time, so that the solar cell can be used as a substitute for a glass window in a building. The thin film type solar cell generally comprises a substrate; a plurality of front electrodes at fixed intervals on the substrate; a plurality of semiconductor layers at fixed intervals with a contact portion or separating channel interposed in-between, the plurality of semiconductor layers on the plurality of front electrodes; and a plurality of rear electrodes at fixed intervals by the each separating channel interposed in-between, the each rear electrode being electrically connected with the each front electrode; wherein the each rear electrode is patterned in such a way that a light-transmitting portion is included in a predetermined portion of the rear electrode.

Abstract: An image sensor and a method of fabricating an image sensor. A method of fabricating an image sensor may include forming a plurality of photodiodes on and/or over a semiconductor substrate, a filter array including color filters arranged corresponding to upper parts of photodiodes, a plurality of hydrophilic lenses arranged over a filter array spaced apart from one another, and/or a plurality of hydrophobic lenses arranged over a filter array between hydrophilic lenses. A curvature of a lens may be substantially equal in a horizontal, vertical and/or diagonal direction.

Abstract: In some embodiments, a method of doping a semiconductor wafer disposed on a pedestal electrode in an inductive plasma chamber includes generating a plasma having a first voltage with respect to ground in the inductive plasma chamber, and applying a radio frequency (RF) voltage with respect to ground to the pedestal electrode in the inductive plasma chamber. The positive RF voltage is based on the first voltage of the plasma.

Abstract: An image sensor includes a photodiode arranged over a semiconductor substrate, a core layer for an optical waveguide, to allow incident light to move toward the photodiode, the core layer being arranged over the photodiode, a clad layer for the optical waveguide, having a lower refractive index than the core layer to reflect the incident light to the photodiode, the clad layer being arranged over the side core layer, and a dielectric layer arranged over a side of the clad layer. An optical waveguide having a uniform refractive index and a flat light-reflection surface can be formed using semiconductor materials such as InP, InGaAsP, SiO2, SiON and PMMA. Furthermore, the optical waveguide can control a refractive index and thus reduce light loss, and a buffer layer can be simply formed by using a polymer.

Abstract: Disclosed are a light emitting device having a plurality of non-polar light emitting cells and a method of fabricating the same. This method comprises preparing a first substrate of sapphire or silicon carbide having an upper surface with an r-plane, an a-plane or an m-plane. The first substrate has stripe-shaped anti-growth patterns on the upper surface thereof, and recess regions having sidewalls of a c-plane between the anti-growth patterns. Nitride semiconductor layers are grown on the substrate having the recess regions, and the nitride semiconductor layers are patterned to form the light emitting cells separated from one another. Accordingly, there is provided a light emitting device having non-polar light emitting cells with excellent crystal quality.

Abstract: An image sensor includes a semiconductor substrate, an interconnection and an interlayer dielectric, an image sensing device, a trench, a buffer layer, a barrier pattern, a via hole, and a metal contact. The semiconductor substrate includes a readout circuitry. The interconnection and an interlayer dielectric layer are formed on and/or over the semiconductor substrate while the interconnection is connected to the readout circuitry. The image sensing device may be formed on and/or over the interlayer dielectric and a trench may be formed in the image sensing device, the trench corresponding to the interconnection. The buffer layer may be formed on a sidewall of the trench. The barrier pattern may be formed on the buffer layer with the via hole penetrating through the image sensing device and the interlayer dielectric under the barrier pattern and exposing the interconnection. The metal contact may be formed in the via hole.

Abstract: A method that includes forming an opening between at least one first electrode and a second electrode by forming a recess in a first electrode layer, the recess having sidewalls that correspond to a surface of the at least one first electrode, forming a first sacrificial layer on the sidewalls of the recess, the first sacrificial layer having a first width that corresponds to a second width of the opening, forming a second electrode layer in the recess that corresponds to the second electrode, and removing the first sacrificial layer to form the opening between the second electrode and the at least one first electrode.

Abstract: In a method of manufacturing an inkjet head, a silicon dioxide (SiO2) layer is produced on the surface of first silicon member formed from single-crystal silicon. Next, a glass layer formed of borosilicate glass or the like is sputtered onto the surface of the silicon dioxide (SiO2) layer. A silicon oxide (SiOx, x<2) layer is then formed on the surface of a second silicon member. The first and second silicon members and are bonded together by applying heat at about 450° C. with heaters, as a DC voltage is applied across electrode terminals. As a result, a silicon dioxide (SiO2) layer is formed at the interface of the glass layer and silicon oxide (SiOx, x<2) layer, anodically bonding the two layers.

Abstract: The current invention provides methods of fabricating a capacitive micromachined ultrasonic transducer (CMUT) that includes oxidizing a substrate to form an oxide layer on a surface of the substrate having an oxidation-enabling material, depositing and patterning an oxidation-blocking layer to form a post region and a cavity region on the substrate surface and remove the oxidation-blocking layer and oxide layer at the post region. The invention further includes thermally oxidizing the substrate to grow one or more oxide posts from the post region, where the post defines the vertical critical dimension of the device, and bonding a membrane layer onto the post to form a membrane of the device. A maximum allowed second oxidation thickness t2 can be determined, that is partially based on a desired step height and a device size, and a first oxidation thickness t1 can be determined that is partially based on the determined thickness t2.

Abstract: A method is disclosed for enhancing tensile stress in the channel region of a semiconductor structure. The method includes performing a series of ion implantation steps at predetermined implant energies to implant carbon ions deep within the semiconductor structure to create a strain layer. The strain layer is annealed using a millisecond anneal process. Subsequent ion implantation steps are used to dope the source/drain region, and the source/drain extension with phosphorus ions, so that the doped regions remain above the strain layer. A second millisecond anneal step activates the source/drain region and the source/drain extension. The strain layer enhances carrier mobility within a channel region of the semiconductor structure, while also preventing diffusion of P within the structure.

Abstract: A harsh environment transducer including a substrate having a first surface and a second surface, wherein the second surface is in communication with the environment. The transducer includes a device layer sensor means located on the substrate for measuring a parameter associated with the environment. The sensor means including a single crystal semiconductor material having a thickness of less than about 0.5 microns. The transducer further includes an output contact located on the substrate and in electrical communication with the sensor means. The transducer includes a package having an internal package space and a port for communication with the environment. The package receives the substrate in the internal package space such that the first surface of the substrate is substantially isolated from the environment and the second surface of the substrate is substantially exposed to the environment through the port.

Abstract: A monolithic LED chip is disclosed comprising a plurality of junctions or sub-LEDs (“sub-LEDs”) mounted on a submount. The sub-LEDs are serially interconnected such that the voltage necessary to drive the sub-LEDs is dependent on the number of serially interconnected sub-LEDs and the junction voltage of the sub-LEDs. Methods for fabricating a monolithic LED chip are also disclosed with one method comprising providing a single junction LED on a submount and separating the single junction LED into a plurality of sub-LEDs. The sub-LEDs are then serially interconnected such that the voltage necessary to drive the sub-LEDs is dependent on the number of the serially interconnected sub-LEDs and the junction voltage of the sub-LEDs.

Abstract: The present invention provides a group III nitride semiconductor light emitting device and a method for producing the same. The group III nitride semiconductor light emitting device comprises (a1), (b1) and (c1) in this order: (a1) an N electrode, (b1) a semiconductor multi-layer film, (c1) a transparent electric conductive oxide P electrode, wherein the semiconductor multi-layer film comprises an N-type semiconductor layer, light emitting layer, P-type semiconductor layer and high concentration N-type semiconductor layer having an n-type impurity concentration of 5×1018 cm?3 to 5×1020 cm?3 in this order, the N-type semiconductor layer is in contact with the N electrode, and the semiconductor multi-layer film has a convex.

Abstract: Disclosed is a method of fabricating a display device. The method includes providing a substrate in which a display region and a pad region formed around the display region are defined, forming a conductive layer on the substrate, forming a mask pattern by rolling a roller on the conductive layer, and patterning the conductive layer using the mask pattern to form a line in the display region and a pad in the pad region. The pad is formed of a pattern having a second width corresponding to a first width of the line.

Abstract: In some embodiments of the invention, encapsulated semiconducting nanomaterials are described. In certain embodiments the nanostructures described are semiconducting nanomaterials encapsulated with ordered carbon shells. In some aspects a method for producing encapsulated semiconducting nanomaterials is disclosed. In some embodiments applications of encapsulated semiconducting nanomaterials are described.

Abstract: A solar panel can include a substrate with layers of droplets of different materials disposed on a surface of the substrate. An outer layer can be disposed away from the surface and can comprise a face of the solar panel. The layers can comprise a cathode electrode and an anode electrode disposed between the outer layer and the surface of the substrate. The layers can further comprise a P region and an N region. The P region can be disposed at least partially around the anode electrode. The N region can be disposed at least partially around the P region and at least partially around the cathode electrode. The P region and the N region can comprise droplets of a P material comprising P-doped semiconductor particles and an N material comprising N-doped semiconductor particles respectively.

Abstract: A C4 grind tape and a laser-ablative adhesive layer are formed on a front side of a semiconductor substrate. A carrier substrate is thereafter attached to the laser-ablative adhesive layer. The back side of the semiconductor substrate is thinned by polishing or grinding, during which the carrier substrate provides mechanical support to enable thinning of the semiconductor substrate to a thickness of about 25 ?m. A film frame tape is attached to the back side of the thinned semiconductor substrate and the laser-ablative adhesive layer is ablated by laser, thereby dissociating the carrier substrate from the back side of the C4 grind tape. The assembly of the film frame tape, the thinned semiconductor substrate, and the C4 grind tape is diced. The C4 grind tape is irradiated by ultraviolet light to become less adhesive, and is subsequently removed.

Abstract: Disclosed are a light emitting device having a plurality of light emitting cells and a method of fabricating the same. The light emitting device comprises a plurality of light emitting cells positioned on a substrate to be spaced apart from one another. Each of the light emitting cells comprises a first conductive-type upper semiconductor layer, an active layer and a second conductive-type lower semiconductor layer. Electrodes are positioned between the substrate and the light emitting cells, and each of the electrodes has an extension extending toward adjacent one of the light emitting cells. An etching prevention layer is positioned in regions between the light emitting cells and between the electrodes. Each wire has one end connected to the upper semiconductor layer and the other end connected to the electrode through the etching prevention layer.

Abstract: A method for preparing nanocrystals is disclosed. The method includes synthesizing colloidal semiconductor nanocrystal cores, and adding a metal salt to the colloidal semiconductor nanocrystal cores and heating the mixture while maintaining the reaction temperature constant. During the reaction, the surfaces of the semiconductor nanocrystal cores are etched (‘in-situ etching’) and metal-surfactant layers are formed on the etched surface portions of the semiconductor nanocrystal cores. The metal-surfactant layers are derived from the metal salt. Nanocrystals prepared by the method have minimal surface defects and exhibit high luminescence efficiency and good stability.

Abstract: Provided are a micro-electromechanical systems (MEMS) microphone and a method of manufacturing the same. A manufacturing process is simplified compared to a conventional art using both upper and lower substrate processes. Since defects which may occur during manufacturing are reduced due to the simplified manufacturing process, the manufacturing throughput is improved, and since durability of the MEMS microphone is improved, system stability against the external environment is improved.

Abstract: A gate insulating film (13) is formed on a substrate (1) so as to cover a gate electrode (11), and an amorphous silicon film (semiconductor thin film) (15) is further formed. A light absorption layer (19) is formed thereon through a buffer layer (17). Energy lines Lh are applied to the light absorption layer (19) from a continuous-wave laser such as a semiconductor laser. This oxidizes only a surface side of the light absorption layer Lh and produces a beautiful crystalline silicon film (15a) obtained by crystallizing the amorphous silicon film (15) using heat generated by thermal conversion of the energy lines Lh at the light absorption layer (19) and heat of the oxidation reaction. This provides a method for crystallizing a thin film with good controllability at low costs achieved with simpler process.

Abstract: A method of manufacturing a plurality of electro-optical devices by notching, dicing, and cutting a composite substrate obtained by adhering a first substrate and a second substrate which faces the first substrate with an electro-optical layer interposed therebetween.

Abstract: Disclosed are methods of making fine patterns by exploiting difference in threshold laser fluence of materials and a thin film transistor (TFT) fabrication methods using the same, and more particularly, to a method of forming a fine pattern and a method of fabricating a TFT through the same method, in which a plurality of layers different in threshold laser fluence are stacked and then exposed to a laser so that a layer having a low threshold laser fluence can be selectively removed, thereby making fine patterns precisely and forming a cavity of a gate electrode precisely and easily.

Abstract: The present invention discloses a MEMS device with particles blocking function, and a method for making the MEMS device. The MEMS device comprises: a substrate on which is formed a MEMS device region; and a particles blocking layer deposited on the substrate.

Abstract: A protruding structure having a linear edge is formed on a substrate. The protruding structure may be a gate line of a field effect transistor. A stress-generating liner is deposited on the substrate. A non-photosensitive self-assembling block copolymer layer containing at least two immiscible polymeric block components is deposited on the stress-generating liner, and is annealed to allow phase separation of immiscible components. The polymeric resist is developed to remove at least one of the at least two polymeric block components, which formed a pattern of nested lines due to the linear edge of the protruding structure. Linear nanoscale stripes are formed in the polymeric resist which is self-aligning and self-assembled. The stress-generating layer is patterned into linear stress-generating stripes having a sublithographic width.