Abstract: A method for producing a thin film includes the following steps: providing a primary substrate; forming an etching stop layer on the primary substrate; forming a sacrificial layer on the etching stop layer; implanting gas ions to form an ion implantation peak layer, which defines an effective transferred layer and a remnant layer; and separating the effective transferred layer from the remnant layer. The thickness of the effective transferred layer can be effectively determined by controlling the thickness of the sacrificial layer. Moreover, the thickness of the effective transferred layer can be uniform and then the effective transferred layer can become a nanoscale thin film.

Abstract: A method for providing a tuned repair for damage to a silicon based low-k dielectric layer with organic compounds, where damage replaces a methyl attached to silicon with a hydroxyl attached to silicon is provided. A precursor gas is provided, comprising a first repair agent represented as Si—(R)x(OR?)y, where y?1 and x+y=4, and wherein R is an alkyl or aryl group and R? is an alkyl or aryl group and a second repair agent represented as Si—(R)x(OR?)yR?, where y?1 and x+y=3, and wherein R is an alkyl or aryl group and R? is an alkyl or aryl group, and R? is of a group that reduces interfacial surface tension between a wet clean chemical and the low-k dielectric. Some of the first repair agent and second repair agent are bonded to the low-k dielectric to form a monolayer of the first repair agent and the second repair agent.

Abstract: A process for obtaining a hybrid substrate that includes at least one active layer of Group III/N material for applications in the field of electronics, optics, photovoltaics or optoelectronics. The method includes selecting a source substrate of Group III/N material having a hexagonal single crystal crystallographic structure; carrying out an implantation of He+ helium ions into the source substrate through an implantation face which lies in a plane approximately parallel with the “c” crystallographic axis of the material, at an implantation dose equal to or greater than 1×1016 He+/cm2 and 1×1017 He+/cm2, to form therein a number of nanocavities defining a weakened zone which delimits the active layer; and transferring the active layer by applying an overall energy budget capable of causing detachment of the layer from the source substrate, wherein the budget also causes the nanocavities to grow into cavities.

Abstract: A nitride semiconductor laser device is formed by growing a group III nitride semiconductor multilayer structure on a substrate. The group III nitride semiconductor multilayer structure has a laser resonator including an n-type semiconductor layer, a p-type semiconductor layer and a light emitting layer held between the n-type semiconductor layer and the p-type semiconductor layer. The laser resonator is arranged to be offset from the center with respect to a device width direction orthogonal to a resonator direction toward one side edge of the device. A wire bonding region having a width of not less than twice the diameter of an electrode wire to be bonded to the device is formed between the laser resonator and the other side edge of the device.

Abstract: Methods of processing films on substrates are provided. In one aspect, the methods comprise treating a patterned low dielectric constant film after a photoresist is removed form the film by depositing a thin layer comprising silicon, carbon, and optionally oxygen and/or nitrogen on the film. The thin layer provides a carbon-rich, hydrophobic surface for the patterned low dielectric constant film. The thin layer also protects the low dielectric constant film from subsequent wet cleaning processes and penetration by precursors for layers that are subsequently deposited on the low dielectric constant film.

Abstract: Methods for bonding a first substrate to a second substrate are described. A surface of the first substrate is coated with an adhesive layer. The adhesive layer is cured to b-stage. The surface of the first substrate is positioned in contact with the second substrate. An edge of the first substrate is pressed to an edge of the second substrate to initiate Van der Waals bonding. The first and second substrates are allowed to come together by Van der Waals bonding. The bonded first and second substrates are subjected to a sufficient heat for a sufficient time period to cure completely the adhesive layer.

Abstract: A method of processing a substrate having horizontal and non-horizontal surfaces is disclosed. The substrate is implanted with particles using an ion implanter. During the ion implant, due to the nature of the implant process, a film may be deposited on the surfaces, wherein the thickness of this film is thicker on the horizontal surfaces. The presences of this film may adversely alter the properties of the substrate. To rectify this, a second process step is performed to remove the film deposited on the horizontal surfaces. In some embodiments, an etching process is used to remove this film. In some embodiments, a material modifying step is used to change the composition of the material comprising the film. This material modifying step may be instead of, or in addition to the etching process.

Abstract: A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner.

Abstract: A solar cell device of improved efficiency consists of a photovoltaic solar cell and an efficiency-improving antireflective nanocoating film that is applied on the solar cell and interacts with the photovoltaic process of the cell. The coating film has a thickness ranging from 100 nm to 100 ?m, and comprises a dielectric material that contains metal nanoparticles having dimensions from 4.5 to 10 nm and concentration ranging from 1 to 5%. The effect of improved efficiency is presumably obtained due to organization of nanoparticles into specific clusters. The method of manufacturing the solar-cell device of the invention comprises preparation of the polymer solution that contains uniformly dispersed metal nanoparticles of silver, gold, or another diamagnetic metal and forming the aforementioned coating film by heat-treating and drying the applied solution under specific conditions.

Abstract: An elementary device to generate electric energy including a photovoltaic converter and a thermoelectric converter. The photovoltaic converter includes a stack of layers, resting on a supporting substrate in heat-insulating material, including a first conductive layer as an upper electrode, and a second conductive layer as a lower electrode, the upper and lower electrodes sandwiching a layer in photoactive material between them. The thermoelectric converter includes a third conductive layer acting as a hot junction and a fourth conductive layer acting as a cold junction, the hot and cold junctions sandwiching between them an element in thermoelectric and electrically conductive material. The thermoelectric and electrically conductive element is included in the thickness of the supporting substrate, so that one end is in contact with the hot junction and the other end is in contact with the cold junction.

Abstract: MEMS resonators containing a first material and a second material to tailor the resonator's temperature coefficient of frequency (TCF). The first material has a different Young's modulus temperature coefficient than the second material. In one embodiment, the first material has a negative Young's modulus temperature coefficient and the second material has a positive Young's modulus temperature coefficient. In one such embodiment, the first material is a semiconductor and the second material is a dielectric. In a further embodiment, the quantity and location of the second material in the resonator is tailored to meet the resonator TCF specifications for a particular application. In an embodiment, the second material is isolated to a region of the resonator proximate to a point of maximum stress within the resonator. In a particular embodiment, the resonator includes a first material with a trench containing the second material.

Abstract: A method for forming a semiconductor device is disclosed. The device includes a control electrode on a semiconductor P-channel layer having at least a gate dielectric layer. The gate dielectric layer has an exponentially decreasing density of defect levels Et in as function of energy from the band edges of the adjacent layer (the semiconductor P-channel layer or optionally the capping layer) toward the center of the bandgap of this layer. The method includes selecting at least one parameter of the P-channel semiconductor device such that the inversion carrier injection into the distribution of defect levels deviates from the energy level at the center of the bandgap of a layer adjacent the gate dielectric layer at the same side of the gate dielectric layer as the P-channel layer, with a value not more than about 49%, such as not more than about 40%, for example not more than about 20%, not more than about 10%, even not more than about 5% of that bandgap in eV. In one aspect, this allows reducing NBTI.

Abstract: A method of forming a thermal bend actuator in an inkjet nozzle assembly. The method includes: depositing sidewalls and a roof layer to define a nozzle chamber; defining first and second vias in one sidewall to reveal first and second electrodes; filling the vias with a conductive material using electroless plating to provide first and second connector posts; depositing an active beam material onto the roof layer; etching the active beam material to define a planar active beam member comprising a bent or serpentine beam element; and etching the roof layer to define the thermal bend actuator.

Abstract: A method of fabricating MEMS device includes: providing a substrate with a first surface and a second surface. The substrate includes at least one logic region and at least one MEMS region. The logic region includes at least one logic device positioned on the first surface of the substrate. Then, an interlayer material is formed on the first surface of the substrate within the MEMS region. Finally, the second surface of the substrate within the MEMS region is patterned. After the pattern process, a vent pattern is formed in the second surface of the substrate within the MEMS region. The interlayer material does not react with halogen radicals. Therefore, during the formation of the vent pattern, the substrate is protected by the interlayer material and the substrate can be prevented from forming any undercut.

Abstract: A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material.

Abstract: A semiconductor laser device includes a substrate 11 having a (1-100) oriented principal surface, a semiconductor multilayer structure 12 formed on the substrate 11 and having a stripe-shaped optical waveguide, and a plurality of pyramidal protrusions 13 formed at least on a part of a light emitting facet of the substrate 11. The light emitting facet has a (000-1) plane orientation.

Abstract: A method for surface treatment of a group III nitride crystal includes the steps of lapping a surface of a group III nitride crystal using a hard abrasive grain with a Mohs hardness higher than 7, and abrasive-grain-free polishing the lapped surface of the group III nitride crystal using a polishing solution without containing abrasive grain, and the polishing solution without containing abrasive grain has a pH of not less than 1 and not more than 6, or not less than 8.5 and not more than 14. Accordingly, the method for surface treatment of a group III nitride crystal can be provided according to which hard abrasive grains remaining at the lapped crystal can be removed to reduce impurities at the crystal surface.

Abstract: A seal (40) for sealing an interface between a container and a lid of a process chamber. The seal (40) comprises a metallic or polymeric sealing element (50) and an elastomeric sealing element (60) that are arranged to seal the interface in series, with the metallic or polymeric sealing element (50) being situated to encounter processing activity upstream of the elastomeric sealing element (60).

Abstract: Optical modulator utilizing wafer bonding technology. An embodiment of a method includes etching a silicon on insulator (SOI) wafer to produce a first part of a silicon waveguide structure on a first surface of the SOI wafer, and preparing a second wafer, the second wafer including a layer of crystalline silicon, the second wafer including a first surface of crystalline silicon. The method further includes bonding the first surface of the second wafer with a thin oxide to the first surface of the SOI wafer using a wafer bonding technique, wherein a second part of the silicon waveguide structure is etched in the layer of crystalline silicon.

Abstract: An integrated circuit (IC) having a microelectromechanical system (MEMS) device buried therein is provided. The integrated circuit includes a substrate, a metal-oxide semiconductor (MOS) device, a metal interconnect, and the MEMS device. The substrate has a logic circuit region and a MEMS region. The MOS device is located on the logic circuit region of the substrate. The metal interconnect, formed by a plurality of levels of wires and a plurality of vias, is located above the substrate to connect the MOS device. The MEMS device is located on the MEMS region, and includes a sandwich membrane located between any two neighboring levels of wires in the metal interconnect and connected to the metal interconnect.

Abstract: A capacitive accelerometer having one or more micromachined acceleration sensor assembly is disclosed. The acceleration sensor assembly comprises a spring-mass-support structure, a top cap and a bottom cap. The proof mass plate of the spring-mass-support structure has cutout spaces and is supported by a pair of branched torsional beams which are substantially located in the cutout spaces. The torsional axis of the proof mass plate is offset from the mass center in direction perpendicular to the proof mass plate. The acceleration sensor assembly further comprises multiple coplanar electrodes for differential capacitive sensing and electrostatic forcing. The capacitive accelerometer according to the present invention may comprise one, two or six micromachined acceleration sensor assemblies with electronic signal detection, conditioning and control circuits in different configurations and applications to detect and measure linear and angular accelerations.

Abstract: Field effect transistors described herein include first and second terminals vertically separated by a channel region. The first and second terminals comprise first and second silicide elements respectively. The first silicide element prevents the migration of carriers from the first terminal into the underlying semiconductor body or adjacent devices which can activate parasitic devices. The first silicide element is also capable of acting as a low resistance conductive line for interconnecting devices or elements. The second silicide element provides a low resistance contact between the second terminal and overlying elements.

Abstract: Provided are a method of manufacturing a group-III nitride semiconductor light-emitting device in which a light-emitting device excellent in the internal quantum efficiency and the light extraction efficiency can be obtained, a group-III nitride semiconductor light-emitting device and a lamp. Included are an epitaxial step of forming a semiconductor layer (30) so as to a main surface (20) of a substrate (2), a masking step of forming a protective film on the semiconductor layer (30), a semiconductor layer removal step of removing the protective film and the semiconductor layer (30) by laser irradiation to expose the substrate (2), a grinding step of reducing the thickness of the substrate (2), a polishing step of polishing the substrate (2), a laser processing step of providing processing marks to the inside of the substrate (2), a division step of creating a plurality of light-emitting devices (1) while forming a division surface of the substrate (2) to have a rough surface.

Abstract: A method of manufacturing a surface emitting laser element of a vertical cavity type in accordance with the present invention is characterized in that comprises the following steps of: applying a process of accumulations on a substrate, the process sequentially including accumulating a reflecting mirror of a multilayered film layer at a lower side thereof on to the substrate, and accumulating layers of a semiconductor as a plurality thereof on to the reflecting mirror of the multilayered film layer at the lower side thereof, that comprises an active layer and that further comprises a contact layer at a top layer thereof as well; forming a first layer of a dielectric substance as a process of a formation of the first layer of the dielectric substance at a part of regions on the contact layer; forming an electrode of an annular shape as a process of a formation of the electrode of the annular shape on the contact layer, that has an open part at a center thereof, in order to be arranged for the first layer of th

Abstract: The present invention provides a manufacturing method by which a substrate (typically, a TFT substrate) can be installed directly in a treatment apparatus by using a transfer container without transferring the substrate. It is possible to use the container efficiently and transfer different substrates in size with one container. A manufacturing method in which a substrate is directly installed in an electrostatic-protected transfer container by a substrate supplier, and then the container is directly installed a treatment apparatus by a substrate demander after transferring can be realized, thereby making it possible to transfer substrates such as a TFT substrate. A contamination of a substrate due to particles and electrostatic discharge damage of a TFT substrate can be avoided because a transferring operation is not needed.

Abstract: A system for processing a semiconductor substrate is provided. The system includes a mainframe having a plurality of modules attached thereto. The modules include processing modules, storage modules, and transport mechanisms. The processing modules may include combinatorial processing modules and conventional processing modules, such as surface preparation, thermal treatment, etch and deposition modules. In one embodiment, at least one of the modules stores multiple masks. The multiple masks enable in-situ variation of spatial location and geometry across a sequence of processes and/or multiple layers of a substrate to be processed in another one of the modules. A method for processing a substrate is also provided.

Abstract: According to the present invention, there is provided a semiconductor device fabrication method comprising, bringing a mold having a predetermined pattern into contact with at least a portion of an imprinting material formed on a substrate to be processed, and forming the pattern on the substrate to be processed by sequentially transferring the pattern for each shot, wherein one of a dicing region and a monitor pattern formation region of the substrate to be processed is coated with the imprinting material.

Abstract: Provided are a semiconductor device manufacturing method and a substrate processing apparatus. The method comprise: a first process of forming a film containing a predetermined element on a substrate by supplying a source gas containing the predetermined element to a substrate processing chamber in which the substrate is accommodated; a second process of removing the source gas remaining in the substrate processing chamber by supplying an inert gas to the substrate processing chamber; a third process of modifying the predetermined element-containing film formed in the first process by supplying a modification gas that reacts with the predetermined element to the substrate processing chamber; a fourth process of removing the modification gas remaining in the substrate processing chamber by supplying an inert gas to the substrate processing chamber; and a filling process of filling an inert gas in a gas tank connected to the substrate processing chamber.

Abstract: An optical device having a structured active region configured for one or more selected wavelengths of light emissions and formed on an off-cut m-plane gallium and nitrogen containing substrate.

Abstract: A system and method for an electrically pumped laser system is disclosed. The system includes a silicon micro-ring resonator 405. A quantum well 412 formed of a III-V group semiconductor material is optically coupled with the micro-ring resonator 405 to provide optical gain. A trapezoidal shaped buffer 414 formed of a III-V group semiconductor material and doped with a first type of carrier is optically coupled to the quantum well 412. A ring electrode 410 is coupled to the trapezoidal shaped buffer 414. The trapezoidal shaped buffer 414 enables the ring electrode 410 to be substantially isolated from an optical mode of the micro-ring resonator 405.

Abstract: A semiconductor laser device includes a semiconductor multilayer structure 12 having a stripe-shaped ridge waveguide portion 12a extending in a direction intersecting a cavity end face. A dielectric layer 16 is formed on the semiconductor multilayer structure 12 to cover at least part of both side faces of the ridge waveguide portion 12a. Light absorption layers 17 are formed on both sides of the ridge waveguide portion 12a on the semiconductor multilayer structure 12 so as to be spaced from the ridge waveguide portion 12a and the cavity end face.

Abstract: In a high-power diode laser, facets which lie opposite one another contain in each case an amorphous layer system composed of silicon and carbon. The layer system is formed to perform the function both of a passivation layer and of the reflection-determining functional layers. This measure makes it possible to produce a high-power diode laser having a high COD threshold in conjunction with a long service life by way of a simplified method.

Abstract: A method for forming a metal oxide thin film pattern using nanoimprinting according to one embodiment of the present invention includes: coating a photosensitive metal-organic material precursor solution on a substrate; pressurizing the photosensitive metal-organic material precursor coating layer to a mold patterned to have a protrusion and depression structure; forming the metal oxide thin film pattern by irradiating ultraviolet rays to the pressurized photosensitive metal-organic material precursor coating layer to cure it; and removing the patterned mold from the metal oxide thin film pattern.

Abstract: An active device array mother substrate including a substrate, pixel arrays, and a polymer-stabilized alignment curing circuit is provided. The substrate has panel regions, a circuit region, a first cutting line, and a second cutting line. The first cutting line is disposed on the circuit region between an edge of the substrate and the second cutting line. The active devices of the pixel arrays have a semiconductor layer. The polymer-stabilized alignment curing circuit disposed on the circuit region includes curing pads disposed between the edge of the substrate and the first cutting line and curing lines having an upper conductive layer connected to the corresponding curing pads and the corresponding pixel array. The upper conductive layer is in the same layer as the source/drain conductor. Therefore, the curing lines are capable of preventing problems such as peeling, so as to keep the polymer-stabilized alignment curing circuit operating normally.

Abstract: A well (2) doped for a conductivity type and provided as the sensor region is formed in a substrate (1) made of semiconductor material. Contact regions (4), arranged spaced apart from one another and doped for the same conductivity type as the well (2), are formed in a cover layer (3) that delimits the region with the conductivity type of the well. The contact areas (4) are electroconductively connected to the well (2) and provided for terminal contacts (6).

Abstract: A neutron detector, or array of neutron detectors, and method for fabricating same, having active region comprised of inorganic materials such as semiconductors and/or small particles and/or molecules. The detector active region is comprised of a layer or multi-layer heterojunction structure such as p-n junction wherein at least one layer comprises a composite of host semiconductor material in which neutron sensitizing guest material is distributed in all directions throughout the host semiconductor. This composite layer contains neutron capturing atoms such as 10B, 6Li, 157Gd, 235U, 239Pu, 51V , and 103Rh. The semiconductor host and other semiconductor layers transports carriers excited as a result of neutron absorption in the detector active region.

Abstract: A method of manufacturing a semiconductor composite device, including steps of: preparing a substrate comprising circuit elements, which are part of a driving circuit; attaching an array of driven elements onto the substrate via a passivation layer, the array being formed of a semiconductor thin film having a crystal structure wherein the driven elements are arrayed to be driven by the driving circuit; and forming a metal wire by a photo-lithography method such that the circuit elements are electrically connected with the metal wire to form the driving circuit and the driving circuit is electrically connected to the driven elements with the metal wire.

Abstract: A method for fabricating an image sensor is described. A substrate is provided. Multiple photoresist patterns are formed over the substrate, and then a thermal reflow step is performed to convert the photoresist patterns into multiple microlenses arranged in an array. The focal length of the microlens increases from the center of the array toward the edge of the array.

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Abstract: In preferred embodiments, this invention provides a semiconductor structure that has a semi-conducting support, an insulating layer arranged on a portion of the support and a semi-conducting superficial layer arranged on the insulating layer. Electronic devices can be formed in the superficial layer and also in the exposed portion of the semi-conducting bulk region of the substrate not covered by the insulating layer. The invention also provides methods of fabricating such semiconductor structures which, starting from a substrate that includes a semi-conducting superficial layer arranged on a continuous insulating layer both of which being arranged on a semi-conducting support, by transforming at least one selected region of a substrate so as to form an exposed semi-conducting bulk region of the substrate.

Abstract: Disclosed is a substrate processing apparatus, comprising a processing chamber, a holder to hold at least a plurality of product substrates, a heating member, a supplying member to alternately supply at least a first reactant and a second reactant, and a control unit, wherein the control unit executes forming thin films on the substrates by supplying the first reactant, removing a surplus of the first reactant after the first reactant has been adsorbed on the product substrates, subsequently supplying the second reactant, to cause the second reactant to react with the first reactant adsorbed on the substrates, and executes the forming the thin films in a state where a number of the product substrates is insufficient when a number of the product substrates is less than a maximum number of the product substrates which can be held by the holder.

Abstract: A quantum well infrared photodetector comprising a tunable voltage source; first and second contacts operatively connected to the tunable voltage source; a substantially-transparent substrate adapted to admit light; first and second layers operatively connected to the first and second contacts; a quantum well layer positioned between the first and second layers; light admitted through the substantially transparent substrate entering at least one of the first and second layers and passing through the quantum well layer; at least one side wall adjacent to at least one of the first and second layers and the quantum well layer; the at least one side wall being substantially non-parallel to the incident light; the at least one sidewall comprising reflective layer which reflects light into the quantum well layer for absorption.

Abstract: A VCSEL with undoped mirrors. An essentially undoped bottom DBR mirror is formed on a substrate. A periodically doped first conduction layer region is formed on the bottom DBR mirror. The first conduction layer region is heavily doped at a location where the optical electric field is at about a minimum. An active layer, including quantum wells, is on the first conduction layer region. A periodically doped second conduction layer region is connected to the active layer. The second conduction layer region is heavily doped where the optical electric field is at a minimum. An aperture is formed in the epitaxial structure above the quantum wells. A top mirror coupled to the periodically doped second conduction layer region. The top mirror is essentially undoped and formed in a mesa structure. An oxide is formed around the mesa structure to protect the top mirror during wet oxidation processes.

Abstract: A light emitting device includes: a conductive substrate; a metal film provided above the conductive substrate; a light emitting layer provided above the metal film; an electrode provided partly above the light emitting layer; and a current suppression layer being in contact with the metal film, provided in a region including at least part of an immediately underlying region of the electrode, and configured to suppress current, a first portion of the metal film including at least part of a portion located between the current suppression layer and the electrode, being separated from an portion other than the first portion.

Abstract: A structure with an integrated circuit (IC) and a silicon condenser microphone mounted thereon includes a substrate having a first area and a second area. The IC is fabricated on the first area in order to form a conducting layer and an insulation layer. Both the conducting layer and the insulation layer further extend to the second area. The insulation layer is removed under low temperature in order to expose the conducting layer on which the silicon condenser microphone is fabricated. The silicon condenser microphone includes a first film layer, a connecting layer and a second film layer under a condition that the connecting layer connects the first and the second film layers. The first film layer and the second film layer act as two electrodes of a variable capacitance.

Abstract: A method of forming a film pattern with micro-pattern and a method of manufacturing a thin film transistor liquid crystal display (TFT-LCD) array substrate are provided. The method of manufacturing the film pattern with micro-pattern comprises: depositing a thin film on a substrate; jetting or dropping etchant on the thin film with a predetermined etching pattern by an inkjet print device; etching the thin film by the etchant; and cleaning the thin film to form a film pattern on the substrate.

Abstract: A support having a larger density of crystalline defects, an insulating layer disposed on a first region of a front face of the support, and a superficial layer disposed on the insulating layer. An additional layer can be disposed at least on a second region of the front face of the support has a thickness sufficient to bury crystalline defects of the support. A substrate can also include an epitaxial layer arranged at least over the first region of the front face of the support, between the support and the insulation layer. Also, a method of making the substrate by forming a masking layer on the first region of the superficial layer and removing the superficial layer and the insulating layer in the second region uncovered by the masking layer. The additional layer is formed in the second region and then planarized.

Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving substrate and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.

Abstract: Crystal oriented photovoltaic cells with increased efficiency are disclosed herein. In an exemplary embodiment, a photovoltaic device includes a metal substrate with a crystalline orientation comprising a diffracting structure integrated into a surface of the metal substrate. The photovoltaic device includes a heteroepitaxial crystal silicon layer having the crystalline orientation of the metal substrate and a heteroepitaxially grown buffer layer having the crystalline orientation. The buffer layer is positioned adjacent to the surface of the metal substrate having the diffracting structure.

Abstract: A method of formation of a thermal spray coating which forms a thermal spray coating on a coating-forming surface, characterized by comprising a thermal spraying step of thermally spraying feedstock powder on the coating-forming surface and a deposition and coating forming step of having the thermally sprayed feedstock powder deposit on the coating-forming surface and solidify to form a coating, in the deposition and coating forming step, when deposited on the coating-forming surface by thermal spraying, the feedstock powder deposits in the solid phase state in 50 to 90%, preferably 70 to 80%, of the whole so as to raise the ratio of the crystallite remaining in the feedstock powder and secure a high heat conductivity.