Abstract: A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.

Abstract: An object of the present invention is to provide an SOI substrate including a semiconductor layer which is efficiently planarized. A method for manufacturing an SOI substrate includes a step of irradiating a bond substrate with an accelerated ion to form an embrittlement region; a step of bonding the bond substrate and the base substrate with an insulating layer positioned therebetween; a step of splitting the bond substrate at the embrittlement region to leave a semiconductor layer bonded to the base substrate; a step of disposing the semiconductor layer in front of a semiconductor target containing the same semiconductor material as the semiconductor layer; and a step of alternately irradiating the surface of the semiconductor layer and the semiconductor target with a rare gas ion, so that the surface of the semiconductor layer is planarized.

Abstract: Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate.

Abstract: A semiconductor light emitting device comprises a substrate for mounting at least one light emitting element, a reflective film formed on the substrate, an edge of which rises perpendicularly to a surface of the substrate, and at least one light emitting element. A decrease in a reflected luminous flux from a reflective film can be restrained.

Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. One such apparatus includes a tier of silicon with a void between tiers of dielectric material. Residual silicide is on the tier of silicon and/or on the tiers of dielectric material and a device is formed at least partially in the void. Additional embodiments are also described.

Abstract: A method for transferring a monocrystalline semiconductor layer onto a support substrate by implanting species in a donor substrate; bonding the donor substrate to the support substrate; and fracturing the donor substrate to transfer the layer onto the support substrate; wherein a portion of the monocrystalline layer to be transferred is rendered amorphous, without disorganizing the crystal lattice of a second portion of the layer, with the portions being, respectively, a surface portion and a buried portion of the monocrystalline layer; and wherein the amorphous portion is recrystallized at a temperature below 500° C., with the crystal lattice of the second portion serving as a seed for recrystallization.

Abstract: A donor silicon wafer may be bonded to a substrate and a lamina cleaved from the donor wafer. A photovoltaic cell may be formed from the lamina bonded to the substrate. An intermetal stack is described that is optimized for use in such a cell. The intermetal stack may include a titanium layer in contact with the lamina, which reacts to form titanium silicide, a non-reactive barrier layer to check the silicide reaction, a low-resistance layer, and an adhesion layer to help adhesion to the receiver element.

Abstract: Provided is a semiconductor device manufacturing method wherein the following steps are performed; a step of forming at least a part of an element on a base body layer, a step of forming a peeling layer, a step of forming a planarizing film; a step of forming a die by separating the base body layer at a separating region; a step of bonding the die to a substrate by bonding the die on the planarizing film; and a step of peeling and removing a part of the base body layer along the peeling layer. Prior to the step of forming the die, a step of forming a groove opened on the surface of the planarizing film such that at least a part of the separating region is included on the bottom surface of the groove, and forming the die such that the die has a polygonal outer shape wherein all the internal angles are obtuse by forming the groove is performed.

Abstract: Disclosed is a method for manufacturing a surface-emitting laser device that emits laser light in a direction perpendicular to a substrate. The method includes manufacturing a laminated body in which a lower reflecting mirror, a resonator structure including an active layer, and an upper reflecting mirror including a selectively oxidized layer are laminated on the substrate; etching the laminated body from an upper surface to form a mesa structure having at least the selectively oxidized layer exposed at a side surface; and mounting the laminated body on a tray having a front surface shaped to follow a warpage of the laminated body at an oxidation temperature and selectively oxidizing the selectively oxidized layer from the side surface of the mesa structure, thereby generating a confinement structure in which a current passing region is surrounded by an oxide.

Abstract: A seed layer having a predetermined pattern is formed on a side of one surface of a second substrate, and a ferroelectric layer is formed on the side of the one surface of the second substrate. A lower electrode is formed on the ferroelectric layer, and the lower electrode and a first substrate are bonded via a bonding layer. A laser beam with a predetermined wavelength is irradiated from a side of other surface of the second substrate to transfer a ferroelectric film, which overlaps with the seed layer, of the ferroelectric layer and the seed layer onto the side of said one surface of the first substrate. The laser beam passes through the second substrate, is reflected by the seed layer, and is absorbed by a second portion of the ferroelectric layer. The second portion does not overlap with the seed layer.

Abstract: A method for temporary wafer bonding employs a curable adhesive composition and a degradation agent combined with the curable adhesive composition. The adhesive composition may include (A) a polyorganosiloxane containing an average of at least two silicon-bonded unsaturated organic groups per molecule, (B) an organosilicon compound containing an average of at least two silicon-bonded hydrogen atoms per molecule in an amount sufficient to cure the composition, (C) a catalytic amount of a hydrosilylation catalyst, and (D) a base. The film prepared by curing the composition is degradable and removable by heating.

Abstract: Embodiments related to measuring process pressure in low-pressure semiconductor processing environments are provided. In one example, a semiconductor processing module for processing a substrate with a process gas in a vacuum chamber is provided. The example module includes a reactor positioned within the vacuum chamber for processing the substrate with the process gas and a pressure-sensitive structure operative to transmit a pressure transmission fluid pressure to a location exterior to the vacuum chamber. In this example, the pressure transmission fluid pressure varies in response to the process gas pressure within the vacuum chamber.

Abstract: Provided are methods of removing water adsorbed or bonded to a surface of a semiconductor substrate, and methods of depositing an atomic layer using the method of removing water described herein. The method of removing water includes applying a chemical solvent to the surface of a semiconductor substrate, and removing the chemical solvent from the surface of the semiconductor substrate.

Abstract: An apparatus that comprises a device on a substrate and a crack stop in the substrate. Methods of forming a device are also disclosed. The methods may include providing a device, such as a semiconductor device, on a substrate having a first thickness, reducing the thickness of the substrate to a second thickness, and providing a crack stop in the substrate. Reducing the thickness of the substrate may include mounting the substrate to a carrier substrate for support and then removing the carrier substrate. The crack stop may prevent a crack from reaching the device.

Abstract: In one exemplary embodiment, a method includes: providing a structure having a first layer overlying a substrate, where the first layer includes a dielectric material having a plurality of pores; applying a filling material to a surface of the first layer, where the filling material includes a polymer and at least one additive, where the at least one additive includes at least one of a surfactant, a high molecular weight polymer and a solvent; and after applying the filling material, heating the structure to enable the filling material to at least partially fill the plurality of pores uniformly across an area of the first layer, where heating the structure results in residual filling material being uniformly left on the surface of the first layer.

Abstract: The present disclosure provides methods and apparatus for reducing dark current in a backside illuminated semiconductor device. In one embodiment, a method of fabricating a semiconductor device includes providing a substrate having a frontside surface and a backside surface, and forming a plurality of sensor elements in the substrate, each of the plurality of sensor elements configured to receive light directed towards the backside surface. The method further includes forming a dielectric layer on the backside surface of the substrate, wherein the dielectric layer is formed to have a compressive stress to induce a tensile stress in the substrate. A backside illuminated semiconductor device fabricated by such a method is also disclosed.

Abstract: A gas sensor manufacturing method including the following steps: providing a SOI substrate, including an oxide layer, a device layer, and a carrier, wherein the oxide layer is disposed between the device layer and the carrier; etching the device layer to form an integrated circuit region, an outer region, a trench and a conducting line, the conducting line including a connecting arm connecting to the integrated circuit region, the trench is formed around the conducting line and excavated to the oxide layer for reducing power consumption of the heater circuit, the connecting arm reaches over a gap between the integrated circuit region and the outer region and electrically connects to the integrated circuit region; coating or imprinting a sensing material on the circuit region; and etching the carrier and the oxide layer to form a cavity to form a film structure suspended in the cavity by the cantilevered connecting arm.

Abstract: A two-terminal mesa phototransistor and a method for making it are disclosed. The photo transistor has a mesa structure having a substantially planar semiconductor surface. In the mesa structure is a first semiconductor region of a first doping type, and a second semiconductor region of a second doping type opposite to that of the first semiconductor region, forming a first semiconductor junction with the first region. In addition, a third semiconductor region of the first doping type forms a second semiconductor junction with the second region. The structure also includes a dielectric layer. The second semiconductor region, first semiconductor junction, and second semiconductor junction each has an intersection with the substantially planar semiconductor surface. The dielectric covers, and is in physical contact with, all of the intersections.

Abstract: A method for producing a product wafer having chips thereon, comprising the steps of: processing the first side of the product wafer bonding the product wafer with its first side onto a first rigid carrier wafer with a first intermediate layer consisting of one first adhesion layer applied at least on the edge side, processing a second side of the product wafer, bonding of the product wafer with its second side on a second rigid carrier wafer with a second intermediate layer consisting of one second adhesion layer applied at least on the edge side, characterized in that the first intermediate layer and the second intermediate layer are made different such that the first carrier wafer can be separated selectively before the second carrier wafer.

Abstract: A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing.

Abstract: A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.

Abstract: A method to minimize edge-related substrate breakage during spalling using an edge-exclusion region where the stressor layer is either non-present (excluded either during deposition or removed afterwards) or present but significantly non-adhered to the substrate surface in the exclusion region is provided. In one embodiment, the method includes forming an edge exclusion material on an upper surface and near an edge of a base substrate. A stressor layer is then formed on exposed portions of the upper surface of the base substrate and atop the edge exclusion material, A portion of the base substrate that is located beneath the stressor layer and which is not covered by the edge exclusion material is then spalled.

Abstract: Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

Abstract: A method of manufacturing a bonded body of a semiconductor substrate and a semiconductor device to be mounted on the semiconductor substrate are provided. The method includes: preparing a first base member and a second base member; imparting liquid repellency for a liquid material to at least a part of a bonding film non-formation region of the first base member to form a liquid repellent region thereon; supplying the liquid material onto the first base member to selectively form a liquid coating on a bonding film formation region of the first base member; drying the liquid coating to obtain a bonding film on the bonding film formation region; and bonding the first base member and the second base member together through the bonding film due to a bonding property developed in a vicinity of a surface of the bonding film to thereby obtain the bonded body.

Abstract: According to one embodiment, a template substrate includes a substrate and a mask. The substrate includes a mesa region formed in a central portion of an upper surface of the substrate. The mesa region is configured to protrude more than a region of the substrate around the mesa region. An impurity is introduced into an upper layer portion of a partial region of a peripheral portion of the mesa region. The mask film is provided on the upper surface of the substrate.

Abstract: A method for manufacturing a semiconductor laser includes the steps of preparing a mold with a pattern surface having recesses, forming a stacked semiconductor layer including a grating layer, forming a resin part on the grating layer, forming a resin pattern portion on the resin part, forming a diffraction grating by etching the grating layer using the resin part as a mask, and forming a mesa-structure on the stacked semiconductor layer. Each of the recesses includes two end portions and a middle portion between the two end portions. A depth of at least one of the two end portions from the pattern surface is greater than that of the middle portion. The step of forming the mesa-structure includes the step of etching the stacked semiconductor layer so as to remove end portions of the diffraction grating in a direction orthogonal to a periodic direction thereof.

Abstract: A process for fabricating a substrate that includes a buried oxide layer for the production of electronic components or the like. The process includes depositing an oxide layer or a nitride layer on either of a donor or receiver substrate, and bringing the donor and receiver substrates into contact; conducting at least a first heat treatment of the oxide or nitride layer before bonding the substrates, and conducting a second heat treatment of the fabricated substrate of the receiver substrate, the oxide layer and all or part of the donor substrate at a temperature equal to or higher than the temperature applied in the first heat treatment. Substrates that have an oxide or nitride layer deposited thereon wherein the oxide or nitride layer is degassed and has a refractive index smaller than the refractive index of an oxide or nitride layer of the same composition formed by thermal growth.

Abstract: A structure for a semiconductor component is provided having a bi-layer capping coating integrated and built on supporting layer to be transferred. The bi-layer capping protects the layer to be transferred from possible degradation resulting from the attachment and removal processes of the carrier assembly used for layer transfer. A wafer-level layer transfer process using this structure is enabled to create three-dimensional integrated circuits.

Abstract: A method of forming a high k gate stack on a surface of a III-V compound semiconductor, such GaAs, is provided. The method includes subjecting a III-V compound semiconductor material to a precleaning process which removes native oxides from a surface of the III-V compound semiconductor material; forming a semiconductor, e.g., amorphous Si, layer in-situ on the cleaned surface of the III-V compound semiconductor material; and forming a dielectric material having a dielectric constant that is greater than silicon dioxide on the semiconducting layer. In some embodiments, the semiconducting layer is partially or completely converted into a layer including at least a surface layer that is comprised of AOxNy prior to forming the dielectric material. In accordance with the present invention, A is a semiconducting material, preferably Si, x is 0 to 1, y is 0 to 1 and x and y are both not zero.

Abstract: A semiconductor device includes a substrate, a nanowire, a first structure, and a second structure. The nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate, where the nanowire includes a layer on a surface of the nanowire, where the layer includes at least one of silicide and carbide, where the layer has a substantially uniform shape.

Abstract: The invention relates to a process for fabricating a semiconductor that comprises providing a handle substrate comprising a seed substrate and a weakened sacrificial layer covering the seed substrate; joining the handle substrate with a carrier substrate; optionally treating the carrier substrate; detaching the handle substrate at the sacrificial layer to form the semiconductor structure; and removing any residue of the sacrificial layer present on the seed substrate.

Abstract: A deposition mask is used to pattern a thin film 3 on a substrate 10 by depositing deposition particles through a plurality of openings K having a stripe pattern. The deposition mask includes a frame 65; a plurality of mask layers 70 provided in the frame so as to overlap each other; and a support layer 71 provided between the mask layers 70. Each of the mask layers 70 is formed by arranging a plurality of mask wires 72 in a stripe pattern in a tensioned state, and the support layer 71 is formed by arranging a plurality of support wires 74 in a tensioned state so as to cross the mask wires 72. A plurality of gaps 73 in each of the plurality of mask layers 70 overlap each other to form a plurality of through gaps 73a that linearly extend through all of the plurality of mask layers 70. The openings K are formed by the through gaps 73a.

Abstract: A manufacturing method of a photoelectric conversion device module, wherein an insulating layer and a first electrode are formed over a base substrate; a plurality of single-crystal semiconductor substrates having a first conductivity type including embrittlement layers formed inside are attached; the plurality of single-crystal semiconductor substrates are separated at the embrittlement layers so that a plurality of stacked bodies including the insulating layer, the first electrode and a first single-crystal semiconductor layer is formed; a second single-crystal semiconductor layer is formed over the stacked bodies to form a first photoelectric conversion layer; a second photoelectric conversion layer including a non-single-crystal semiconductor layer is formed; a second electrode is formed; and selective etching is conducted to form photoelectric conversion cells which are element-separated, and a connecting electrode is formed to connect the second electrode of one photoelectric conversion cell and the fir

Abstract: A method of controlled layer transfer is provided. The method includes providing a stressor layer to a base substrate. The stressor layer has a stressor layer portion located atop an upper surface of the base substrate and a self-pinning stressor layer portion located adjacent each sidewall edge of the base substrate. A spalling inhibitor is then applied atop the stressor layer portion of the base substrate, and thereafter the self-pinning stressor layer portion of the stressor layer is decoupled from the stressor layer portion. A portion of the base substrate that is located beneath the stressor layer portion is then spalled from the original base substrate. The spalling includes displacing the spalling inhibitor from atop the stressor layer portion. After spalling, the stressor layer portion is removed from atop a spalled portion of the base substrate.

Abstract: Embodiments of the invention relate to a method of functional materials deposition using a polymer template fabricated on a substrate. Such template forms an exposed and masked areas of the substrate material, and can be fabricated using polymer resists or Self-assembled monolayers. Deposition is performed using an applicator, which is fabricated in the shape of cylinder or cone made of soft elastomeric materials or laminated with soft elastomeric film. Functional materials, for example, metals, semiconductors, sol-gels, colloids of particles are deposited on the surface of applicator using liquid immersion, soaking, contact with wetted surfaces, vapor deposition or other techniques. Then wetted applicator is contacted the surface of the polymer template and rolled over it's surface. During this dynamic contact functional material is transferred selectively to the areas of the template. Patterning of functional material is achieved by lift-off of polymeric template after deposition.

Abstract: A method for establishing a calibrating standard for wafer inspection includes depositing solid ionized particles of a known size range with an aerosol onto a wafer. The method also includes depositing particles onto a wafer in a deposition chamber by using an aerosol stream and the solid particles suspended in a gas; ionizing the aerosol stream with a negative or positive charge polarity or both by passing the aerosol stream through a non-radioactive ionizer to produce charged particles and supplying such aerosol stream to the deposition chamber.

Abstract: A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion.

Abstract: An MEMS component including a monolithically integrated electronic component with a multi-plane conductor track layer stack which is arranged on a substrate and into which is integrated a cantilevered elastically movable metallic actuator which is arranged in the multi-plane conductor track layer stack at the level of a conductor track plane and is connected by via contacts to conductor track planes which are arranged thereabove or therebeneath and which apart from an opening in the region of the actuator are separated from the conductor track plane of the actuator by a respective intermediate plane insulator layer, wherein the actuator is formed from a metallically conductive layer or layer combination which is resistant to corrosive liquids or gases and which contains titanium nitride or consists of titanium nitride.

Abstract: One aspect of the invention relates to a method for deposition of a film having a predetermined film composition. The method comprises: in a deposition chamber: providing a substrate at a fixed temperature; depositing a film; flowing a mixture of two gases, wherein the ratio of the two gases is selected such that the mixture has a redox potential to provide a predetermined film composition. In some embodiments, depositing a film occurs via an atomic layer deposition process or chemical vapor deposition process. Methods for chemical vapor deposition of a metal or lanthanide oxide layer are provided featuring a mixture of oxidizing and reducing gases is flowed over the transition metal oxide or lanthanide oxide layer. The mixture of gases has an oxidation potential selected to produce a layer having a desired stoichiometry of a deposited film.

Abstract: A method to prevent movable structures within a MEMS device, and more specifically, in recesses having one or more dimension in the micrometer range or smaller (i.e., smaller than about 10 microns) from being inadvertently bonded to non-moving structures during a bonding process. The method includes surface preparation of silicon both structurally and chemically to aid in preventing moving structures from bonding to adjacent surfaces during bonding, including during high force, high temperature fusion bonding.

Abstract: A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.

Abstract: Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate.

Abstract: A method for producing a hybrid substrate includes preparing a first substrate including a mixed layer and an underlying electrically insulating continuous layer, the mixed layer made up of first single-crystal areas and second adjacent amorphous areas, the second areas making up at least part of the free surface of the first substrate. A second substrate is bonded to the first substrate, the second substrate including on the surface thereof, a reference layer with a predetermined crystallographic orientation. The first substrate is bonded to the second substrate by hydrophobic molecular bonding of at least the amorphous areas. A recrystallization of at least part of the amorphous areas to solid phase is carried out according to the crystallographic orientation of the reference layer, and the two substrates are separated at the bonding interface.

Abstract: A method of manufacturing a semiconductor device, comprising bonding a first principal surface of a substrate to a supporting substrate through a light-to-heat conversion film, and removing a portion of the light-to-heat conversion film exposed on the supporting substrate. A method of manufacturing a semiconductor device, comprising forming a light-to-heat conversion film on a supporting substrate, bonding a semiconductor substrate to the supporting substrate, so that the light-to-heat conversion film extends outside the semiconductor substrate, performing an anti-contamination treatment on the light-to-heat conversion film, and separating the supporting substrate and the semiconductor substrate from each other.

Abstract: A method for decapsulating an integrated circuit package in the absence of a mask is disclosed. First, a package is provided. The package includes at least a circuit element and a molding compound enclosing the circuit. Second, a caustic solution is simultaneously provided and drained. The caustic solution is capable of etching the molding compound while in continuous contact with the molding compound to etch the molding compound. As a consequence, the molding compound is removed so that the circuit element in the package is substantially exposed.

Abstract: System and method for operating a material deposition system are disclosed. In one embodiment, the method can include periodically injecting a precursor into a vaporizer through an injector at the vaporizer, vaporizing the precursor in the vaporizer and supplying the vaporized precursor to a reaction chamber in fluid communication with the vaporizer, and shutting down the vaporizer and the reaction chamber after a period of time. The method can also include conducting maintenance of the injector at the vaporizer by using a vapor solvent rinse.

Abstract: A method for decapsulating an integrated circuit package without the need of using a mask during the decapsulation process is disclosed. First, a package is provided. The package includes at least a circuit element and a molding compound enclosing the circuit. Second, a caustic solution is simultaneously provided. The caustic solution is capable of etching the molding compound and intermittently contacts a pre-selected area of the molding compound to etch the molding compound. As a consequence, the caustic solution removes the molding compound in the pre-selected area so the circuit element in the package is substantially exposed.

Abstract: An apparatus and method for multiple symmetrical divisional gas distribution providing a mounting plate, a plurality of manifolds coupled to the mounting plate, a center purge block coupled to the mounting plate and the plurality of manifolds, a plurality of reactant distribution blocks, wherein each reactant distribution block is stacked atop each other to form a reactant distribution block stack, wherein the reactant distribution block stack sits atop the center purge block, a coupling mechanism to secure the plurality of reactant distribution blocks of the reactant distribution block stack together; and a top cap coupled to the reactant distribution block stack and the coupling mechanism.

Abstract: After flash irradiation on a semiconductor wafer is started and then the temperatures of front and back surfaces of the semiconductor wafer become equal to each other, the temperature of the back surface of the semiconductor wafer, which has a known emissivity, is measured with a radiation thermometer. The emissivity of the front surface of the semiconductor wafer is calculated based on the intensity of radiated light from a black body having an equal temperature to the temperature of the back surface thereof, and the intensity of radiated light actually radiated from the front surface of the semiconductor wafer. Then, the temperature of the front surface of the semiconductor wafer heated by the flash irradiation is calculated based on the calculated emissivity and the intensity of the radiated light from the front surface of the semiconductor wafer that has been measured after the flash irradiation is started.

Abstract: A method and semiconductor device for synthesizing graphene using ion implantation of carbon. Carbon is implanted in a metal using ion implantation. After the carbon is distributed in the metal, the metal is annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the surface of the metal. The metal/graphene surface is then transferred to a dielectric layer in such a manner that the graphene layer is placed on top of the dielectric layer. The metal layer is then removed. Alternatively, recessed regions are patterned and etched in a dielectric layer located on a substrate. Metal is later formed in these recessed regions. Carbon is then implanted into the metal using ion implantation. The metal may then be annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the metal's surface.