Abstract: Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate.

Abstract: According to an embodiment, a composite wafer includes a carrier substrate having a graphite layer and a monocrystalline semiconductor layer attached to the carrier substrate.

Abstract: Systems, methods, and apparatus for depositing a protective layer on a wafer substrate are disclosed. In one aspect, a protective layer is deposited over a surface of a wafer substrate using a process configured to produce substantially less damage in the wafer substrate than a first plasma-assisted deposition process. The protective layer is less than about 100 Angstroms thick. A barrier layer is deposited over the protective layer using the first plasma-assisted deposition process.

Abstract: The present invention relates to a thin film transistor array panel, a liquid crystal display, and a method capable of reducing an effect on neighboring pixels in a process of repairing a pixel defect. The thin film transistor array panel may include: a thin film transistor connected to a gate line and a data line to define a pixel area; a pixel electrode formed in the pixel area and connected to the thin film transistor; and a storage electrode including a first portion overlapping the data line between two adjacent gate lines. The storage electrode may also include a second portion connected to the first portion and enclosing an edge of the pixel area except for a region where the first portion is formed. The storage electrode may be branched between pixel electrodes respectively formed in two adjacent pixel areas.

Abstract: According to an embodiment, a composite wafer includes a carrier substrate having a graphite core and a monocrystalline semiconductor layer attached to the carrier substrate.

Abstract: Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate.

Abstract: A method of cleaving a substrate is disclosed. A species, such as hydrogen or helium, is implanted into a substrate to form a layer of microbubbles. The substrate is then annealed a pressure greater than atmosphere. This annealing may be performed in the presence of the species that was implanted. This diffuses the species into the substrate. The substrate is then cleaved along the layer of microbubbles. Other steps to form an oxide layer or to bond to a handle also may be included.

Abstract: A method for the direct bonding of a first wafer having an intrinsic curvature before bonding to a second wafer having an intrinsic curvature before bonding, at least one of the two wafers comprising at least one series of microcomponents. The method includes of bringing the two wafers into contact with each other so as to initiate the propagation of a bonding wave therebetween while imposing a predefined bonding curvature in the form of a paraboloid of revolution on one of the two wafers depending at least upon the intrinsic curvature before bonding of the wafer that includes the microcomponents, with the other wafer being free to conform to the predefined bonding curvature.

Abstract: An improved method and apparatus for a device with minimized optical cross-talk are provided. In one example, the device includes a filtering material selected to maximize the attenuation of signals causing cross-talk while minimizing the attenuation of desired signals.

Abstract: A light emitting active region between a first cladding layer and a second cladding layer, wherein the first cladding layer has a lower refractive index than a refractive index of the second cladding layer, and the first cladding layer and the second cladding layer are III-nitride based.

Abstract: First etching is performed on a surface of a single crystal semiconductor layer formed with no substrate bias applied. The single crystal semiconductor layer is formed by attaching a single crystal semiconductor substrate including an embrittled region to a supporting substrate so that an oxide layer is sandwiched between the single crystal semiconductor substrate and the supporting substrate and separating the single crystal semiconductor substrate into the single crystal semiconductor layer and part of the single crystal semiconductor substrate at the embrittled region. After the first etching, the single crystal semiconductor layer is irradiated with a laser beam and at least part of the surface of the single crystal semiconductor layer is melted and solidified. Then, second etching is performed on the surface of the single crystal semiconductor layer with no substrate bias applied.

Abstract: A GaN sample in a sealed enclosure is heated very fast to a high temperature above the point where GaN is thermodynamically stable and is then cooled down very fast to a temperature where it is thermodynamically stable. The time of the GaN exposure to a high temperature range above its thermodynamic stability is sufficiently short, in a range of few seconds, to prevent the GaN from decomposing. This heating and cooling cycle is repeated multiple times without removing the sample from the enclosure. As a result, by accumulating the exposure time in each cycle, the GaN sample can be exposed to a high temperature above its point of thermodynamic stability for a long time but the GaN sample integrity is maintained (i.e., the GaN doesn't decompose) due to the extremely short heating duration of each single cycle.

Abstract: A semiconductor substrate having a semiconductor device formable area, wherein a reinforcing part, which is thicker than the semiconductor device formable area and has a top part of which surface is flat, is formed on an outer circumference part of the semiconductor substrate, and an inner side surface connecting the top part of the reinforcing part and the semiconductor device formable area has a cross-sectional shape of which inner diameter becomes smaller as being closer to the semiconductor device formable area.

Abstract: An apparatus for electrostatic chucking and dechucking of a semiconductor wafer includes an electrostatic chuck with a number of zones. Each zone includes one or more polar regions around a lift pin that contacts a bottom surface of the semiconductor wafer. The apparatus also includes one or more controllers that control the lift pins and one or more controllers that control the polar regions. The controller for the lift pins receives data from one or more sensors and uses the data to adjust the upward force of the lift pins. Likewise, the controller for the polar regions receives data from the sensors and uses the data to adjust the voltage in the polar regions.

Abstract: Freestanding III-nitride single-crystal substrates whose average dislocation density is not greater than 5×105 cm?2 and that are fracture resistant, and a method of manufacturing semiconductor devices utilizing such freestanding III-nitride single-crystal substrates are made available. The freestanding III-nitride single-crystal substrate includes one or more high-dislocation-density regions (20h), and a plurality of low-dislocation-density regions (20k) in which the dislocation density is lower than that of the high-dislocation-density regions (20h), wherein the average dislocation density is not greater than 5×105 cm?2. Herein, the ratio of the dislocation density of the high-dislocation-density region(s) (20h) to the average dislocation density is sufficiently large to check the propagation of cracks in the substrate. And the semiconductor device manufacturing method utilizes the freestanding III-nitride single crystal substrate (20p).

Abstract: A method of manufacturing a semiconductor device, wherein the method comprises applying a first layer comprising silicon to a second layer comprising silicon carbide, wherein an interface is defined between the first and second layers; and oxidising sonic or all of the first layer.

Abstract: A method of manufacturing a semiconductor device includes: carrying a substrate having an oxide film and a nitride film stacked thereon into a processing chamber; supporting and heating the substrate using a substrate support member provided in the processing chamber; adjusting flow rates of hydrogen-containing gas and nitrogen-containing gas in process gas using a gas flow rate controller to set a percentage R of the number of hydrogen atoms with respect to the total number of hydrogen atoms and nitrogen atoms contained in the process gas to be 0%<R?80%; supplying the process gas with the adjusted flow rates into the processing chamber using a gas supplying unit; exciting the process gas supplied into the processing chamber using a plasma generator; processing the substrate with the excited process gas; and carrying the substrate out of the processing chamber.

Abstract: A method for manufacturing a micromechanical component is proposed. In this context, at least one trench structure having a depth less than the substrate thickness is to be produced in a substrate. In addition, an insulating layer and a filler layer are produced or applied on a first side of the substrate. The filler layer comprises a filler material that substantially fills up the trench structure. A planar first side of the substrate is produced by way of a subsequent planarization within a plane of the filler layer or of the insulating layer or of the substrate. A further planarization of the second side of the substrate is then accomplished. A micromechanical component that is manufactured in accordance with the method is also described.

Abstract: A thermally stabilized, high speed, micrometer-scale silicon electro-optic modulator is provided. Methods for maintaining desired temperatures in electro-optic modulators are also provided. The methods can be used to maintain high quality modulation in the presence of thermal variations from the surroundings. Direct current injection into the thermally stabilized electro-optic modulator is used to maintain the modulation performance of the modulator. The direct injected current changes the local temperature of the thermally stabilized electro-optic modulator to maintain its operation over a wide temperature range.

Abstract: A semiconductor-based gas detector enhances the collection of gas molecules and also provides a self-contained means for removing collected gas molecules by utilizing one or more electric fields to transport the gas molecules to and away from a metallic material that has a high permeability to the gas molecules.

Abstract: A substrate depositing system and a method of using a substrate depositing system. A substrate depositing system includes a load-lock chamber for loading and unloading a substrate, at least one transfer chamber connected to the load-lock chamber and including a substrate transfer device configured to vertically transfer the substrate, and a pair of depositing chambers connected to opposite sides of the at least one transfer chamber and including a depositing source and a pair of substrate fixing devices, the substrate transfer device including a pair of substrate installing members.

Abstract: Methods of fabricating semiconductor structures include providing a sacrificial material within a via recess, forming a first portion of a through wafer interconnect in the semiconductor structure, and replacing the sacrificial material with conductive material to form a second portion of the through wafer interconnect. Semiconductor structures are formed by such methods. For example, a semiconductor structure may include a sacrificial material within a via recess, and a first portion of a through wafer interconnect that is aligned with the via recess. Semiconductor structures include through wafer interconnects comprising two or more portions having a boundary therebetween.

Abstract: Provided is a substrate processing apparatus in which after a module is disabled, a substrate is provided to a carry-in module capable of placing the wafers most rapidly in the plurality of unit blocks and the substrates are sequentially transported to the module group by the transportation means to be delivered to the carry-out module according to a providing sequence of the substrate to the carry-in module in each of the plurality of unit blocks. In particular, the substrates are extracted from the carry-out module according to a providing sequence of the substrate to the carry-in module and transported to a rear module or a substrate placing part. Thereafter, the substrates are transported to the rear module from the carry-out module or the substrate placing part according to a predetermined sequence in which the substrate is provided to the carry-in module in a normal state.

Abstract: When a thermal expansion coefficient of a handle substrate is higher than that of a donor substrate, delamination is provided without causing a crack in the substrates. A method for producing a bonded wafer, with at least the steps of: implanting ions into a donor substrate (3) from a surface thereof to form an ion-implanted interface (5); bonding a handle substrate (7) with a thermal expansion coefficient higher than that of the donor substrate (3) onto the ion-implanted surface of the donor substrate to provide bonded substrates, subjecting the bonded substrates to a heat treatment to provide an assembly (1), and delaminating the donor substrate (3) of the assembly (1) at the ion-implanted interface wherein the assembly (1) has been cooled to a temperature not greater than room temperature by a cooling apparatus (20), so that a donor film is transferred onto the handle substrate (7).

Abstract: A method of fabricating epitaxial structures including applying an etch stop to one side of a substrate and then growing at least one epitaxial layer on a first side of said substrate, flipping the substrate, growing a second etch stop and at least one epitaxial layer on a second side of the substrate, applying a carrier medium to the ultimate epitaxial layer on each side, dividing the substrate into two parts generally along an epitaxial plane to create separate epitaxial structures, removing any residual substrate and removing the etch stop.

Abstract: According to an embodiment, an active layer is formed on a first surface of a semiconductor substrate, a wiring layer is formed on the active layer, and an insulating layer is formed covering the wiring layer. The first surface of the semiconductor substrate is bonded to a support substrate via the insulating layer, and the semiconductor substrate bonded to the support substrate is thinned leaving the semiconductor substrate having a predetermined thickness which covers the active layer from a second surface. At least a part of area of the thinned semiconductor substrate is removed to expose the active layer.

Abstract: A method of producing a nitride semiconductor laser device includes: forming a wafer including a nitride semiconductor layer of a first conductivity type, an active layer of a nitride semiconductor, a nitride semiconductor layer of a second conductivity type, and an electrode pad for the second conductivity type stacked in this order on a main surface of a conductive substrate and also including stripe-like waveguide structures parallel to the active layer; cutting the wafer to obtain a first type and a second type of laser device chips; and distinguishing between the first type and the second type of chips by automatic image recognition. The first type and the second type of chips are different from each other in position of the stripe-like waveguide structure with respect to a width direction of each chip and also in area ratio of the electrode pad to the main surface of the substrate.

Abstract: A method of protecting a substrate during fabrication of semiconductor, MEMS devices. The method includes application of a protective thin film which typically has a thickness ranging from 3 angstroms to about 1,000 angstroms, wherein precursor materials used to deposit the protective thin film are organic-based precursors which include at least one fluorine-comprising functional group at one end of a carbon back bone and at least one functional bonding group at the opposite end of a carbon backbone, and wherein the carbon backbone ranges in length from 4 carbons through about 12 carbons. In many applications at least a portion of the protective thin film is removed during fabrication of the devices.

Abstract: A dry-in/dry-out system is disclosed for wafer electroless plating. The system includes an upper zone for wafer ingress/egress and drying operations. Proximity heads are provided in the upper zone to perform the drying operations. The system also includes a lower zone for electroless plating operations. The lower zone includes an electroless plating apparatus that implements a wafer submersion by fluid upwelling method. The upper and lower zones of the system are enclosed by a dual-walled chamber, wherein the inner wall is a chemically inert plastic and the outer wall is a structural metal. The system interfaces with a fluid handling system which provides the necessary chemistry supply and control for the system. The system is ambient controlled. Also, the system interfaces with an ambient controlled managed transfer module (MTM).

Abstract: Showerhead electrodes for a semiconductor material processing apparatus are disclosed. An embodiment of the showerhead electrodes includes top and bottom electrodes bonded to each other. The top electrode includes one or more plenums. The bottom electrode includes a plasma-exposed bottom surface and a plurality of gas holes in fluid communication with the plenum. Showerhead electrode assemblies including a showerhead electrode flexibly suspended from a top plate are also disclosed. The showerhead electrode assemblies can be in fluid communication with temperature-control elements spatially separated from the showerhead electrode to control the showerhead electrode temperature. Methods of processing substrates in plasma processing chambers including the showerhead electrode assemblies are also disclosed.

Abstract: A method for making a nanowire element includes: providing an imprint mold including a first substrate and a conductive pattern-transferring layer, the pattern-transferring layer includes first conductive strips; electrifying the pattern-transferring layer with an alternating current; applying a nanowire-containing suspension on the pattern-transferring layer; reorienting the nanowires in the nanowire-containing suspension using a dielectrophoresis method, thereby the nanowires connected between two adjacent first conductive strips; providing a pattern-receiving body, the pattern-receiving body including a second substrate and a pattern-receiving layer; pressing the imprint mold onto the pattern-receiving body with the conductive pattern-transferring layer facing the pattern-receiving layer, thereby defining a patterned recess in the pattern-receiving layer and transferring the nanowires to the second substrate; forming a first conductive layer on the second substrate to obtain a conductive pattern layer, the

Abstract: The present invention relates to a method for molecular adhesion bonding between at least a first wafer and a second wafer involving aligning the first and second wafers, placing the first and second wafers in an environment having a first pressure (P1) greater than a predetermined threshold pressure; bringing the first wafer and the second wafer into alignment and contact; and initiating the propagation of a bonding wave between the first and second wafer after the wafers are aligned and in contact by reducing the pressure within the environment to a second pressure (P2) below the threshold pressure. The invention also relates to the three-dimensional composite structure that is obtained by the described method of adhesion bonding.

Abstract: In general, embodiments of the present invention provide a variable height LED and method of manufacture. Specifically, under embodiments of the present invention, a buffer layer is applied (e.g., selectively) over a wafer, and a set of LED chips is provided over the buffer layer. One role of the buffer layer is to increase a height of at least a subset of the chips. As such, the buffer layer could be applied using any processing method now known or later developed. For example, the buffer layer could be selectively deposited, etched, etc. Regardless, in a typical embodiment, the buffer layer comprises a mesa structure having a thickness less than approximately 100 ?m. In addition, the mesa structure is typically constructed from three RGB wafers.

Abstract: A solid state light (“SSL”), a solid state emitter (“SSE”), and methods of manufacturing SSLs and SSEs. In one embodiment, an SSL comprises a packaging substrate having an electrical contact and a light emitting structure having a front side and a back side. The back side of the light emitting structure is superimposed with the electrical contact of the packaging substrate. The SSL can further include a temperature control element aligned with the light emitting structure and the electrical contact of the packaging substrate.

Abstract: In a CSP type semiconductor device, the invention prevents a second wiring from forming a narrowed portion on a lower surface of a step portion at the time of forming the second wiring that is connected to the back surface of a first wiring formed near a side surface portion of a semiconductor die on the front surface and extends onto the back surface of the semiconductor die over the step portion of a window that is formed from the back surface side of the semiconductor die so as to expose the back surface of the first wiring. A glass substrate is bonded on a semiconductor substrate on which a first wiring is formed on the front surface near a dicing line with an adhesive resin being interposed therebetween. The semiconductor substrate is then etched from the back surface to form a window having step portions with inclined sidewalls around the dicing line as a center.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming a plurality of first integrated circuits on the surface side of a first semiconductor substrate; forming a plurality of second integrated circuits in a semiconductor layer that is formed on a release layer provided on a second semiconductor substrate; bonding the two semiconductor substrates so that electrically bonding portions are bonded to each other to form a bonded structure; separating the second semiconductor substrate from the bonded structure at the release layer to transfer, to the first semiconductor substrate, the semiconductor layer in which the plurality of second integrated circuits are formed; and dicing the first semiconductor substrate to obtain stacked chips each including the first integrated circuit and the second integrated circuit.

Abstract: Multiple bonding layer schemes that temporarily join semiconductor substrates are provided. In the inventive bonding scheme, at least one of the layers is directly in contact with the semiconductor substrate and at least two layers within the scheme are in direct contact with one another. The present invention provides several processing options as the different layers within the multilayer structure perform specific functions. More importantly, it will improve performance of the thin-wafer handling solution by providing higher thermal stability, greater compatibility with harsh backside processing steps, protection of bumps on the front side of the wafer by encapsulation, lower stress in the debonding step, and fewer defects on the front side.

Abstract: A Light-Emitting Diode (LED) includes a light-emitting structure having a passivation layer disposed on vertical sidewalls across a first doped layer, an active layer, and a second doped layer that completely covers at least the sidewalls of the active layer. The passivation layer is formed by plasma bombardment or ion implantation of the light-emitting structure. It protects the sidewalls during subsequent processing steps and prevents current leakage around the active layer.

Abstract: A micro-electromechanical systems (MEMS) transducer device mounted to a package substrate includes an active transducer having a resonator stack formed over a cavity through a transducer substrate, and a stress mitigation structure between the transducer substrate and the package substrate. The stress mitigation structure reduces stress induced on the transducer substrate due to mismatched coefficients of thermal expansion (CTEs) of the transducer substrate and the package substrate, respectively.

Abstract: An integrated circuit structure includes a substrate having a top surface; a first conductive layer over and contacting the top surface of the substrate; a dielectric layer over and contacting the first conductive layer, wherein the dielectric layer includes an opening exposing a portion of the first conductive layer; and a proof-mass in the opening and including a second conductive layer at a bottom of the proof-mass. The second conductive layer is spaced apart from the portion of the first conductive layer by an air space. Springs anchor the proof-mass to portions of the dielectric layer encircling the opening. The springs are configured to allow the proof-mass to make three-dimensional movements.

Abstract: A vent hole precursor structure (26) in an intermediate product for a semi-conductor device has delicate structures (27, 28), and said intermediate product has a cavity (21) with a pressure therein differing from the pressure of the surroundings. The intermediate product comprises a first wafer (20) in which there is formed a depression (21). The first wafer is bonded to a second wafer (22) comprising a device layer (23) from which the structures (27, 28) are to be made by etching. A hole or groove (26) having a predefined depth extends downwards into the device layer, such that the cavity (21) during etching is opened up before the etching procedure breaks through the device layer (23) to form the structures (27, 28).

Abstract: Methods, structures, and design structures for improved adhesion of protective layers of imager microlens structures are disclosed. A method of fabricating a semiconductor structure includes forming an interfacial region between a microlens and a protective oxide layer. The interfacial region has a lower concentration of oxygen than the protective oxide layer.

Abstract: A method of producing a heterostructure by bonding at least one first substrate having a first thermal expansion coefficient onto a second substrate having a second thermal expansion coefficient, with the first thermal expansion coefficient being different from the second thermal expansion coefficient. Prior to bonding, trenches are formed in one of the two substrates from the bonding surface of the substrate. The trenches are filled with a material having a third thermal expansion coefficient lying between the first and second thermal expansion coefficients.

Abstract: A semiconductor device and a method for manufacturing a semiconductor device are provided. A semiconductor device comprises a first single-crystal semiconductor layer including a first channel formation region and a first impurity region over a substrate having an insulating surface, a first gate insulating layer over the first single-crystal semiconductor layer, a gate electrode over the first gate insulating layer, a first interlayer insulating layer over the first gate insulating layer, a second gate insulating layer over the gate electrode and the first interlayer insulating layer, and a second single-crystal semiconductor layer including a second channel formation region and a second impurity region over the second gate insulating layer. The first channel formation region, the gate electrode, and the second channel formation region are overlapped with each other.

Abstract: Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.

Abstract: A light amplifier includes a single crystal semiconductor substrate with a rare earth oxide, light amplifying gain medium deposited on the substrate and formed into a light waveguide, and a pump laser. A lattice matching virtual substrate integrates the pump laser to the gain medium with a first opposed surface crystal lattice matched to the gain medium and second opposed surface crystal lattice matched to the pump laser. The pump laser is positioned with a light output surface coupled to a light input surface of the gain medium so as to introduce pump energy into the light waveguide. The light amplifier has a very small footprint and allows the integration of control and monitoring electronics.

Abstract: A method of fabricating a printhead integrated circuit configured for backside electrical connections. The method comprises the steps of: (a) providing a wafer comprising a plurality of partially-fabricated nozzle assemblies on a frontside of the wafer and through-silicon connectors extending from the frontside towards a backside of the wafer; (b) depositing a conductive layer on the frontside of said wafer and etching to form an actuator for each nozzle assembly and a frontside contact pad over a head of each through-silicon connector; (c) performing further MEMS processing steps to complete formation of nozzle assemblies ink supply channels through-silicon connectors; and (d) dividing the wafer into individual printhead integrated circuits. Each printhead integrated circuit thus formed is configured for backside-connection to the drive circuitry via the through-silicon connectors the contact pads.

Abstract: Substrate stand-offs for use with semiconductor devices are provided. Active pillars and dummy pillars are formed on a first substrate such that the dummy pillars may have a height greater than a height of the active pillars. The dummy pillars act as stand-offs when joining the first substrate to a second substrate, thereby creating greater uniformity. In an embodiment, the dummy pillars may be formed simultaneously as the active pillars by forming a patterned mask having openings with a smaller width for the dummy pillars than for the active pillars. When an electro-plating process of the like is used to form the dummy and active pillars, the smaller width of the dummy pillar openings in the patterned mask causes the dummy pillars to have a greater height than the active pillars.

Abstract: A method of manufacturing a neutron detector comprises forming a first wafer by at least forming an oxide layer on a substrate, forming an active semiconductor layer on the oxide layer, and forming an interconnect layer on the active semiconductor layer, forming at least one electrically conductive pathway extending from the interconnect layer through the active semiconductor layer and the oxide layer, forming a circuit transfer bond between the interconnect layer and a second wafer, removing the substrate of the first wafer after forming the circuit transfer bond, depositing a bond pad on the oxide layer after removing the substrate of the first wafer, wherein the bond pad is electrically connected to the electrically conductive pathway, depositing a barrier layer on the oxide layer after removing the substrate of the first wafer, and depositing a neutron conversion layer on the barrier layer after depositing the barrier layer.

Abstract: Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.