Abstract: An integrated circuit device includes a bottom wafer having a first annular dielectric block, at least one stacking wafer having a second annular dielectric block positioned on the bottom wafer, and a conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner. In one embodiment of the present invention, the bottom wafer and the stacking wafer are bonded by an intervening adhesive layer, no bump pad is positioned between the bottom wafer and the stacking wafer, and the conductive via is positioned within the first annular dielectric block and the second annular dielectric block.

Abstract: An apparatus and method for combinatorial non-contact wet processing of a liquid material may include a source of a liquid material, a first reaction cell, a second reaction cell, a first plurality of gas jets disposed within an interior of the first reaction cell, the first plurality of gas jets configured to atomize the liquid material transferred to the interior of the first reaction cell, a second plurality of gas jets disposed within an interior of the second reaction cell, the second plurality of gas jets configured to atomize the liquid material transferred to the interior of the second reaction cell, a first vacuum element disposed along a periphery of the first reaction cell, and a second vacuum element disposed along a periphery of the at least a second reaction cell.

Abstract: In a semiconductor integrated circuit sandwiched between a pair of a first impact resistance layer and a second impact resistance layer, an impact diffusion layer is provided between the semiconductor integrated circuit and the second impact resistance layer. By provision of the impact resistance layer against the external stress and the impact diffusion layer for diffusing the impact, force applied to the semiconductor integrated circuit per unit area is reduced, so that the semiconductor integrated circuit is protected. The impact diffusion layer preferably has a low modulus of elasticity and high breaking modulus.

Abstract: This invention provides methods that permit wafers to be loaded and unloaded in a gas-phase epitaxial growth chamber at high temperatures. Specifically, this invention provides a method for moving wafers or substrates that can bathe a substrate being moved in active gases that are optionally temperature controlled. The active gases can act to limit or prevent sublimation or decomposition of the wafer surface, and can be temperature controlled to limit or prevent thermal damage. Thereby, previously-necessary temperature ramping of growth chambers can be reduced or eliminated leading to improvement in wafer throughput and system efficiency.

Abstract: A gas sensor manufacturing method including the following steps: providing a SOI substrate, including an oxide layer, a device layer, and a carrier, wherein the oxide layer is disposed between the device layer and the carrier; etching the device layer to form an integrated circuit region, an outer region, a trench and a conducting line, the conducting line including a connecting arm connecting to the integrated circuit region, the trench is formed around the conducting line and excavated to the oxide layer for reducing power consumption of the heater circuit, the connecting arm reaches over a gap between the integrated circuit region and the outer region and electrically connects to the integrated circuit region; coating or imprinting a sensing material on the circuit region; and etching the carrier and the oxide layer to form a cavity to form a film structure suspended in the cavity by the cantilevered connecting arm.

Abstract: A process for cleaving a substrate for the purpose of detaching a film therefrom. The method includes the formation of a stress-generating structure locally bonded to the substrate surface and designed to expand or contract in a plane parallel to the substrate surface under the effect of a heat treatment; and the application of a heat treatment to the structure, designed to cause the structure to expand or contract so as to generate a plurality of local stresses in the substrate which generates a stress greater than the mechanical strength of the substrate in a cleavage plane parallel to the surface of the substrate defining the film to be detached, the stress leading to the cleavage of the substrate over the cleavage plane. Also, an assembly of a substrate and the stress-generating structure as well as use of the assembly in a semiconductor device for photovoltaic, optoelectronic or electronic applications.

Abstract: A system for simultaneously treating multiple workpieces is configured with treatment sites, configured to hold respective workpieces, fixed on a rotatable base. Treatment stations are equipped with respective active components operable simultaneously to treat respective workpieces identically on respective aligned treatment sites. For loading and unloading the treatment sites are rotated through distinct loading and unloading stations of the treatment stations which allow loading of a second batch while a first batch is being unloaded.

Abstract: A phase-shift mask having a checkerboard array and a surrounding sub-resolution assist phase pattern. The checkerboard array comprises alternating phase-shift regions R that have a relative phase difference of 180 degrees. The sub-resolution assist phase regions R? reside adjacent corresponding phase-shift regions R and have a relative phase difference of 180 degrees thereto. The sub-resolution assist phase regions R? are configured to mitigate undesirable edge effects when photolithographically forming photoresist features. Method of forming LEDs using the phase-shift mask are also disclosed.

Abstract: Methods of forming a semiconductor structure including a semiconductor nanowire or epitaxial semiconductor material which extends from at least a surface of source region and the drain region are provided. The methods include converting an upper portion of the source region and the drain region and the semiconductor nanowire or epitaxial semiconductor material into a continuous metal semiconductor alloy. The continuous metal semiconductor alloy includes a lower portion that is contained within an upper surface of each of the source region and the drain region, and a vertical pillar portion extending upwardly from the lower portion.

Abstract: Disclosed is a film forming method of an amorphous carbon film, including: disposing a substrate in a processing chamber; supplying a processing gas containing carbon, hydrogen and oxygen into the processing chamber; and decomposing the processing gas by heating the substrate in the processing chamber and depositing the amorphous carbon film on the substrate.

Abstract: A wafer processing method transfers an optical device layer (ODL) in an optical device wafer (ODW) to a transfer substrate. The ODL is formed on the front side of an epitaxy substrate through a buffer layer, and is partitioned by a plurality of crossing streets to define a plurality of regions where optical devices are formed. The transfer substrate is bonded to the front side of the ODL. The transfer substrate and the ODL cut along the streets. The transfer substrate is attached to a supporting member, and a laser beam is applied to the epitaxy substrate from the back side of the epitaxy substrate to the unit of the ODW and the transfer substrate. The focal point of the laser beam is set in the buffer layer, thereby decomposing the buffer layer. The epitaxy substrate is then peeled off from the ODL.

Abstract: A thermal path is formed in a layer transferred semiconductor structure. The layer transferred semiconductor structure has a semiconductor wafer and a handle wafer bonded to a top side of the semiconductor wafer. The semiconductor wafer has an active device layer formed therein. The thermal path is in contact with the active device layer within the semiconductor wafer. In some embodiments, the thermal path extends from the active device layer to a substrate layer of the handle wafer. In some embodiments, the thermal path extends from the active device layer to a back side external thermal contact below the active device layer.

Abstract: A laser cooling system includes a substrate, an REO layer of single crystal rare earth oxide including at least one rare earth element positioned on the surface of the substrate, and an active layer of single crystal semiconductor material positioned on the REO layer to form a semiconductor-on-insulator (SOI) device. Light guiding structure is at least partially formed by the REO layer so as to introduce energy elements into the REO layer and produce cooling by anti-Stokes fluorescence. The active layer of single crystal semiconductor material is positioned on the REO layer in proximity to the light guiding structure so as to receive the cooling.

Abstract: A microphone package structure is provided, including an integrated circuit (IC) structure and a microphone structure disposed thereover and electrically connected therewith. The IC structure includes a first semiconductor substrate with opposite first and second surfaces, and a first through hole disposed in and through the first semiconductor substrate. The microphone structure includes: a second semiconductor substrate with opposite third and fourth surfaces, wherein the third surface faces to the second surface of the first semiconductor substrate; a second through hole disposed in and through the second semiconductor substrate; an acoustic sensing device embedded in the second through hole and adjacent to the third surface; and a sealing layer disposed over the fourth surface of the second semiconductor substrate, defining a back chamber with the sealing layer, wherein the first through hole allows acoustic pressure waves to penetrate and pass therethrough to the acoustic sensing device.

Abstract: A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P? layer, and the P? layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P? layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P? layer. Also provided are a non-transitory computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

Abstract: A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.

Abstract: There are disclosed an epitaxial film, comprising: heating an Si substrate provided with an SiO2 layer with a film thickness of 1.0 nm or more to 10 nm or less on a surface of the substrate; and forming on the SiO2 layer by use of a metal target represented by the following composition formula: yA(1?y)B??(1), in which A is one or more elements selected from the group consisting of rare earth elements including Y and Sc, B is Zr, and y is a numeric value of 0.03 or more to 0.20 or less, the epitaxial film represented by the following composition formula: xA2O3?(1?x)BO2??(2), in which A and B are respectively same elements as A and B of the composition formula (1), and x is a numeric value of 0.010 or more to 0.035 or less.

Abstract: A method for fabricating an image sensor is described. A substrate is provided. Multiple photoresist patterns are formed over the substrate, and then a thermal reflow step is performed to convert the photoresist patterns into multiple microlenses arranged in an array. The focal length of the microlens increases from the center of the array toward the edge of the array.

Abstract: A semiconductor fabrication apparatus and a method of fabricating a semiconductor device using the same performs semiconductor etching and deposition processes at an edge of a semiconductor substrate after disposing the semiconductor substrate at a predetermined place in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus has lower, middle and upper electrodes sequentially stacked. The semiconductor substrate is disposed on the middle electrode. Semiconductor etching and deposition processes are performed on the semiconductor substrate in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus forms electrical fields along an edge of the middle electrode during performance of the semiconductor etching and deposition processes.

Abstract: A method of manufacturing a semiconductor device includes forming a lower film including a cell region and a peripheral circuit region, forming a first sacrificial film on the lower film, the first sacrificial film having trenches in the cell region, forming a second sacrificial pattern on the first sacrificial film, the second sacrificial pattern having line-shaped patterns spaced apart from each other and crossing the trenches in the cell region, and the second sacrificial pattern covering a top surface of the first sacrificial film in the peripheral circuit region, and patterning the first sacrificial film to form upper holes in portions of the trenches exposed by the second sacrificial pattern.

Abstract: A method of manufacturing a semiconductor laser having a diffraction grating includes the steps of forming a first semiconductor layer on a semiconductor substrate; forming periodic projections and recesses which constitute a diffraction grating in the first semiconductor layer; cleaning a surface of the first semiconductor layer with water; drying the surface of the first semiconductor layer; and forming a second semiconductor layer on the first semiconductor layer. In drying the surface of the first semiconductor layer, after replacing water adhering to the surface of the first semiconductor layer with a water-soluble organic solvent, exposing the surface of the first semiconductor layer provided with the projections and recesses to an atmosphere containing the water-soluble organic solvent. At least one of the first semiconductor layer and the second semiconductor layer is composed of a p-type semiconductor.

Abstract: A VCSEL with undoped mirrors. An essentially undoped bottom DBR mirror is formed on a substrate. A periodically doped first conduction layer region is formed on the bottom DBR mirror. The first conduction layer region is heavily doped at a location where the optical electric field is at about a minimum. An active layer, including quantum wells, is on the first conduction layer region. A periodically doped second conduction layer region is connected to the active layer. The second conduction layer region is heavily doped where the optical electric field is at a minimum. An aperture is formed in the epitaxial structure above the quantum wells. A top mirror coupled to the periodically doped second conduction layer region. The top mirror is essentially undoped and formed in a mesa structure. An oxide is formed around the mesa structure to protect the top mirror during wet oxidation processes.

Abstract: An electron transport device, including at least one transport layer in which at least one periodic dislocation and/or defect array is produced, and a mechanism for guiding electrons in the transport layer.

Abstract: Provided is a method of fabricating a semiconductor device. The method of fabricating a semiconductor device includes forming a plurality of magnetic memory patterns spaced apart from each other on a substrate, with each of the magnetic memory patterns including a free pattern, a tunnel barrier pattern, and a reference pattern which are stacked on the substrate, performing a magnetic thermal treatment process on the magnetic memory patterns, and forming a passivation layer on the magnetic memory patterns. The magnetic thermal treatment process and the forming of the passivation layer are simultaneously performed in one reactor.

Abstract: Provided are gas distribution plates (showerheads) for use in an apparatus configured to form a film during, for example, an atomic layer deposition (ALD) process. The gas distribution plate comprises a body defining a thickness and a peripheral edge and has a front surface for facing the substrate. The front surface has a central region with a plurality of openings configured to distribute process gases over the substrate and a focus ring with a sloped region. The focus ring is concentric to the central region such that the thickness at the focus ring is greater than the thickness at the central region.

Abstract: An integrated circuit device includes a bottom wafer, at least one stacking wafer positioned on the bottom wafer, and at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein the bottom wafer and the stacking wafer are bonded by an intervening adhesive layer, and no bump pad is positioned between the bottom wafer and the stacking wafer. A method for preparing an integrated circuit device includes the steps of forming a bottom wafer, forming at least one stacking wafer, bonding the at least one stacking wafer to the bottom wafer by an intervening adhesive layer, and forming at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein no bump pad is positioned between the bottom wafer and the stacking wafer.

Abstract: Provided is a substrate for fabricating a light emitting device and a method for fabricating the light emitting device. The method for fabricating the light emitting device may include forming a sacrificial layer having band gap energy less than energy of a laser irradiated on a substrate, forming a growth layer on the sacrificial layer, forming a light emitting structure including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer on the growth layer, and irradiating the laser onto the sacrificial layer to pass through the substrate, thereby to lift-off the substrate.

Abstract: The substrate processing apparatus includes: a processing chamber for storing and processing substrates stacked in multiple stages in horizontal posture; at least one processing gas supply nozzle which extends running along an inner wall of the processing chamber in the stacking direction of the substrates and supplies a processing gas to the inside of the processing chamber; a pair of inactive gas supply nozzles which are provided so as to extend running along the inner wall of the processing chamber in the stacking direction of the substrates and so as to sandwich the processing gas supply nozzle from both sides thereof along the circumferential direction of the substrates and which supply the inactive gas to the inside of the processing chamber; and an exhaust line for exhausting the inside of the processing chamber.

Abstract: Devices, methods, and systems for wafer bonding are described herein. One or more embodiments include forming a bond between a first wafer and a second wafer using a first material adjacent the first wafer and a second material adjacent the second wafer. The first material includes a layer of gold (Au) and a layer of indium (In), and the second material includes a layer of Au. Forming the bond between the first wafer and the second wafer includes combining the layer of Au in the first material, the layer of In in the first material, and a portion of the layer of Au in the second material, wherein an additional portion of the layer of Au in the second material is not combined with the layer of Au in the first material and the layer of In in the first material.

Abstract: A method of fabricating a silicon carbide substrate that can reduce the fabrication cost of a semiconductor device employing the silicon carbide substrate includes the steps of: preparing a SiC substrate made of single crystal silicon carbide; arranging a base substrate in a vessel so as to face one main face of the SiC substrate; forming a base layer made of silicon carbide so as to contact one main face of the SiC substrate by heating a base substrate to a temperature range greater than or equal to a sublimation temperature of silicon carbide constituting the base substrate. In the step of forming a base layer, a silicon generation source made of a substance including silicon is arranged in the vessel, in addition to the SiC substrate and the base substrate.

Abstract: A through-wafer interconnect and a method for fabricating the same are disclosed. The method starts with a conductive wafer to form a patterned trench by removing material of the conductive wafer. The patterned trench extends in depth from the front side to the backside of the wafer, and has an annular opening generally dividing the conductive wafer into an inner portion and an outer portion whereby the inner portion of the conductive wafer is insulated from the outer portion and serves as a through-wafer conductor. A dielectric material is formed or added into the patterned trench mechanical to support and electrically insulate the through-wafer conductor. Multiple conductors can be formed in an array.

Abstract: Disclosed are a method for fabricating a flexible electronic device using laser lift-off and an electronic device fabricated thereby. More particularly, disclosed are a method for fabricating a flexible electronic device using laser lift-off allowing for fabrication of a flexible electronic device in an economical and stable way by separating a device such as a secondary battery fabricated on a sacrificial substrate using laser, and an electronic device fabricated thereby.

Abstract: The method for forming a multilayer structure on a substrate comprises providing a stack successively comprising an electron hole blocking layer, a first layer made from N-doped semiconductor material having a dopant concentration greater than or equal to 1018 atoms/cm3or P-doped semiconductor material, and a second layer made from semiconductor material of different nature. A lateral electric contact pad is made between the first layer and the substrate, and the material of the first layer is subjected to anodic treatment in an electrolyte.

Abstract: A manufacture method for a gallium-doped monocrystalline silicon solar cell is provided. The method includes classifying the sheets of gallium-doped monocrystalline silicon according to resistivity; texturing and washing the sheets of gallium-doped monocrystalline silicon; diffusing the classified, textured and washed sheets of gallium-doped monocrystalline silicon; etching and depositing the sheets of gallium-doped monocrystalline silicon; and metalizing the sheets of gallium-doped monocrystalline silicon. Advantageously, Light Induced Degradation (LID) is efficiently, economically and conveniently suppressed, the light induced efficiency degradation of monocrystalline silicon solar cell can be controlled within 1%, and meanwhile, the effect of the uneven resistivity distribution of gallium-doped monocrystalline on the cell process is reduced.

Abstract: A CVD showerhead that includes a circular inner showerhead and at least one outer ring showerhead. At least two process gas delivery tubes are coupled to each showerhead. Also, a dual showerhead that includes a circular inner showerhead and at least one outer ring showerhead where each showerhead is coupled to oxygen plus a gas mixture of lead, zirconium, and titanium organometallics. A method of depositing a CVD thin film on a wafer. Also, a method of depositing a PZT thin film on a wafer.

Abstract: A method of fabricating epitaxial semiconductor devices includes: (a) forming an etch limiting film that includes a sacrificial layer on an epitaxial substrate; (b) growing epitaxially layers of a semiconductor structure on the sacrificial layer; (c) forming on the semiconductor structure a layer of a device substrate that can be magnetized, and a patterned passage unit that extends from the device substrate to a depth as deep as the sacrificial layer such that a plurality of semiconductor units are defined in the semiconductor structure and the device substrate; and (d) separating the semiconductor units from the epitaxial substrate by etching laterally the sacrificial layer through the patterned passage unit while a magnetic attraction force is applied to the device substrate.

Abstract: An array of vertical-cavity surface emitting lasers (VCSELs) may be fabricated with very high fill-factors, thereby enabling very high output power densities during pulse, quasi-continuous wave (QCW), and continuous wave (CW) operation. This high fill-factor is achieved using asymmetrical pillars in a rectangular packing scheme as opposed prior art pillar shapes and packing schemes. The use of asymmetrical pillars maintains high efficiency operation of VCSELs by maintaining minimal current injection distance from the metal contacts to the laser active region and by maintaining efficient waste heat extraction from the VCSEL. This packing scheme for very high fill-factor VCSEL arrays is directly applicable for next generation high-power, substrate removed, VCSEL arrays.

Abstract: There are provided methods for functionalizing a planar surface of a microelectronic structure, by exposing the surface to at least one vapor including at least one functionalization species, such as NO2 or CH3ONO, that non-covalently bonds to the surface while providing a functionalization layer of chemically functional groups, to produce a functionalized surface. The functionalized surface is exposed to at least one vapor stabilization species that reacts with the functionalization layer to form a stabilization layer that stabilizes the functionalization layer against desorption from the planar microelectronic surface while providing chemically functional groups. The stabilized surface is exposed to at least one material layer precursor species that deposits a material layer on the stabilized planar microelectronic surface. The stabilized planar microelectronic surface can be annealed at a peak annealing temperature that is less than about 700° C.

Abstract: Provided is a 3D stacked semiconductor integrated circuit including a plurality of chips coupled through a plurality of TSVs. A first chip among the plurality of chips is configured to detect and repair a defective TSV among the plurality of TSVs, and transmit repair information to remaining chips other than the first chip, and the remaining chips other than the first chip are configured to repair the defective TSV in response to the repair information.

Abstract: A method and apparatus for manufacturing a semiconductor device is disclosed, which is capable of realizing an extension of a cleaning cycle for a processing chamber, the method comprising preheating a substrate; placing the preheated substrate onto a substrate-supporting unit provided in a susceptor while the preheated substrate is maintained at a predetermined height from an upper surface of the susceptor provided in a processing chamber; and forming a thin film on the preheated substrate, wherein a temperature of the preheated substrate is higher than a processing temperature for forming the thin film in the processing chamber.

Abstract: Methods of fabricating semiconductor structures and devices include bonding a seed structure to a substrate using a glass. The seed structure may comprise a crystal of semiconductor material. Thermal treatment of the seed structure bonded to the substrate using the glass may be utilized to control a strain state within the seed structure. The seed structure may be placed in a state of compressive strain at room temperature. The seed structure bonded to the substrate using the glass may be used for growth of semiconductor material, or, in additional methods, a seed structure may be bonded to a first substrate using a glass, thermally treated to control a strain state within the seed structure and a second substrate may be bonded to an opposite side of the seed structure using a non-glassy material.

Abstract: Field effect transistors described herein include first and second terminals vertically separated by a channel region. The first and second terminals comprise first and second silicide elements respectively. The first silicide element prevents the migration of carriers from the first terminal into the underlying semiconductor body or adjacent devices which can activate parasitic devices. The first silicide element is also capable of acting as a low resistance conductive line for interconnecting devices or elements. The second silicide element provides a low resistance contact between the second terminal and overlying elements.

Abstract: Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate.

Abstract: The present invention relates to a process for realizing a connecting structure in a semiconductor substrate, and the semiconductor substrate realized accordingly. The semi-conductor substrate has at least a first surface, and is foreseen for a 3D integration with a second substrate along the first surface, wherein the 3D integration is subject to a lateral misalignment in at least one dimension having a misalignment value.

Abstract: An embedded vertical optical grating, a semiconductor device including the embedded vertical optical grating and a method for forming the same. The method for forming the embedded optical grating within a substrate includes depositing a hard mask layer on the substrate, patterning at least one opening within the hard mask layer, vertically etching a plurality of scallops within the substrate corresponding to the at least one opening within the hard mask layer, removing the hard mask layer, and forming an oxide layer within the plurality of scallops to form the embedded vertical optical grating.

Abstract: The invention relates to a semiconductor apparatus and a method of fabrication for a semiconductor apparatus, whereby the semiconductor apparatus includes a semiconductor layer and a passivation layer arranged on a surface of the semiconductor layer and serving for passivating the semiconductor layer surface, whereby the passivation layer comprises a chemically passivating passivation sublayer and a field-effect-passivating passivation sublayer, which are arranged one above the other on the semiconductor layer surface.

Abstract: A method of film deposition using localized plasma to protect bevel edge of a wafer in a plasma chamber. The method includes adjusting an electrode gap between a movable electrode and a stationary electrode, the wafer being disposed on one of the movable electrode and the stationary electrode, to a gap distance configured to prevent plasma formation over a center portion of the wafer, the gap distance also dimensioned such that a plasma-sustainable condition around the bevel edge of the wafer is formed after the adjusting. The method also includes flowing deposition gas into the plasma chamber. The method includes maintaining, using a heater, a chuck temperature that is configured to facilitate film deposition on the bevel edge. The method further includes generating the localized plasma from the deposition gas for depositing a film on the bevel edge.

Abstract: The present invention concerns a method for bonding a first substrate having a first surface to a second substrate having a second surface. This method includes the steps of holding the first substrate by at least two support points, positioning the first substrate and the second substrate so that the first surface and the second surface face each other, deforming the first substrate by applying between at least one pressure point and the two support points a strain toward the second substrate, bringing the deformed first surface and the second surface into contact, and progressively releasing the strain to facilitate bonding of the substrates while minimizing or avoiding the trapping of air bubbles between the substrates.

Abstract: The embodiment provides a semiconductor MP wafer process including processing a plurality of MP wafers in a lot or batch with a first process step. The plurality of the MP wafers is split into an MP wafer group-1 and an MP wafer group-2. At least one of the MP wafers of the MP wafer group-1 is processed with a second process step-1 and at least one of the MP wafers of the MP wafer group-2 is processed with a second process step-2 to form different device components on the MP wafers of the MP wafer group-1 and group-2, respectively. At least one of the MP wafers of the MP wafer group-1 is processed with a third process step-3 and at least one of the MP wafers of the MP wafer group-2 is processed with a third process step-4 to form a substantially same device component on the MP wafers.

Abstract: This invention provides apparatus, protocols, and methods that permit wafers to be loaded and unloaded in a gas-phase epitaxial growth chamber at high temperatures. Specifically, this invention provides a device for moving wafers or substrates that can bath a substrate being moved in active gases that are optionally temperature controlled. The active gases can act to limit or prevent sublimation or decomposition of the wafer surface, and can be temperature controlled to limit or prevent thermal damage. Thereby, previously-necessary temperature ramping of growth chambers can be reduced or eliminated leading to improvement in wafer throughput and system efficiency.