Abstract: A method for manufacturing an SOI substrate in which crystal defects of a single crystal semiconductor layer are reduced is provided. An oxide film containing halogen is formed on each of surfaces of a single crystal semiconductor substrate and of a semiconductor substrate provided with a single crystal semiconductor layer separated from the single crystal semiconductor substrate, whereby impurities that exist on the surfaces of and inside the substrates are decreased. In addition, the single crystal semiconductor layer provided over the semiconductor substrate is irradiated with a laser beam, whereby crystallinity of the single crystal semiconductor layer is improved and planarity is improved.

Abstract: An integrated circuit is provided including a narrow gate stack having a width less than or equal to 65 nm, including a silicide region comprising Pt segregated in a region of the silicide away from the top surface of the silicide and towards an lower portion defined by a pulldown height of spacers on the sidewalls of the gate conductor. In a preferred embodiment, the spacers are pulled down prior to formation of the silicide. The silicide is first formed by a formation anneal, at a temperature in the range 250° C. to 450° C. Subsequently, a segregation anneal at a temperature in the range 450° C. to 550° C. The distribution of the Pt along the vertical length of the silicide layer has a peak Pt concentration within the segregated region, and the segregated Pt region has a width at half the peak Pt concentration that is less than 50% of the distance between the top surface of the silicide layer and the pulldown spacer height.

Abstract: Described herein are composite semiconductor substrates for use in semiconductor device fabrication and related devices and methods. In one embodiment, a composite substrate includes: (1) a bulk silicon layer; (2) a porous silicon layer adjacent to the bulk silicon layer, wherein the porous silicon layer has a Young's modulus value that is no greater than 110.5 GPa; (3) an epitaxial template layer, wherein the epitaxial template layer has a root-mean-square surface roughness value in the range of 0.2 nm to 1 nm; and (4) a set of silicon nitride layers disposed between the porous silicon layer and the epitaxial template layer.

Abstract: Certain embodiments provide a method for manufacturing a semiconductor light emitting device, including: providing a first stack film on a first substrate, the first stack film being formed by stacking a p-type nitride semiconductor layer, an active layer having a multiquantum well structure of a nitride semiconductor, and an n-type nitride semiconductor layer in this order; forming an n-electrode on an upper face of the n-type nitride semiconductor layer; and forming a concave-convex region on the upper face of the n-type nitride semiconductor layer by performing wet etching on the upper face of the n-type nitride semiconductor layer with the use of an alkaline solution, except for a region in which the n-electrode is formed.

Abstract: Misfit dislocations are redirected from the buffer/Si interface and propagated to the Si substrate due to the formation of bubbles in the substrate. The buffer layer growth process is generally a thermal process that also accomplishes annealing of the Si substrate so that bubbles of the implanted ion species are formed in the Si at an appropriate distance from the buffer/Si interface so that the bubbles will not migrate to the Si surface during annealing, but are close enough to the interface so that a strain field around the bubbles will be sensed by dislocations at the buffer/Si interface and dislocations are attracted by the strain field caused by the bubbles and move into the Si substrate instead of into the buffer epi-layer. Fabrication of improved integrated devices based on GaN and Si, such as continuous wave (CW) lasers and light emitting diodes, at reduced cost is thereby enabled.

Abstract: A nitride semiconductor includes: a substrate having a major surface including a first crystal polarity surface and a second crystal polarity surface different from the first crystal polarity surface; and a single polarity layer provided above the major surface and having a single crystal polarity.

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor laminated structure on a substrate as a wafer including semiconductor laser structures; forming a first groove between the semiconductor laser structures on a major surface of the wafer; separating the wafer to laser bars including at least two of the semiconductor laser structures arrayed in a bar shape, after forming the first groove; forming a second groove in the first groove of the laser bars, the second groove having a width no wider than the first groove; and separating one of the laser bars into respective semiconductor lasers along the second groove.

Abstract: A semiconductor device has a satisfactory ohmic contact on a p-type principal surface tilting from a c-plane. The principal surface 13a of a p-type semiconductor region 13 extends along a plane tilting from a c-axis (axis <0001>) of hexagonal group-III nitride. A metal layer 15 is deposited on the principal surface 13a of the p-type semiconductor region 13. The metal layer 15 and the p-type semiconductor region 13 are separated by an interface 17 such that the metal layer functions as a non-alloy electrode. Since the hexagonal group-III nitride contains gallium as a group-III element, the principal surface 13a comprising the hexagonal group-III nitride is more susceptible to oxidation compared to the c-plane of the hexagonal group-III nitride. The interface 17 avoids an increase in amount of oxide after the formation of the metal layer 15 for the electrode.

Abstract: A superlattice layer including a plurality of periods, each of which is formed from a plurality of sub-layers is provided. Each sub-layer comprises a different composition than the adjacent sub-layer(s) and comprises a polarization that is opposite a polarization of the adjacent sub-layer(s). In this manner, the polarizations of the respective adjacent sub-layers compensate for one another.

Abstract: There is provided an inkjet print head including an ink head and a chipping prevention portion. The ink head includes a nozzle for ejecting ink to the outside by a driving force of a piezoelectric actuator mounted on a surface of the ink head. The chipping prevention portion includes a cutting portion disposed at a side of the ink head and being cut so as to have a height lower than that of the nozzle.

Abstract: A quantum dot laser diode and a method of fabricating the same are provided. The quantum dot laser diode includes: a first clad layer formed on an InP substrate; a first lattice-matched layer formed on the first clad layer; an active layer formed on the first lattice-matched layer, and including at least one quantum dot layer formed of an InAlAs quantum dot or an InGaPAs quantum dot which is grown by an alternate growth method; a second lattice-matched layer formed on the active layer; a second clad layer formed on the second lattice-matched layer; and an ohmic contact layer formed on the second clad layer.

Abstract: This invention relates to imaging device and its related transferring technologies to independent substrate able to attain significant broadband capability covering the wavelengths from ultra-violet (UV) to long-Infrared. More particularly, this invention is related to the broadband image sensor (along with its manufacturing technologies), which can detect the light wavelengths ranges from as low as UV to the wavelengths as high as 20 ?m covering the most of the wavelengths using of the single monolithic image sensor on the single wafer. This invention is also related to the integrated circuit and the bonding technologies of the image sensor to standard integrated circuit for multicolor imaging, sensing, and advanced communication. Our innovative approach utilizes surface structure having more than micro-nano-scaled 3-dimensional (3-D) blocks which can provide broad spectral response.

Abstract: In a III-nitride semiconductor laser device, a laser structure includes a support base comprised of a hexagonal III-nitride semiconductor and having a semipolar primary surface, and a semiconductor region provided on the semipolar primary surface of the support base. An electrode is provided on the semiconductor region of the laser structure.

Abstract: An embodiment of a process for realizing a system for recovering heat is described, the process comprising the steps of: formation on a substrate of a plurality of L-shaped down metal structures; deposition of a dielectric layer on the substrate and the plurality of L-shaped down metal structures by using a screen printing approach; definition and opening in the dielectric layer of upper contacts and lower contacts of the L-shaped down metal structures; formation of a plurality of L-shaped up metal structures being connected to the plurality of L-shaped down metal structure in correspondence of the upper and lower contacts so as to form a plurality of serially connected thermocouples, each comprising at least one L-shaped down metal structure and at least one L-shaped up metal structure, being made of different metal materials and interconnected at a junction, the serially connected thermocouples thus realizing the system for recovering heat.

Abstract: Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. In view of the above described object, one feature of the invention is to provide the steps of forming a separation layer over an insulating substrate and forming a thin film integrated circuit having a semiconductor film as an active region over the separation layer, wherein the thin film integrated circuit is not separated. There is less limitation on the shape of a mother substrate in the case of using the insulating substrate, when compared with the case of taking a chip out of a circular silicon wafer. Accordingly, reduction in cost of an IC chip can be achieved.

Abstract: A semiconductor light emitting device made of nitride III-V compound semiconductors is includes an active layer made of a first nitride III-V compound semiconductor containing In and Ga, such as InGaN; an intermediate layer made of a second nitride III-V compound semiconductor containing In and Ga and different from the first nitride III-V compound semiconductor, such as InGaN; and a cap layer made of a third nitride III-V compound semiconductor containing Al and Ga, such as p-type AlGaN, which are deposited in sequential contact.

Abstract: When an insulating layer is provided in order to protect an energy generating element, there arises a possibility that the layer dissolves in a contacting liquid. Therefore, in order to eject liquid, a first protection layer containing metal is provided on the insulating layer facing a substrate for a liquid-ejection head and a second protection layer containing metal is provided on the surface of a liquid supply port to which a base containing silicon is exposed.

Abstract: There are provided a process for producing a semiconductor device and a semiconductor device which allow conductivity distribution to be formed without making refractive index distributed even in a material system of a semiconductor difficult to be subjected to ion implantation. The process for producing a semiconductor device includes the steps of forming a semiconductor layer containing a dopant; forming a concave and convex structure on the semiconductor layer by partially removing the semiconductor layer; and forming a conductivity distribution reflecting the concave and convex structure in the semiconductor layer by performing heat treatment on the semiconductor layer in which the concave and convex structure has been formed at a temperature at which a material forming the semiconductor layer causes mass transport and filling up a hole of a concave portion of the concave and convex structure with the material forming the semiconductor layer.

Abstract: In certain desirable embodiments, the present invention relates to the use of 15N isotopes into GaAsN, InAsN or GaSbN films for ion beam analysis. A semiconductor-nitride assembly for growing and analyzing crystal growth in a group III-V semiconductor sample that includes: a substrate; a buffer layer deposited on the substrate, a nitrogen gas injector to incorporate enriched nitrogen gas and the nitrogen gas injector includes a concentration of enriched nitrogen gas, a thin film consisting of at least one group III element containing compound where at least one group III element is covalently bonded with the nitrogen in the presence of the same or different group V element of the buffer layer, and a proton beam to analyze the incorporation of the nitrogen gas in the thin film layer is described.

Abstract: In a III-nitride light emitting device, the device layers including the light emitting layer are grown over a template designed to reduce strain in the device, in particular in the light emitting layer. Reducing the strain in the light emitting device may improve the performance of the device. The template may expand the lattice constant in the light emitting layer over the range of lattice constants available from conventional growth templates. Strain is defined as follows: a given layer has a bulk lattice constant abulk corresponding to a lattice constant of a free standing material of a same composition as that layer and an in-plane lattice constant ain-plane corresponding to a lattice constant of that layer as grown in the structure. The amount of strain in a layer is |(ain-plane?abulk)|/abulk. In some embodiments, the strain in the light emitting layer is less than 1%.

Abstract: An object of the present invention is to provide a group III nitride semiconductor stacked structure having a high-quality A-plane group III nitride semiconductor layer on an R-plane sapphire substrate. The inventive group III nitride semiconductor stacked structure comprises a substrate composed of R-plane sapphire (?-Al2O3), a buffer layer composed of aluminum gallium nitride (AlxGa1-xN: 0?X?1) formed on said substrate and an underlying layer composed of an A-plane group III nitride semiconductor (AlxGayInzN1-aMa: 0?X?1, 0?Y?1, 0?Z?1, and X+Y+Z=1; wherein, M represents a group V element other than nitrogen (N), and 0?a?1) formed on said buffer layer, wherein the pit density of the surface of said underlying layer is 1×1010 cm?2 or less.

Abstract: Atomic layer deposition apparatus for depositing a film in a continuous fashion. The apparatus includes a process tunnel, extending in a transport direction and bounded by at least a first and a second wall. The walls are mutually parallel and allow a flat substrate to be accommodated there between. The apparatus further includes a transport system for moving a train of substrates or a continuous substrate in tape form, through the tunnel. At least the first wall of the process tunnel is provided with a plurality of gas injection channels that, viewed in the transport direction, are connected successively to a first precursor gas source, a purgegas source, a second precursor gas source and a purge gas source respectively, so as to create a tunnel segment that—in use—comprises successive zones containing a first precursor gas, a purge gas, a second precursor gas and a purge gas, respectively.

Abstract: The present invention provides a plasma treatment apparatus and a conditioning method capable of performing a conditioning for the whole vacuum chamber. A plasma treatment apparatus according to an embodiment of the present invention is provided with a moving means for moving a substrate holder (2) between a reaction chamber (8) and a transfer chamber (9) lying on the under side thereof. Moreover, it has such structure that the exhaust conductance of the reaction chamber (8) becomes large when the substrate holder (2) lies in the transfer chamber. Upon the conditioning, the substrate holder (2) is moved to the transfer chamber (9) to allow diffusing species to spread widely, thereby effectively performing the conditioning for both reaction chamber (8) and transfer chamber (9) in the vacuum chamber (1).

Abstract: A process for forming at least one photovoltaic component on a substrate is described. The substrate comprises a polyimide and a sub-micron filler. The polyimide is derived substantially or wholly from rigid rod monomers and the sub-micron filler has an aspect ratio of at least 3:1. The substrates of the present disclosure are particularly well suited for photovoltaic applications, due at least in part to high resistance to hygroscopic expansion and relatively high levels of thermal and dimensional stability.

Abstract: Light emitting devices include a gallium nitride-based epitaxial structure that includes an active light emitting region and a gallium nitride-based outer layer, for example gallium nitride. A indium nitride-based layer, such as indium gallium nitride, is provided directly on the outer layer. A reflective metal layer or a transparent conductive oxide layer is provided directly on the indium gallium nitride layer opposite the outer layer. The indium gallium nitride layer forms a direct ohmic contact with the outer layer. An ohmic metal layer need not be used. Related fabrication methods are also disclosed.

Abstract: A method of selectively growing a plurality of semiconductor carbon nanotubes using light irradiation. The method includes disposing a plurality of nanodots, which include a catalyst material, on a substrate; growing a plurality of carbon nanotubes from the plurality of nanodots, and irradiating light onto the nanodot to selectively grow the plurality of semiconductor carbon nanotubes.

Abstract: GaN-based heterojunction field effect transistor (HFET) sensors are provided with engineered, functional surfaces that act as pseudo-gates, modifying the drain current upon analyte capture. In some embodiments, devices for sensing nitric oxide (NO) species in a NO-containing fluid are provided which comprise a semiconductor structure that includes a pair of separated GaN layers and an AlGaN layer interposed between and in contact with the GaN layers. Source and drain contact regions are formed on one of the GaN layers, and an exposed GaN gate region is formed between the source and drain contact regions for contact with the NO-containing fluid. The semiconductor structure most preferably is formed on a suitable substrate (e.g., SiC). An insulating layer may be provided so as to cover the semiconductor structure. The insulating layer will have a window formed therein so as to maintain exposure of the GaN gate region and thereby allow the gate region to contact the NO-containing fluid.

Abstract: A detector (100) for detecting neutrons includes a neutron reactive material (102) adapted to interact with neutrons to be detected and release ionizing radiation reaction products in relation to the interactions with neutrons. The detector also includes a first semiconductor element (101) being coupled with the neutron reactive material (102) and adapted to interact with the ionizing radiation reaction products and provide electrical charges proportional to the energy of the ionizing radiation reaction products. In addition electrodes are arranged in connection with the first semiconductor element (101) for providing charge collecting areas (106) for collecting the electrical charges and to provide electrically readable signal proportional to the collected electrical charges. The thickness of the first semiconductor element (101) is adapted to be electrically and/or physically so thin that it is essentially/practically transparent for incident photons, such as background gamma photons.

Abstract: A method of manufacturing a solar cell module, including: forming a laminated body including a first protective member, a first sealing member having a first melting point, a plurality of solar cells, a second sealing member having a second melting point higher than the first melting point, and the second protective member; heating the first sealing member to a temperature equal to or higher than the first melting point but lower than the second melting point; and heating the second sealing member to a temperature equal to or higher than the second melting point. In forming the laminated body, the second sealing member is arranged to form a surface including a plurality of convex portions faces the first sealing member.

Abstract: A semiconductor device which may include a semiconductor layer, and a superlattice interface layer therebetween. The superlattice interface layer may include a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.

Abstract: A chip provided with a layer for separation of a surface region and a hydrophilic surface is manufactured. One or both of a hydrophilic region and a hydrophobic region are formed on a substrate surface where the chip is placed. Liquid is dropped onto the hydrophilic region on the substrate surface, and the chip is placed thereon. The substrate and the chip are heated while being pressure-bonded so that the chip is fixed on the substrate surface, and then the surface region of the chip is separated. By providing a liquid layer in a position where the chip is placed, the chip can be placed on the substrate with high accuracy and thus productivity can be increased.

Abstract: A MOS solid-state imaging device having: a semiconductor substrate provided with a pair of source and drain regions in a pixel area, the pair of source and drain regions constituting part of a transistor in the pixel area; an insulating film formed over the semiconductor substrate; a wiring layer formed over the insulating film; and a contact plug penetrating through the insulating film to connect either one of the pair of source and drain regions with the wiring layer, wherein a surface area of said one of the pair of source and drain regions is silicided, the surface area contacting with the contact plug, and a width of the surface area is equal to a width of the contact plug.

Abstract: The invention relates to a layered structure (1) with semiconducting materials on a support layer (3) comprising at least one planar semiconducting layer (6) and several electrodes, in particular a first (4) and second (5) one. The semiconducting layer (6) has a top (8) and bottom (7) flat face extending essentially parallel and spaced apart from one another by the height of the layer (10). The semiconducting layer (6) is also applied by the bottom flat face (7) to a flat face of the support layer (2) and the two electrodes are connected to the semiconducting layer in an electrically conducting manner The at least two electrodes are applied by means of a structuring process and are disposed on two oppositely lying faces of the semiconducting layer and/or in planes at least approximately parallel between the two faces.

Abstract: Disclosed is a group-III nitride-based light emitting diode. The group-III nitride-based light emitting diode includes a substrate, an n-type nitride-based cladding layer formed on the substrate, a nitride-based active layer formed on the n-type nitride-based cladding layer, a p-type nitride-based cladding layer formed on the nitride-based active layer, and a p-type multi-layered ohmic contact layer formed on the p-type nitride-based cladding layer and including thermally decomposed nitride. The thermally decomposed nitride is obtained by combining nitrogen (N) with at least one metal component selected from the group consisting of nickel (Ni), copper (Cu), zinc (Zn), indium (In) and tin (Sn). An ohmic contact characteristic is enhanced at the interfacial surface of the p-type nitride-based cladding layer of the group-III nitride-based light emitting device, thereby improving the current-voltage characteristics.

Abstract: Fabrication of a solar cell using a printed contact mask. The contact mask may include dots formed by inkjet printing. The dots may be formed in openings between dielectric layers (e.g., polyimide). Intersections of overlapping dots may form gaps that define contact regions. The spacing of the gaps may be dictated by the alignment of nozzles that dispense the dots. Using the dots as a contact mask, an underlying dielectric layer may be etched to form the contact regions through the underlying dielectric layer. Metal contact fingers may be formed over the wafer to form electrical connections to corresponding diffusion regions through the contact regions.

Abstract: A method for manufacturing a solar cell including a substrate, a first electrode layer, a semiconductor layer, and a second electrode layer, includes forming a first sacrificial layer on a portion of a surface of the substrate; forming the first electrode layer on the substrate and on the first sacrificial layer; and dividing the first electrode layer by removing the first sacrificial layer and a portion of the first electrode layer formed on the first sacrificial layer.

Abstract: Substrate processing of a substrate is performed in a processing chamber and the evenness in in-plane film thickness is enhanced. An exhaust unit exhausts the atmosphere in the processing chamber and a processing gas is supplied that is excited by an exciting unit. A rotational drive unit horizontally rotates a support unit that supports a mounting substrate on which the substrate is mounted; and a coolant supply/discharge unit is connected to the lower end of the support unit through a connecting unit. The substrate mounting unit has a coolant circulation path therein. The support unit includes a first coolant flow path for passing coolant through the coolant circulation path. The coolant supply/discharge unit includes a second coolant flow path. The connecting unit connects the first coolant flow path and the second coolant flow path together and is provided outside the processing chamber.

Abstract: There are provided a semiconductor device in which short circuit failures in magnetic resistor elements and the like are reduced, and a method of manufacturing the same. An interlayer insulating film in which memory cells are formed is formed such that the upper surface of the portion of the interlayer insulating film located in a memory cell region where the magnetic resistor elements are formed is at a position lower than that of the upper surface of the portion of the interlayer insulating film located in a peripheral region. Another interlayer insulating film is formed so as to cover the magnetic resistor elements. In the another interlayer insulating film, formed are bit lines electrically coupled to the magnetic resistor elements. Immediately below the magnetic resistor elements, formed are digit lines.

Abstract: One embodiment of the present invention provides a method for fabricating light-emitting diodes (LEDs). The method includes fabricating an InGaAlN-based multilayer LED structure on a conductive substrate. The method further includes etching grooves of a predetermined pattern through the active region of the multilayer LED structure. The grooves separate a light-emitting region from non-light-emitting regions. In addition, the method includes depositing electrode material on the light-emitting and non-light-emitting regions, thereby creating an electrode. Furthermore, the method includes depositing a passivation layer covering the light-emitting and non-light-emitting regions. Moreover, the method includes removing the passivation layer on the electrode to allow the non-light-emitting regions which are covered with the electrode material and the passivation layer to be higher than the light-emitting region and the electrode, thereby protecting the light-emitting region from contact with test equipment.

Abstract: Described herein is a method for manufacturing a nitride semiconductor layer by stacking, on a silicon nitride layer, the first nitride semiconductor layer having a surface inclined with respect to the surface of the silicon nitride layer and then stacking the second nitride semiconductor layer on the first nitride semiconductor layer, a nitride semiconductor element and a nitride semiconductor light-emitting element each including the nitride semiconductor layer; and a method for manufacturing the nitride semiconductor element.

Abstract: A method of selectively attaching a capping agent to an H-passivated Si or Ge surface is disclosed. The method includes providing the H-passivated Si or Ge surface, the H-passivated Si or Ge surface including a set of covalently bonded Si or Ge atoms and a set of surface substitutional atoms, wherein the set of surface substitutional atoms includes at least one of boron atoms, aluminum atoms, gallium atoms, indium atoms, tin atoms, lead atoms, phosphorus atoms, arsenic atoms, sulfur atoms, and bismuth atoms. The method also includes exposing the set of surface functional atoms to a set of capping agents, each capping agent of the set of capping agents having a set of functional groups bonded to a pair of carbon atoms, wherein the pair of carbon atoms includes at least one pi orbital bond, and further wherein a covalent bond is formed between at least some surface substitutional atoms of the set of surface substitutional atoms and at least some capping agents of the set of capping agents.

Abstract: A multijunction solar cell comprising an upper first solar subcell having a first band gap; a middle second solar subcell adjacent to the first solar subcell and having a second band gap smaller than the first band gap, and having a base layer and an emitter layer; a graded interlayer adjacent to said second solar subcell, having a third band gap greater than the second band gap; a lower solar subcell adjacent to the grading interlayer, having a fourth band gap smaller than said second band gap such that the third subcell is lattice mismatched with respect to said second subcell; and a metal electrode layer deposited on said lower subcell and having a coefficient of thermal expansion substantially similar to that of the subcells.

Abstract: Disclosed herein is an article comprising a substrate; an interlayer comprising aluminum nitride, gallium nitride, boron nitride, indium nitride or a solid solution of aluminum nitride, gallium nitride, boron nitride and/or indium nitride; the interlayer being directly disposed upon the substrate and in contact with the substrate; where the interlayer comprises a columnar film and/or nanorods and/or nanotubes; and a group-III nitride layer disposed upon the interlayer; where the group-III nitride layer completely covers a surface of the interlayer that is opposed to a surface in contact with the substrate; the group-III nitride layer being free from cracks.

Abstract: In manufacturing a semiconductor device, a first chamber is provided. An opening couples the first chamber to a first environment through which at least one substrate can pass. A first seal environmentally isolates the first chamber from the first environment. A process chamber is coupled to the first chamber. Another seal environmental isolates the first and the process chambers. The substrate is placed within the first chamber, and the first chamber and the outside environment are isolated. The second opening is opened, and the substrate moves into the semiconductor process chamber. The first chamber is again environmentally isolated from the second volume. A semiconductor processing step is performed on the substrate within the processing chamber. While the substrate is processed, the substrate is rotated and translated through the processing chamber.

Abstract: An n-side electrode that can inhibit the reduction in ohmic properties is provided. The n-side electrode is an n-side electrode for a nitride semiconductor light-emitting element, and includes an Al layer forming an ohmic contact to an n-type nitride semiconductor layer and having a thickness of 30 nm or greater.

Abstract: Provided is a manufacturing method of a semiconductor device, the manufacturing method including forming a first thin film on a substrate; forming a second thin film, which is different from the first thin film, on the first thin film; forming a sacrificial film, which is a film different from the second thin film, on the second thin film; forming a sacrificial film pattern by processing the sacrificial film into a pattern having desired intervals through etching; coating a silicon oxide film on the sacrificial film pattern by intermittently supplying a silicon-containing precursor and an oxygen-containing gas onto the substrate; forming sidewall spacers on the sidewalls of the sacrificial film by etching the silicon oxide film; removing the sacrificial film; and processing the first film and the second film by using the sidewall spacers as a mask.

Abstract: A complementary metal-oxide-semiconductor (CMOS) optical sensor structure includes a pixel containing a charge collection well of a same semiconductor material as a semiconductor layer in a semiconductor substrate and at least another pixel containing another charge collection well of a different semiconductor material than the material of the semiconductor layer. The charge collections wells have different band gaps, and consequently, generate charge carriers in response to light having different wavelengths. The CMOS sensor structure thus includes at least two pixels responding to light of different wavelengths, enabling wavelength-sensitive, or color-sensitive, capture of an optical data.

Abstract: There is provided a method of fabricating InGaAlN film on a silicon substrate, which comprises the following steps of forming a pattern structured having grooves and mesas on the silicon substrate, and depositing InGaAlN film on the surface of substrate, wherein the depth of the grooves is more than 6 nm, and the InGaAlN film formed on the mesas of both sides of the grooves are disconnected in the horizontal direction. The method may grow high quality, no crack and large area of InGaAlN film by simply treating the substrate. At the same time, there is also provided a method of fabricating InGaAlN light-emitting device by using the silicon substrate.

Abstract: The invention relates to a semiconductor device and its layout, which allows a larger number of capacitors within the same area to increase the cell density, which enables to get a larger number of semiconductor chips out of one wafer, and which retains a sufficient gap between bit lines to prevent SAC failure of the storage node, and to a method of fabricating the semiconductor device.

Abstract: A method of fabricating an integrated semiconductor device, comprising: providing a substrate having a first region and a second region; and forming a semiconductor unit on the first region and forming a micro electro mechanical system (MEMS) unit on the second region in one process.