Abstract: In a conventional optical device which mounts a semiconductor light emitting element, the processing is difficult and a manufacturing process cost is expensive because of the necessity of forming via holes in a substrate. An optical device comprises a laser diode which needs heat radiation, a glass substrate which is integrally molded into a mold glass for arranging the laser diode, a metallic heat sink arranged at an edge of the glass substrate for radiating heat generated from the laser diode, wherein an active layer proximity surface of the laser diode is arranged to oppose the heat sink, both of them are connected with a conductive paste through a lateral groove formed in the glass substrate.

Abstract: A method of manufacturing semiconductor laser device including a GaN wafer includes forming a semiconductor layer on the GaN wafer and on which ridge portions are formed. Grooves are formed in the semiconductor layer such that each groove is disposed in line with the scribe marks, between each of the ridge portions and an upstream scribe mark. The grooves are curved and convex outwardly towards a downstream side, and each groove has an apex on a cleavage line. The side extending from the apex preferably does not form an angle of 60 degrees with respect to a cleavage direction or the cleavage line.

Abstract: A non-volatile semiconductor storage device includes a plurality of memory element groups, each of the memory element groups having a plurality of memory elements, each of the memory elements having a resistance-change element and a Schottky diode connected in series. Each of the memory element groups includes: a first columnar layer extending in a lamination direction; a first insulation layer formed on a side surface of the first columnar layer and functioning as the resistance-change element; and a first conductive layer formed to surround the first columnar layer via the first insulation layer. The first conductive layer is formed of metal. The first columnar layer is formed of a semiconductor having such a impurity concentration that the first conductive layer and the semiconductor configure the Schottky diode.

Abstract: A full color display comprising a red, a green, and a blue light emitting diode, each light emitting diode including a light emitting region having at least one layer of single crystal rare earth material, the rare earth material in each of the light emitting diodes having at least one radiative transition, and the rare earth material producing a radiation wavelength of approximately 640 nm in the red light emitting diode, 540 nm in the green light emitting diode, and 460 nm in the blue light emitting diode. Generally, the color of each LED is determined by selecting a rare earth with a radiative transition producing a radiation wavelength at the selected color. In cases where the rare earth has more than one radiative transition, tuned mirrors can be used to select the desired color.

Abstract: A pressure sensor chip is described. The pressure sensor chip include a substrate, a polycrystalline silicon layer, at least one silicon layer, and a diaphragm movement element. The polycrystalline silicon layer is formed on the substrate and has a cavity recess formed therein. The at least one silicon layer is formed on the polycrystalline silicon layer and covers the cavity recess thereby forming a reference chamber with a diaphragm. The diaphragm movement element is configured to sense movement of the diaphragm. An assembly incorporating the pressure sensor chip and a method of forming the pressure sensor chip are also described.

Abstract: A photonic crystal laser comprises an n-type substrate, an n-type clad layer, an active layer, a p-type clad layer, a photonic crystal layer, a p-type electrode, an n-type electrode and a package member. The n-type clad layer is formed on a first surface of the n-type substrate. The active layer is formed on the n-type clad layer. The p-type clad layer is formed on the active layer. The photonic crystal layer is formed between the n-type clad layer and the active layer or between the active layer and the p-type clad layer, and includes a photonic crystal portion. The p-type electrode is formed on the photonic crystal portion. The n-type electrode is formed on a second surface, and includes a light-transmitting portion arranged on a position opposed to the photonic crystal portion and an outer peripheral portion having lower light transmittance than the light-transmitting portion.

Abstract: The present invention is a method of fabricating an optical device using multiple sacrificial spacer layers. The first step in this process is to fabricate the underlying base structure and deposit an optical structure thereon. A facet is then created at the ends of the optical structure and alternating sacrificial and intermediate layers are fabricated on the device. A mask layer is deposited on the structure, with openings created in the layers to allow use of an etchant. User-defined portions of the spacer layers are subsequently removed with the etchant to create air gaps between the intermediate layers.

Abstract: Provided is a vertical nitride-based LED including a first electrode; a first nitride semiconductor layer that is disposed on the first electrode; an active layer that is disposed on the first nitride semiconductor layer; a second nitride semiconductor layer that is disposed on the active layer; an ohmic contact pattern that is disposed on the second nitride semiconductor layer; a second electrode that is disposed on the ohmic contact pattern; and a bonding pad that is electrically connected to the second electrode and disposed on the second nitride semiconductor layer.

Abstract: An array substrate for a liquid crystal display device and a fabrication method thereof, and a liquid crystal display device having the same are disclosed. The array substrate for a liquid crystal display device and a fabrication method thereof, and a liquid crystal display device having the same according to the present disclosure eliminate optical loss by use of a shielding film that can decrease the optic leakage current to minimize the optic leakage loss, thus it is possible to improve the picture quality.

Abstract: It is an object of the present invention to provide a crystal silicon element emitting a desired visible light at high efficiency, by markedly enhancing the crystallinity of the nano Si. A p-type single crystal silicon substrate 10, a thick silicon oxide film 17a and a thin silicon oxide film 17b are disposed on the one surface of the silicon substrate 10. On the thin silicon oxide film 17b, plural nano Si 15 having the same crystal axis as the silicon substrate 10 are formed. In addition, a thin silicon oxide film 16 that is disposed in a manner that the thin silicon film 16 covers the upper and side faces of the nano Si 15, and a transparent electrode (for example ITO) 19 that is disposed in a manner that the transparent electrode 19 covers at least the upper face of the nano Si 15 are formed. Further, a metal electrode 18 (for example, aluminum) is formed in a manner that the metal electrode 18 has an ohmic contact with the other surface of the silicon substrate 10.

Abstract: Formation of carbon-substituted single crystal silicon layer is prone to generation of large number of defects especially at high carbon concentration. The present invention provides structures and methods for providing low defect carbon-substituted single crystal silicon layer even for high concentration of carbon in the silicon. According to the present invention, the active retrograde profile in the carbon implantation reduces the defect density in the carbon-substituted single crystal silicon layer obtained after a solid phase epitaxy. This enables the formation of semiconductor structures with compressive stress and low defect density. When applied to semiconductor transistors, the present invention enables N-type field effect transistors with enhanced electron mobility through the tensile stress that is present into the channel.

Abstract: Provided is a quantum dot-metal oxide complex including a quantum dot and a metal oxide forming a 3-dimensional network with the quantum dot. In the quantum dot-metal oxide complex, the quantum dot is optically stable without a change in emission wavelength band and its light-emitting performance is enhanced.

Abstract: A wafer bonding process that compensates for curvatures in wafer surfaces, and a wafer stack produced by the bonding process. The process entails forming a groove in a surface of a first wafer, depositing a bonding stack on a surface of a second wafer, aligning and mating the first and second wafers so that the bonding stack on the second wafer contacts a bonding site on the first wafer, and then heating the first and second wafers to reflow the bonding stack. The groove either surrounds the bonding site or lies entirely within the bonding site, and the heating step forms a molten bonding material, causes at least a portion of the molten bonding material to flow into the groove, and forms a bonding structure that bonds the second wafer to the first wafer. Bonding stacks having different lateral surface areas can be deposited to form bonding structures of different heights to compensate for variations in the wafer gap.

Abstract: A method for pulsed plasma deposition of titanium dioxide film is revealed. The method includes the steps of: (1) set a substrate into a chamber and the chamber is pumped down to a certain vacuum level. (2) Introduce titanium tetraisopropoxide gas and gas containing oxygen into the chamber and a RF (radio frequency) pulse power supply is turned on to create a glow discharge for generating pulsed plasma. (3) A layer of titanium dioxide film is deposited on the substrate by the pulsed plasma. The TiO2 film is deposited on a substrate such as plastic substrate at low temperature according to the method so that the heat-resistant and conductive requirements of conventional substrates are removed.

Abstract: A method for manufacturing a semiconductor optical device includes: forming a p-type cladding layer; forming a capping layer on the p-type cladding layer, the capping layer being selectively etchable relative to the p-type cladding layer; forming a through film on the capping layer; forming a window structure by ion implantation; removing the through film after the ion implantation; and selectively removing the capping layer using a chemical solution.

Abstract: The present invention is a method of fabricating an optical device using multiple sacrificial spacer layers. The first step in this process is to fabricate the underlying base structure and deposit an optical structure thereon. A facet is then created at the ends of the optical structure and alternating sacrificial and intermediate layers are fabricated on the device. A mask layer is deposited on the structure, with openings created in the layers to allow use of an etchant. User-defined portions of the spacer layers are subsequently removed with the etchant to create air gaps between the intermediate layers.

Abstract: Semiconductor wafers composed of monocrystalline silicon and doped with nitrogen contain an OSF region and a PV region, wherein the OSF region extends from the center radially toward the edge of the wafer as far as the Pv region; the wafer has an OSF density of less than 10 cm?2, a BMD density in the bulk of at least 3.5×108 cm?3, and a radial distribution of the BMD density with a fluctuation range BMDmax/BMDmim of not more than 3. The wafers are produced by controlling initial nitrogen content and maintaining oxygen within a narrow window, followed by a heat treatment.

Abstract: An image sensor comprising at least: CMOS-type photodiodes and transistors produced in a semiconductor layer having a thickness of between approximately 1 ?m and 1.5 ?m, a dielectric layer in which electrical interconnect layers are made, which are electrically connected to one another and/or to the CMOS photodiodes and/or transistors, said dielectric layer being arranged against a first face of the semiconductor layer opposite a second face of the semiconductor layer through which the light received by the sensor from the exterior is intended to enter, light-reflecting means arranged in the dielectric layer, opposite the photodiodes, and capable of reflecting at least a portion of the light received by the sensor towards the photodiodes.

Abstract: A GaN layer functions as an electron transit layer and is formed to exhibit, at least at a portion thereof, A/B ratio of 0.2 or less obtained by a photoluminescence measurement, where “A” is the light-emission intensity in the 500-600 nm band, and “B” is the light-emission intensity at the GaN band-edge.

Abstract: The invention relates to a method of fabricating and electromechanical device on at least one substrate, the device including at least one active element and wherein the method comprises: a) making a heterogeneous substrate comprising a first portion, an interface layer, and a second portion, the first portion including one or more buried zones sandwiched between first and second regions formed in a first monocrystalline material, the first region extending to the surface of the first portion, and the second region extending to the interface layer, at least one said buried zone being made at least in part out of a second monocrystalline material so as to make it selectively attackable relative to the first and second regions; b) making openings from the surface of the first portion and through the first region, which openings open out to at least one said buried zone; and c) etching at least part of at least one buried zone to form at least one cavity so as to define at least one active element that is at

Abstract: Normally-off semiconductor devices are provided. A Group III-nitride buffer layer is provided. A Group III-nitride barrier layer is provided on the Group III-nitride buffer layer. A non-conducting spacer layer is provided on the Group III-nitride barrier layer. The Group III-nitride barrier layer and the spacer layer are etched to form a trench. The trench extends through the barrier layer and exposes a portion of the buffer layer. A dielectric layer is formed on the spacer layer and in the trench and a gate electrode is formed on the dielectric layer. Related methods of forming semiconductor devices are also provided herein.

Abstract: A wafer for backside illumination type solid imaging device has a plurality of pixels inclusive of a photoelectric conversion device and a charge transfer transistor at its front surface side and a light receiving surface at its back surface side, wherein said wafer is a SOI wafer obtained by forming a given active layer on a support substrate made of C-containing n-type semiconductor material through a chemical oxide film having a thickness of not more than 1 nm.

Abstract: A method of manufacturing a semiconductor device based on a SiC substrate (12), comprising the steps of forming (201) an oxide layer (14) on a Si-terminated face of the SiC substrate (12) at an oxidation rate sufficiently high to achieve a near interface trap density below 5×1011 cm?2; and annealing (202) the oxidized SiC substrate in a hydrogen-containing environment, in order to passivate deep traps formed in the oxide-forming step, thereby enabling manufacturing of a SiC-based MOSFET (10) having improved inversion layer mobility and reduced threshold voltage. It has been found by the present inventors that the density of DTs increases while the density of NITs decreases when the Si-face of the SiC substrate is subject to rapid oxidation. According to the present invention, the deep traps formed during the rapid oxidation can be passivated by hydrogen annealing, thus leading to a significantly decreased threshold voltage for a semiconductor device formed on the oxide.

Abstract: A photovoltaic device module and a fabrication method thereof are disclosed. There are provided a solar cell module structure effective to prevent the performance of the overall module from being degraded when photoelectric conversion efficiency of a specific portion cell is degraded in a solar cell module in which solar cells are integrated, and a fabrication method thereof. More particularly, there are provided a module structure having two terminal wirings, in which one of them is formed by selecting and connecting at least two unit cells from a plurality of unit cells electrically connected and the other is formed by selecting and connecting at least two unit cells differentiated from the said selected unit cells., and a fabrication method thereof.

Abstract: A method of growing carbon nanotubes and a method of manufacturing a field emission device using the same is provided. The method of growing carbon nanotubes includes steps of preparing a substrate, forming a catalyst metal layer on the substrate to promote growing of carbon nanotubes, forming an inactivation layer on the catalyst metal layer to reduce the activity of the catalyst metal layer, and growing carbon nanotubes on a surface of the catalyst metal layer. Because the inactivation layer partially covers the catalyst metal layer, carbon nanotubes are grown on a portion of the catalyst metal layer that is not covered by the inactivation layer. Thus, density of the carbon nanotubes can be controlled. This method for growing carbon nanotubes can be used to make an emitter of a field emission device. The field emission device having carbon nanotube emitter made of this method has superior electron emission characteristics.

Abstract: Photovoltaic devices and methods of making photovoltaic devices are provided. The photovoltaic device comprises a plurality of solar cells electrically coupled to each other. The plurality of solar cells are formed of respective semiconductor material having different band gaps. Each solar cell includes a plurality of sub-junctions having a respective plurality of p-n junctions and at least one tunnel junction located between juxtaposed sub-junctions of the plurality of sub-junctions.

Abstract: In one embodiment of the present invention, in a method of fabricating a nitride semiconductor laser device, after an insulating film is formed on a layered nitride semiconductor portion on a substrate, a resist mask is formed on the insulating film, such that the insulating film is exposed near a position where an exit-side cleaved facet and a reflection-side cleaved facet are formed. The insulating film near a position where the exit-side cleaved facet and the reflection-side cleaved facet are formed is then removed, and, after the resist mask is removed, cleavage is performed. As a result, even if the substrate and the layered nitride semiconductor portion are cleaved at a position where the exit-side cleaved facet and the reflection-side cleaved facet are formed, the insulating film is not broken. This helps prevent fragments produced from the insulating film from being adhered to the exit-side cleaved facet and to the reflection-side cleaved facet.

Abstract: To grasp an accumulation state of residual matters inside of a vaporizer without decomposing the vaporizer, and grasp the timing of performing maintenance to the inside of the vaporizer in advance.

Abstract: Semiconductor structures and devices based thereon include an aluminum nitride single-crystal substrate and at least one layer epitaxially grown thereover. The epitaxial layer may comprise at least one of AlN, GaN, InN, or any binary or tertiary alloy combination thereof, and have an average dislocation density within the semiconductor heterostructure is less than about 106 cm?2.

Abstract: A thin film type solar cell and a method for manufacturing the same is disclosed, wherein the thin film type solar cell includes a first anti-oxidation layer formed on a front electrode, and a semiconductor layer formed on the first anti-oxidation layer, so that it is possible to prevent an oxide from being formed in the interface between the front electrode and the semiconductor layer by preventing a reaction between an oxidant contained in the front electrode and silicon of the semiconductor layer, to thereby realize improved cell efficiency, wherein the method for manufacturing the thin film type solar cell comprises forming the front electrode on a substrate; forming the first anti-oxidation layer on the front electrode; forming the semiconductor layer on the first anti-oxidation layer; and forming a rear electrode on the semiconductor layer.

Abstract: A method of fabricating a semiconductor transistor device is provided. The fabrication method begins by forming a gate structure overlying a layer of semiconductor material, such as silicon. Then, spacers are formed about the sidewalls of the gate structure. Next, ions of an amorphizing species are implanted into the semiconductor material at a tilted angle toward the gate structure. The gate structure and the spacers are used as an ion implantation mask during this step. The ions form amorphized regions in the semiconductor material. Thereafter, the amorphized regions are selectively removed, resulting in corresponding recesses in the semiconductor material. In addition, the recesses are filled with stress inducing semiconductor material, and fabrication of the semiconductor transistor device is completed.

Abstract: Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. In view of the above described object, one feature of the invention is to provide the steps of forming a separation layer over an insulating substrate and forming a thin film integrated circuit having a semiconductor film as an active region over the separation layer, wherein the thin film integrated circuit is not separated. There is less limitation on the shape of a mother substrate in the case of using the insulating substrate, when compared with the case of taking a chip out of a circular silicon wafer. Accordingly, reduction in cost of an IC chip can be achieved.

Abstract: A trenched semiconductor power device that includes a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. Each of the body regions extended between two adjacent trenched gates further having a gap exposing a top surface above an epitaxial layer above said semiconductor substrate. The trenched semiconductor power device further includes a Schottky junction barrier layer covering the top surface above the epitaxial layer between the trenched gate thus forming embedded Schottky diodes between adjacent trenched gates.

Abstract: In the formation of a multilayer interference filter that is included in a solid-state imaging device, at the outset, a titanium dioxide layer (401), a silicon dioxide layer (402), a titanium dioxide layer (403), and a spacer layer are successively laminated on an interlayer insulation film (304) to form a lower films. Next, the reflectance characteristics of the lower films are measured to specify the thickness of the lower films. When the thickness is deviated from the design value, the thickness of the spacer layer (404), and the thickness of upper films that include titanium dioxide layers (407, 409) and silicon dioxide layers (408, 410) are changed. Then, according to the changes, the spacer layer (404) is etched to regulate the thickness, and the upper films are formed thereon.

Abstract: A compound semiconductor light-emitting device which includes an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer, that are made of a compound semiconductor, formed on a substrate, the n-type semiconductor layer and the p-type semiconductor layer are stacked so as to interpose the light-emitting layer therebetween, a first conductive transparent electrode and a second conductive electrode. The first conductive transparent electrode is made of an IZO film containing an In2O3 crystal having a bixbyite structure. Also discussed is a method of manufacturing the device.

Abstract: A method of fabricating a T-gate HEMT with a club extension comprising the steps of: providing a substrate; providing a bi-layer resist on the substrate; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to a T-gate opening; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to the shape of the club extension wherein the area corresponding to the club extension is approximately 1 micron to an ohmic source side of a T-gate and approximately 0.5 microns forward from a front of the T-gate; developing out the bi-layer resist in the exposed area that corresponds to the T-gate opening; developing out the bi-layer resist in the exposed area that corresponds to the club extension; and forming the T-gate and club extension through a metallization process.

Abstract: A photovoltaic system includes a first submodule and a second submodule connected in parallel.

Abstract: A thick film conductive composition comprising electrically conductive material, rhodium-containing additive, one or more glass frits, and an organic medium.

Abstract: A nitride-based semiconductor laser device includes a nitride-based semiconductor layer formed on a main surface of a substrate and having an emission layer, wherein the nitride-based semiconductor layer includes a first side surface formed by a (000-1) plane and a second side surface inclined with respect to the first side surface, and a ridge having an optical waveguide extending perpendicular to a [0001] direction in an in-plane direction of the main surface of the substrate is formed by a region held between the first side surface and the second side surface.

Abstract: The present invention generally relates to thin film transistors (TFTs) and methods of making TFTs. The active channel of the TFT may comprise one or more metals selected from the group consisting of zinc, gallium, tin, indium, and cadmium. The active channel may also comprise nitrogen and oxygen. To protect the active channel during source-drain electrode patterning, an etch stop layer may be deposited over the active layer. The etch stop layer prevents the active channel from being exposed to the plasma used to define the source and drain electrodes. The etch stop layer and the source and drain electrodes may be used as a mask when wet etching the active material layer that is used for the active channel.

Abstract: A method that combines alternate low/medium ion dose implantation with rapid thermal annealing at relatively low temperatures. At least one dopant is implanted in one of a single crystal and an epitaxial film of the wide band gap compound by a plurality of implantation cycles. The number of implantation cycles is sufficient to implant a predetermined concentration of the dopant in one of the single crystal and the epitaxial film. Each of the implantation cycles includes the steps of: implanting a portion of the predetermined concentration of the one dopant in one of the single crystal and the epitaxial film; annealing one of the single crystal and the epitaxial film and implanted portion at a predetermined temperature for a predetermined time to repair damage to one of the single crystal and the epitaxial film caused by implantation and activates the implanted dopant; and cooling the annealed single crystal and implanted portion to a temperature of less than about 100° C.

Abstract: An integrated circuit (IC) substrate (32) comprising a germanium layer (26), an aluminium oxide layer (22), and an interfacial layer (28) provided on the germanium layer between the germanium layer and the aluminium oxide layer, which interfacial layer provides control of electrical properties at an interface between the germanium layer and the interfacial layer. The electrical properties may comprise charge carrier trap density, and the interfacial layer may provide control of the charge carrier trap density to minimise the trap density. The interfacial layer is used to ensure an intimate, high-quality germanium layer—interfacial layer interface. A method manufacturing an IC substrate is also provided, along with a gallium arsenide circuit integrated in a system-on-chip (SOC) comprising an IC substrate, and a germanium electronic circuit in combination with a gallium arsenide circuit, integrated in a system-on-chip—(SOC), comprising an IC substrate.

Abstract: A ZnO based semiconductor device includes: a lamination structure including a first semiconductor layer containing ZnO based semiconductor of a first conductivity type and a second semiconductor layer containing ZnO based semiconductor of a second conductivity type opposite to the first conductivity type, formed above the first semiconductor layer and forming a pn junction together with the first semiconductor layer; and a Zn—Si—O layer containing compound of Zn, Si and O and covering a surface exposing the pn junction of the lamination structure.

Abstract: The invention concerns a chemical sensor comprising at least one cantilever sensor unit with a capture surface for a chemical substance to be detected. The cantilever comprises a piezoresistor of doped single crystalline silicon with a pair of wires for applying an electrical field over the piezoresistor, and a current shield capable of shielding the piezoresistor electrically from a liquid for a sufficient time to performing a measurement when a liquid sample is applied in contact with the capture surface. The current shield comprises one or more of the materials selected from the group consisting of nitrides, such as silicon nitride, metal oxides, such as aluminum oxide, ceramics, diamond films, silicon carbide, tantalum oxide, single crystalline silicon, glass mixtures and combinations thereof, said current shield preferably comprises one or more of the materials silicon nitride and single crystalline silicon. The invention also relates to methods of preparing such chemical sensor.

Abstract: A method of preparing active silicon regions for CMOS or other devices includes providing a structure including a silicon substrate (210, 410) having formed thereon first and second silicon diffusion lines (110, 420), both of which include first and second silicon layers (211, 213, 421, 423), a silicon germanium layer (212, 422), and a mask layer (214, 424). The method further includes forming an oxide layer (430) in first and second regions of the structure, forming a polysilicon layer (510) over the oxide layer, removing the polysilicon layer from the first region and depositing oxide (610) therein in order to form an oxide anchor, removing the polysilicon layer from the second region, removing the silicon germanium layer, filling the first and second gaps with an electrically insulating material (910), and depositing oxide in the second region.

Abstract: There are provided a semiconductor device having a structure which can realize not only suppression of a punch-through current but also reuse of a silicon wafer used for bonding, in manufacturing a semiconductor device using an SOI technique, and a manufacturing method thereof. A semiconductor film into which an impurity imparting a conductivity type opposite to that of a source region and a drain region is implanted is formed over a substrate, and a single crystal semiconductor film is bonded to the semiconductor film by an SOI technique to form a stacked semiconductor film. A channel formation region is formed using the stacked semiconductor film, thereby suppressing a punch-through current in a semiconductor device.

Abstract: A group-III nitride semiconductor stack comprises a single-crystal substrate, a first group-III nitride layer formed on a principal surface of the single-crystal substrate, a graded low-temperature deposited layer formed on the group-III nitride layer and made of nitride in which group-III element composition is continuously changed, and a second group-III nitride layer formed on the graded low-temperature deposited layer.

Abstract: In a III-nitride light emitting device, the device layers including the light emitting layer are grown over a template designed to reduce strain in the device, in particular in the light emitting layer. Reducing the strain in the light emitting device may improve the performance of the device. The template may expand the lattice constant in the light emitting layer over the range of lattice constants available from conventional growth templates. Strain is defined as follows: a given layer has a bulk lattice constant abulk corresponding to a lattice constant of a free standing material of a same composition as that layer and an in-plane lattice constant ain-plane corresponding to a lattice constant of that layer as grown in the structure. The amount of strain in a layer is |(ain-plane?abulk)|/abulk. In some embodiments, the strain in the light emitting layer is less than 1%.

Abstract: A digital x-ray detector and its fabrication method are disclosed to strengthen an electrical connection between an upper electrode and a lower by employing a multi-contact hole structure and obtaining reliability of a contact hole by electrically connecting the side of the lower line and the upper electrode. A semiconductor layer is inserted at a lower portion of the contact hole to prevent damage of a gate insulating layer possibly caused by an overetch to thus reduce a defective contact.

Abstract: Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer over the substrate, and a stacked gate structure of SiGe and/or Si:C having stresses produced at the interfaces of SSi (strained Si)/SiGe or SSi/Si:C in the stacked gate structure. The stacked gate structure has a first stressed film layer of large grain size Si or SiGe over the gate dielectric layer, a second stressed film layer of strained SiGe or strained Si:C over the first stressed film layer, and a semiconductor or conductor such as p(poly)-Si over the second stressed film layer.