Abstract: A semiconductor process and apparatus fabricate a metal gate electrode (30) and an integrated semiconductor resistor (32) by forming a metal-based layer (26) and semiconductor layer (28) over a gate dielectric layer (24) and then selectively implanting the resistor semiconductor layer (28) in a resistor area (97) to create a conductive upper region (46) and a conduction barrier (47), thereby confining current flow in the resistor semiconductor layer (36) to only the top region (46) in the finally formed device.

Abstract: Semiconductor devices including through-wafer interconnects are disclosed. According to an embodiment of the present invention, a semiconductor device may comprise a substrate having a first surface and a second, opposing surface, and a through-wafer interconnect extending into the first surface of the substrate. The through-wafer interconnect may include an electrically conductive material extending from the first surface of the substrate to the second, opposing surface of the substrate. The through-wafer interconnect may also include a first dielectric material disposed between the electrically conductive material and the substrate and extending from the second, opposing surface of the substrate to the first portion of the conductive material.

Abstract: Disclosed herein is an RF printed rectifier manufactured using a roll to roll printing process, comprising: a printed antenna manufactured using conductive ink through the roll to roll printing process; a printed diode manufactured using the conductive ink through the roll to roll printing process; and a printed capacitor manufactured using the conductive ink through the roll to roll printing process, wherein an alternating current is input through the printed antenna, and a direct current is output through the printed diode and capacitor.

Abstract: A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 ?m-10 ?m thick edge process-induced degradation layer.

Abstract: A process and apparatus for making silicon or silicon/germanium core fiber is described, which uses a plasma process with reducing agent to make preform. The process also makes the recommendations in selecting the adequate cladding tube for better fiber properties. An improved fiber drawing apparatus is also disclosed in order to draw this new type of preforms.

Abstract: A method of manufacturing an SiC semiconductor device includes the steps of ion implanting a dopant at least in a part of a surface of an SiC single crystal, forming an Si film on the surface of the ion-implanted SiC single crystal, and heating the SiC single crystal on which the Si film is formed to a temperature not less than a melting temperature of the Si film.

Abstract: A method for making a flexible semiconductor device includes the following steps. A rigid substrate is provided. A flexible substrate is provided, and placed on the rigid substrate. A semiconductor device is directly formed on the flexible substrate using a semiconductor process. After the rigid substrate is removed, the flexible semiconductor device is formed.

Abstract: A light-emitting device includes a substrate, a first doped semiconductor layer situated above the substrate, a second doped semiconductor layer situated above the first doped layer, and a multi-quantum-well (MQW) active layer situated between the first and the second doped layers. The device also includes a first electrode coupled to the first doped layer and a first passivation layer situated between the first electrode and the first doped layer in areas other than an ohmic-contact area. The first passivation layer substantially insulates the first electrode from edges of the first doped layer, thereby reducing surface recombination. The device further includes a second electrode coupled to the second doped layer and a second passivation layer which substantially covers the sidewalls of the first and second doped layers, the MQW active layer, and the horizontal surface of the second doped layer.

Abstract: A trenched semiconductor power device that includes a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. Each of the body regions extended between two adjacent trenched gates further having a gap exposing a top surface above an epitaxial layer above said semiconductor substrate. The trenched semiconductor power device further includes a Schottky junction barrier layer covering the top surface above the epitaxial layer between the trenched gate thus forming embedded Schottky diodes between adjacent trenched gates.

Abstract: A thick gallium nitride (GaN) film is formed on a LiAlO2 substrate through two stages. First, GaN nanorods are formed on the LiAlO2 substrate through chemical vapor deposition (CVD). Then the thick GaN film is formed through hydride vapor phase epitaxy (HVPE) by using the GaN nanorods as nucleus sites. In this way, a quantum confined stark effect (QCSE) becomes small and a problem of spreading lithium element into gaps in GaN on using the LiAlO2 substrate is mended.

Abstract: An integrated semiconductor optical device and an optical module capable of the high-speed and large-capacity optical transmission are provided. In an integrated semiconductor optical device in which a plurality of optical devices buried with semi-insulating semiconductor materials are integrated on the same semiconductor substrate and an optical module using the integrated semiconductor optical device, configurations (material and electrical characteristics) of the buried layers are made different for each of the optical devices.

Abstract: A light emitting device comprising a staggered composition quantum well.

Abstract: A semiconductor region having an upper surface and a side surface is formed on a substrate. A first impurity region is formed in an upper portion of the semiconductor region. A second impurity region is formed in a side portion of the semiconductor region. The resistivity of the second impurity region is substantially equal to or smaller than that of the first impurity region.

Abstract: Example embodiments provide triple-gate semiconductor devices isolated by reverse shallow trench isolation (STI) structures and methods for their manufacture. In an example process, stacked layers including a form layer over a dielectric layer can be formed over a semiconductor substrate. One or more trenches can be formed by etching through the stacked layers. The one or more trenches can be filled by an active area material to form one or more active areas, which can be isolated by remaining portions of the dielectric layer. Bodies of the active area material can be exposed by removing the form layer. One or more triple-gate devices can then be formed on the exposed active area material. The example triple-gate semiconductor devices can control the dimensions for the active areas and provide less isolation spacing between the active areas, which optimizes manufacturing efficiency and device integration quality.

Abstract: A substrate processor enables realization of a proper process by combining advantages of a remote plasma and a plasma generated in an entire processing chamber. The substrate processor includes a conductive member (10) which is installed surrounding a processing space (1) and grounded to the earth and a pair of electrodes (4) installed inside the conductive member (10). A primary coil of an insulating transformer (7) is connected to a high-frequency power supply unit (14) and a secondary coil is connected to the electrodes (4). A switch (13) is connected to the connection line connecting the secondary coil to the electrodes (4). By setting up/cutting off the connection of the line to the earth with use of the switch (13), the region where the plasma is generated in the processing space (1) can be changed.

Abstract: The invention is a vertical geometry light emitting diode capable of emitting light in the electromagnetic spectrum having a substrate, a lift-off layer, a strain relieved superlattice layer, a first doped layer, a multilayer quantum wells comprising alternating layers quantum wells and barrier layers, a second doped layer, a third doped layer and a metallic contact that is in a vertical geometry orientation. The different layers consist of a compound with the formula AlxlnyGa(1-x-y)N, wherein x is more than 0 and less than or equal to 1, y is from 0 to 1 and x+y is greater than 0 and less than or equal to 1. The barrier layer on each surface of the quantum well has a band gap larger than a quantum well bandgap. The first and second doped layers have different conductivities.

Abstract: Photovoltaic cells and methods for making photovoltaic cells are described. The methods include disposing an intermediate layer within the back contact at a thickness that does not negatively impact reflection or transmission of light through the solar cell. The intermediate layer prevents peeling of metal from the back contact during laser scribing.

Abstract: A surface emitting semiconductor laser includes a first semiconductor layer sequence, which comprises a pump laser. A second semiconductor layer sequence is arranged on the first semiconductor layer sequence and comprises a vertical emitter. The vertical emitter has a radiation-emitting active layer, a radiation exit side and a connecting side lying opposite the radiation exit side. The pump laser is arranged at the radiation exit side of the vertical emitter and a carrier body is arranged at the connecting side of the vertical emitter. Furthermore, a method for producing a surface emitting semiconductor laser is specified.

Abstract: A tunable terahertz resonator includes a semiconductor substrate and a metal layer contacting a surface of the semiconductor substrate. A depletion layer is formed in the semiconductor substrate near an interface between the metal layer and the semiconductor substrate. A chiral nanostructure is coupled to the substrate or the metal layer, the chiral nanostructure including a conducting or semiconducting material and having an inductance. A bias circuit applies a bias voltage across the metal layer and the semiconductor substrate to control a capacitance of a tunable capacitor that includes the depletion layer. The chiral nanostructure and the tunable capacitor form a tunable resonant circuit. The tunable terahertz resonator can be used in a terahertz radiation emitter or receiver.

Abstract: A method of electrically connecting an element to wiring includes the steps of forming a conductive fixing member precursor layer at least on wiring provided on a base; and arranging an element having a connecting portion on the wiring such that the connecting portion contacts the conductive fixing member precursor layer, and then heating the conductive fixing member precursor layer to form a conductive fixing member latter, thereby fixing the connecting portion of the element to the wiring, with the conductive fixing member layer therebetween, wherein the conductive fixing member precursor layer is composed of a solution-tape conductive material.

Abstract: Embodiments of an apparatus and methods for improving multi-gate device performance including methods to fabricate a plurality of multi-gate fins from a diffused body of a substantially planar structure that is substantially electrically isolated using a shallow trench region are generally described herein. Other embodiments may be described and claimed.

Abstract: A method for wafer-to-wafer bonding of a sensor readout circuitry separately fabricated with a silicon substrate to a photodiode device made of non-silicon materials grown from a separate substrate. In preferred embodiments the non-silicon materials are epitaxially grown on a silicon wafer. The bonding technique of preferred embodiments of the present invention utilizes lithographically pre-fabricated metallic interconnects to connect each of a number of pixel circuits on a readout circuit wafer to each of a corresponding number of pixel photodiodes on a photodiode wafer. The metallic interconnects are extremely small (with widths of about 2 to 4 microns) compared to prior art bump bonds with the solder balls of diameter typically larger than 20 microns. The present invention also provides alignment techniques to assure proper alignment of the interconnects during the bonding step.

Abstract: A thermopile-based thermal detector is provided by a thermocouple, formed from a single sheet of material, which is made dissimilar with a P-doped and an N-doped junction electrically isolated via a naturally forming depletion region. The thermopile P-N sheet is uniform and planar, addressing stress and manufacturing issues. The usual non-active area of a conventional thermopile is significantly reduced or eliminated, and thus the output signal per unit diaphragm area of the detector is substantially increased, without the typical reduction in the signal-to-noise ratio. Also, a significant reduction in size of the thermal detector area is provided without a reduction in signal or signal-to-noise ratio. In an aspect, a second layer of thermocouples is axially positioned over, and connected with, a first layer of thermocouples. Additional axially stacked thermopiles can be provided within the same fabrication process. Signal processing circuitry may be electrically interconnected with the thermocouple.

Abstract: The present disclosure presents a chemical vapor deposition reactor having improved chemical utilization and cost efficiency. The wafer susceptors of the present disclosure may be used in a stackable configuration for processing many wafers simultaneously. The reactors of the present disclosure may be reverse-flow depletion mode reactors, which tends to provide uniform film thickness and a high degree of chemical utilization.

Abstract: High frequency performance of (e.g., silicon) bipolar devices (40, 100, 100?) is improved by reducing the capacitive coupling (Cbc) between the extrinsic base contact (46) and the collector (44, 44?, 44?). A dielectric ledge (453, 453?) is created during fabrication to separate the extrinsic base contract (46) from the collector (44, 44?, 44?) periphery (441). The dielectric ledge (453, 453?) underlies the transition region (461) where the extrinsic base contact (46) is coupled to the intrinsic base. (472) During device fabrication, a multi layer dielectric stack (45) is formed adjacent the intrinsic base (472) that allows the simultaneous creation of an undercut region (457, 457?) in which the intrinsic base (472) to extrinsic base contact (46) transition region (461) can be formed.

Abstract: Provided is a method for producing a Group III nitride-based compound semiconductor light-emitting device, wherein a contact electrode is formed on an N-polar surface of an n-type layer through annealing at 350° C. or lower. In the case where, in a Group III nitride-based compound semiconductor device produced by the laser lift-off process, a contact electrode is formed, through annealing at 350° C. or lower, on a micro embossment surface (i.e., a processed N-polar surface) of an n-type layer from vanadium, chromium, tungsten, nickel, platinum, niobium, or iron, when a pseudo-silicon-heavily-doped layer is formed on the micro embossment surface (i.e., N-polar surface) of the n-type layer through treatment with a plasma of a silicon-containing compound gas, and treatment with a fluoride-ion-containing chemical is not carried out, ohmic contact is obtained, and low resistance is attained.

Abstract: A III-nitride structure comprising a light emitting layer disposed between an n-type region and a p-type region is grown on a silicon substrate. The III-nitride structure is attached to a host, then a portion of the silicon substrate is etched away to reveal a top surface of the III-nitride structure. In some embodiments, the silicon substrate is etched to form an enclosure on the top surface of the III-nitride structure. A wavelength converting material such as phosphor may be disposed in the enclosure.

Abstract: A method for manufacturing a semiconductor device, comprising: loading a wafer to be subjected to film formation to a chamber; supporting the wafer to be spaced from a film formation position of the wafer; preliminarily heating the wafer while rotating a rotating member for rotating the wafer through a supporting member during the film formation at a predetermined rotational speed under a state of the wafer to be spaced from the film formation position; placing the wafer on the supporting member in the film formation position; and heating the wafer at a predetermined temperature and supplying a process gas onto the wafer while rotating the wafer.

Abstract: A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.

Abstract: The invention relates to a semiconductor fuse structure comprising a substrate (1) having a surface, the substrate (1) having a field oxide region (3) at the surface, the fuse structure further comprising a fuse body (FB), the fuse body (FB) comprising polysilicon (PLY), the fuse body (FB) lying over the field oxide region (3) and extending into a current-flow direction (CF), wherein the fuse structure is programmable by means of leading a current through the fuse body (FB), wherein the fuse body (FB) has a tensile strain in the current-flow direction (CF) and a compressive strain in a direction (Z) perpendicular to said surface of the substrate (1). The invention further relates to methods of manufacturing such a semiconductor fuse.

Abstract: This invention discloses a high-efficiency solar cell structure which enables high throughput manufacturing process thereof. The solar cell is accomplished by forming a plurality of first emitter regions in a front surface of a substrate, a plurality of second emitter regions in the front surface, and a plurality of fingers. Each of the fingers is formed over a least a portion of the second emitter region and a portion of the first emitter region. The first emitter regions and the second emitter regions have a depth not less than 0.2 ?m.

Abstract: Provided is a semiconductor laser including: a substrate (semiconductor substrate); an optical waveguide (active layer waveguide) with a mesa structure that includes an active layer (strain-compensated multiple quantum well active layer) including Al, is provided over the semiconductor substrate; a semiconductor protective layer that is provided so as to cover the top and the side of a mesa of the active layer waveguide; a current block layer that is provided so as to embed the active layer waveguide and the semiconductor protective layer; and a clad layer (p-type InP clad layer) that is provided over the semiconductor protective layer and the current block layer, wherein, the semiconductor protective layer has a semiconductor layer (p-type InGaAsP protective layer) that includes As, but does not include Al.

Abstract: An exemplary embodiment includes a semiconductor device. The semiconductor device can include a channel including one or more compounds of the formula AxBxOx, wherein each A is selected from the group of Cu, Ag, Sb, each B is selected from the group of Cu, Ag, Sb, Zn, Cd, Ga, In, Ge, Sn, and Pb, each O is atomic oxygen, each x is independently a non-zero integer, and each of A and B are different.

Abstract: There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point.

Abstract: Transistor devices are formed with nickel silicide layers formulated to prevent degradation upon removal of overlying stress liners. Embodiments include transistors with nickel silicide layers having a platinum composition gradient increasing in platinum content toward the upper surfaces thereof, i.e., increasing in platinum in a direction away from the gate electrode and source/drain regions. Embodiments include forming a first layer of nickel having a first amount of platinum and forming, on the first layer of nickel, a second layer of nickel having a second amount of platinum, the second weight percent of platinum being greater than the first weight percent. The layers of nickel are then annealed to form a nickel silicide layer having the platinum composition gradient increasing in platinum toward the upper surface.

Abstract: A method and semiconductor device for forming a uniformly thin dielectric layer on graphene. A metal or semiconductor layer is deposited on graphene which is located on the surface of a dielectric layer or on the surface of a substrate. The metal or semiconductor layer may act as a nucleation layer for graphene. The metal or semiconductor layer may be subjected to an oxidation process. A thin dielectric layer may then be formed on the graphene layer after the metal or semiconductor layer is oxidized. As a result of synthesizing a metal-oxide layer on graphene, which acts as a nucleation layer for the gate dielectric and buffer to graphene, a uniformly thin dielectric layer may be established on graphene without affecting the underlying characteristics of graphene.

Abstract: The invention relates to the design and processing of a semiconductor optical device. The device is formed of at least four layers of III-V compounds in which one consists of the penternary AlGaInAsSb material. The structure is wet etched in order to form optical ridge waveguides. One such device has incorporated two waveguides which are connected through a new junction design which can be made by wet etching. In one design the junction and waveguides consists of wet etched AlO.90GaO.10AsSb cladding around a core of AlO.28GaO.72AsSb in which an active layer composed of AlO.22InO.22GaO.55AsSb/InO.29GaO.71AsSb quantum wells is embedded. The resulting device is a erdge junction laser which has single mode emission and emits a narrow line width. We made and tested a device in the 2.34 müm to 2.375 müm wavelength area and found it to have an emission line width of around 0.5 nm.

Abstract: A semiconductor wafer structure for integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate; an electrically conductive layer formed on the lower insulating layer; an upper insulating layer formed on the electrically conductive layer, the upper insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; and a semiconductor layer formed on the upper insulating layer.

Abstract: A semiconductor wafer structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer, the electrically conductive layer further having one or more shallow trench isolation (STI) regions formed therein; an etch stop layer formed on the electrically conductive layer and the one or more STI regions; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A subsequent active area level STI scheme, in conjunction with front gate formation over the semiconductor layer, is also disclosed.

Abstract: Provided is a method of forming quantum dots, including: forming a buffer layer on an InP substrate so as to be lattice-matched with the InP substrate; and sequentially alternately depositing In(Ga)As layers and InAl(Ga)As or In(Ga, Al, As)P layers that are greatly lattice-mismatched with each other on the buffer layer so as to form In(Ga, Al)As or In(Ga, Al, P)As quantum dots.

Abstract: A nitride semiconductor device according to the present invention includes: a nitride semiconductor laminated structure comprising a first layer made of a Group III nitride semiconductor, a second layer laminated on the first layer and made of an Al-containing Group III nitride semiconductor with a composition that differs from that of the first layer, the nitride semiconductor laminated structure comprising a stripe-like trench exposing a lamination boundary between the first layer and the second layer; a gate electrode formed to oppose the lamination boundary; and a source electrode and a drain electrode, having the gate electrode interposed therebetween, each connected electrically to the second layer.

Abstract: A method for forming a photovoltaic cell is disclosed which comprises the steps of providing a semiconductor donor body having a first surface and a second surface opposite the first surface, cleaving a first portion from the first surface of the semiconductor donor body to form a first lamina of semiconductor material, wherein the first lamina of semiconductor material has a first lamina thickness, and cleaving a second portion from the second surface of the semiconductor donor body to form a second lamina of semiconductor material, wherein the second lamina of semiconductor material has a second lamina thickness.

Abstract: In one aspect, a method includes fabricating a gallium nitride (GaN) layer with a first diamond layer having a first thermal conductivity and a second diamond layer having a second thermal conductivity greater than the first thermal conductivity. The fabricating includes using a microwave plasma chemical vapor deposition (CVD) process to deposit the second diamond layer onto the first diamond layer.

Abstract: In one aspect, a method includes fabricating a device. The device includes a gallium nitride (GaN) layer, a diamond layer disposed on the GaN layer and a gate structure disposed in contact with the GaN layer and the diamond layer. In another aspect, a device includes a gallium nitride (GaN) layer, a diamond layer disposed on the GaN layer and a gate structure disposed in contact with the GaN layer and the diamond layer.

Abstract: A MEMS microbalance that includes a substrate made of semiconductor material with a cavity, and a resonator, which is suspended above the cavity of the substrate and is formed by a mobile body, by at least one first arm connected between the substrate and the mobile body, which has a first thickness and which enables oscillations of the mobile body with respect to the substrate, by an actuation transducer connected to the mobile body for generating the oscillations at a resonance frequency, and by a detection transducer for detecting a variation of the resonance frequency, wherein the mobile body possesses at least one thin portion having a second thickness smaller than the first thickness of the first arm.

Abstract: Nanotube and graphene transducers are disclosed. A transducer according to the present invention can include a substrate, a plurality of semiconductive structures, one or more metal pads, and a circuit. The semiconductive structures can be nanotubes or graphene located entirely on a surface of the substrate, such that each of the semiconductive structures is supported along its entire length by the substrate. An electrical property of the semiconductive structures can change when a force is applied to the substrate. The metal pads can secure at least one of the semiconductive structures to the substrate. The circuit can be coupled to at least some of the semiconductive structures to provide an output responsive to the change in the electrical property of the semiconductive structures, so as to indicate the applied force.

Abstract: A high luminance semiconductor light emitting device and a fabrication method for such semiconductor light emitting device are provided by forming a metallic reflecting layer using a non-transparent semiconductor substrate.

Abstract: A method for manufacturing a display device using light emitting diode chips contemplates manufacturing a plurality of light emitting diode (LED) chips using a porous template; forming a plurality of first electrodes on a substrate; attaching the LED chips to pixel sites on the first electrodes using fluidic self assembly (FSA); and forming a plurality of second electrodes on a top surface of the LED chips.

Abstract: Metal-oxide-semiconductor transistors are provided. A metal-oxide-semiconductor transistor may be formed on a semiconductor substrate. Source and drain regions may be formed in the substrate. A gate insulator such as a high-K dielectric may be formed between the source and drain regions. A gate may be formed from multiple gate conductors. The gate conductors may be metals with different workfunctions. A first of the gate conductors may form a pair of edge gate conductors that are adjacent to dielectric spacers. An opening between the edge gate conductors may be filled with the second gate conductor to form a center gate conductor. A self-aligned gate formation process may be used in fabricating the metal-oxide-semiconductor transistor.

Abstract: The present invention includes a vertical-cavity surface-emitting semiconductor laser diode having a resonator with a first distributed Bragg reflector, an active zone which has a p-n junction and is embedded into a semiconductor layer sequence, and a second distributed Bragg reflector. The semiconductor laser diode has an emission wavelength ?, wherein a periodic structure is arranged within the resonator as an optical grating made of semiconductive material and dielectric material, the main plane of extension of which is arranged substantially perpendicularly to the direction of emission of the semiconductor laser diode. The periodic structure is in direct contact with at least one of the semiconductor layers embedding the active zone and with at least one of the two distributed Bragg reflectors.