Abstract: A semiconductor device in accordance with the present invention includes a diode 7 that is formed on a semiconductor substrate and serves as a temperature detection element to detect abnormal heat generation, and a thermal conduction layer 102 that is formed between the diode 7 and the semiconductor substrate and has a thermal conductivity higher than that of the semiconductor substrate. In this way, heat generated in a heat generating portion can be swiftly and uniformly conducted over the entire temperature detection element composed of the diode 7 with efficiency. In this way, a semiconductor device capable of detecting temperature with excellent response by the temperature detection element and its manufacturing method can be provided.

Abstract: Certain embodiments disclosed herein relate to the formation of multi-component oxide heterostructures (MCOH) using surface nucleation to pattern the atomic layer deposition (ALD) of perovskite material followed by patterned etch and metallization to produce ultra-high density MCOH nano-electronic devices. Applications include ultra-high density MCOH memory and logic, as well as electronic functionality based on single electrons, for example a novel flash memory cell Floating-Gate (FG) transistor with LaAlO3 as a gate tunneling dielectric. Other types of memory devices (DIMMS, DRAM, and DDR) made with patterned ALD of LaAlO3 as a gate dielectric are also possible.

Abstract: A thermo-electric semiconductor device is provided. The thermo-electric semiconductor device includes: a first electrode layer; a spacer layer formed on the first electrode layer and having a plurality of pillars with a uniform height, the plurality of pillars thermally grown and protruded on a surface of the spacer layer; and a second electrode layer formed over the spacer layer in such a manner as to contact tops of the protruded pillars.

Abstract: A thermoelectric conversion module is formed by bonding a P-type thermoelectric conversion material and an N-type thermoelectric conversion material together with an insulating material including spherical ceramic grains having an index of grain size dispersion, 3CV, of about 20% or less interposed therebetween. The P-type thermoelectric conversion material and the N-type thermoelectric conversion material are electrically connected to each other in a region other than a region in which the P-type thermoelectric conversion material and the N-type thermoelectric conversion material are bonded together with the insulating material interposed therebetween. The spherical ceramic grains have an average grain size of about 0.05 mm to about 0.6 mm, and the insulating material is an insulating glass material.

Abstract: An apparatus including a resonator electrode and a second electrode separated from the resonator electrode by a gap having a size that facilitates electron transfer across the gap, wherein the resonator electrode is a resonator electrode mounted for oscillatory motion relative to the second electrode that results in a size of the gap between the resonator electrode and the second electrode being time variable; a feedback circuit configured to convey an electron transfer signal dependent upon electron transfer across the gap as a feedback signal; and a drive electrode adjacent the resonator electrode configured to receive a feedback signal from a feedback circuit configured to provide a time-varying feedback signal dependent upon electron transfer across a gap.

Abstract: To provide a semiconductor device capable of write operation to a selected magnetoresistive element without causing a malfunction of a non-selected magnetoresistive element and a manufacturing method of this semiconductor device. The semiconductor device includes a magnetic storage element having a magnetization free layer whose magnetization direction is made variable and formed over a lead interconnect and a digit line located below the magnetic storage element, extending in a first direction, and capable of changing the magnetization state of the magnetization free layer by the magnetic field generated. The digit line includes an interconnect body portion and a cladding layer covering therewith the bottom surface and the side surface of the interconnect body portion and opened upward. The cladding layer includes a sidewall portion covering therewith the side surface of the interconnect body portion and a bottom wall portion covering therewith the bottom surface of the interconnect body portion.

Abstract: A method for detaching a first material layer from a second material layer includes following steps. Firstly, a high-magnetic-permeability material layer is formed on a first material layer. Secondly, a second material layer is formed on the high-magnetic-permeability material layer. Thirdly, the first and second material layers are cooled such that the first and second material layers shrink, wherein the first and second material layers are low-magnetic-permeability materials. Finally, the high-magnetic-permeability material layer is heated by applying a high-frequency radiofrequency electromagnetic wave thereto such that the high-magnetic-permeability material layer expands, thus detaching the first material layer from the second material layer.

Abstract: Provided are a semiconductor Field-Effect Transistor (FET) sensor and a method of fabricating the same. The method includes providing a semiconductor substrate, forming a sensor structure having a fin-shaped structure on the semiconductor substrate, injecting ions for electrical ohmic contact into the sensor structure, and depositing a metal electrode on the sensor structure, immobilizing a sensing material to be specifically combined with a target material onto both sidewall surfaces of the fin-shaped structure, and forming a passage on the sensor structure such that the target material passes through the fin-shaped structure.

Abstract: This application discloses a method of manufacturing a photoelectronic device comprising steps of providing a semiconductor stack layer, forming at least one metal adhesive on the semiconductor stack layer by a printing technology, forming an electrode by heating the metal adhesive to remove the solvent in the metal adhesive, wherein an ohmic contact is formed between the electrode and the semiconductor stack layer.

Abstract: A process of making a photovoltaic unit includes steps of simultaneously forming a first layer of n-type material and a second layer of p-type material using a continuous casting process, and continuously bonding the first and second layers to form a p-n junction. The process may be performed using a twin-roll type continuous casting system having a continuous casting mold that includes a first mold compartment for receiving molten n-type material and a second mold compartment for receiving molten p-type material. The molten n-type material and the molten p-type material are gradually solidified into semi-solid shells and are pressed together by opposed casting rolls, creating a metallurgical bond between the n-type material and the p-type material that forms an effective p-n junction. The process permits the large scale efficient manufacturing of photovoltaic units.

Abstract: A phase change material including a high adhesion phase change material formed on a dielectric material and a low adhesion phase change material formed on the high adhesion phase change material. The high adhesion phase change material includes a greater amount of at least one of nitrogen and oxygen than the low adhesion phase change material. The phase change material is produced by forming a first chalcogenide compound material including an amount of at least one of nitrogen and oxygen on the dielectric material and forming a second chalcogenide compound including a lower percentage of at least one of nitrogen and oxygen on the first chalcogenide compound material. A phase change random access memory device, and a semiconductor structure are also disclosed.

Abstract: Expungement ions, preferably including hydrogen ions, are implanted into a face of a first, preferably silicon, substrate such that there will be a maximum concentration of the expungement ions at a predetermined depth from the face. Subsequently a monocrystalline Group II-VI semiconductor layer, or two or more such layers, is/are grown on the face, as by means of molecular beam epitaxy. After this a second, preselected substrate is attached to an upper face of the Group II-VI layer(s). Next, the implanted expungement ions are used to expunge most of the first substrate from a remnant thereof, from the grown II-VI layer, and from the second substrate.

Abstract: There is provided a process for forming a contained second layer over a first layer, including the steps: forming the first layer having a first surface energy; treating the first layer with a priming layer; exposing the priming layer patternwise with radiation resulting in exposed areas and unexposed areas; developing the priming layer to effectively remove the priming layer from either the exposed areas or the unexposed areas resulting in a first layer having a pattern of priming layer, wherein the pattern of priming layer has a second surface energy that is higher than the first surface energy; and forming the second layer by liquid depositions on the pattern of priming layer on the first layer. There is also provided an organic electronic device made by the process.

Abstract: A method for applying at least one layer, selected from diffusion barriers, further protective layers, adhesion promoters, solders and electrical contacts, onto thermoelectric materials, is characterized by the fact that the at least one layer is rolled or pressed onto the thermoelectric material at a temperature at which the thermoelectric material is flowable.

Abstract: A process of making a photovoltaic unit includes steps of simultaneously forming a first layer of n-type material and a second layer of p-type material using a continuous casting process, and continuously bonding the first and second layers to form a p-n junction. The process may be performed using a twin-roll type continuous casting system having a continuous casting mold that includes a first mold compartment for receiving molten n-type material and a second mold compartment for receiving molten p-type material. The molten n-type material and the molten p-type material are gradually solidified into semi-solid shells and are pressed together by opposed casting rolls, creating a metallurgical bond between the n-type material and the p-type material that forms an effective p-n junction. The process permits the large scale efficient manufacturing of photovoltaic units.

Abstract: A semiconductor device 19-1 includes a source electrode 3s and a drain electrode 3d disposed on a substrate 1, an insulating partition wall 5, which has a first opening 5a reaching end portions of the source electrode 3s and the drain electrode 3d and between these electrodes 3s-3d and which is disposed on the substrate 1, a channel portion semiconductor layer 7a, which is composed of a semiconductor layer 7 formed from above the partition wall 5 and which is disposed on the bottom portion of the first opening 5a while being separated from the semiconductor 7 on the partition wall 5, a gate insulating film 9 formed all over the surface from above the semiconductor layer 7 including the channel portion semiconductor layer 7a, and a gate electrode 11a disposed on the gate insulating film 9 while overlapping the channel portion semiconductor layer 7a.

Abstract: A method for manufacturing a photoelectric conversion device typified by a solar cell, having an excellent photoelectric conversion characteristic with a silicon semiconductor material effectively utilized. The point is that the surface of a single crystal semiconductor layer bonded to a supporting substrate is irradiated with a pulsed laser beam to become rough. The single crystal semiconductor layer is irradiated with the pulsed laser beam in an atmosphere containing an inert gas and oxygen so that the surface thereof is made rough. With the roughness of surface of the single crystal semiconductor layer, light reflection is suppressed so that incident light can be trapped. Accordingly, even when the thickness of the single crystal semiconductor layer is equal to or greater than 0.1 ?m and equal to or less than 10 ?m, path length of incident light is substantially increased so that the amount of light absorption can be increased.

Abstract: A trench Schottky diode and its manufacturing method are provided. The trench Schottky diode includes a semiconductor substrate having therein a plurality of trenches, a gate oxide layer, a polysilicon structure, a guard ring and an electrode. At first, the trenches are formed in the semiconductor substrate by an etching step. Then, the gate oxide layer and the polysilicon structure are formed in the trenches and protrude above a surface of the semiconductor substrate. The guard ring is formed to cover a portion of the resultant structure. At last, the electrode is formed above the guard ring and the other portion not covered by the guard ring. The protruding gate oxide layer and the protruding polysilicon structure can avoid cracks occurring in the trench structure.

Abstract: A high quality Group III-Nitride semiconductor crystal with ultra-low dislocation density is grown epitaxially on a substrate via a particle film with multiple vertically-arranged layers of spheres with innumerable micro- and/or nano-voids formed among the spheres. The spheres can be composed of a variety of materials, and in particular silica or silicon dioxide (SiO2).

Abstract: A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of substrate. Deep trenches are provided for isolation between multi-channel VTVS. Trench gates are also provided for increasing the capacitance of VTVS with integrated EMI filter.

Abstract: A substrate processing system includes a first load lock, a process chamber having a first opening to allow an exchange of a substrate between the first load lock and the first process chamber, first rollers in the process chamber; and second rollers in the first load lock, wherein the first rollers and the second rollers are configured to transport a substrate thereon through the first opening between the first load lock and the process chamber. At least some of the first rollers and the second rollers are idler rollers.

Abstract: Optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit an array of conductive regions; and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a method of forming a nanocrystalline film includes fabricating a plurality of nanocrystals having a plurality of first ligands attached to their outer surfaces; exchanging the first ligands for second ligands of different chemical composition than the first ligands; forming a film of the ligand-exchanged nanocrystals; removing the second ligands; and fusing the cores of adjacent nanocrystals in the film to form an electrical network of fused nanocrystals.

Abstract: The present invention provides a method of manufacturing a semiconductor substrate that includes a substrate, a first semiconductor layer arranged on the substrate, a metallic material layer arranged on the first semiconductor layer, a second semiconductor layer arranged on the first semiconductor layer and the metallic material layer, and a cavity formed in the first semiconductor layer under the metallic material layer.

Abstract: A phase change memory device having buried conduction lines directly underneath phase change memory cells is presented. The phase change memory device includes buried conduction lines buried in a semiconductor substrate and phase change memory cells arranged on top of the buried conductive lines. By having the buried conduction lines directly underneath the phase change memory cells, the resultant device can realize a considerable reduction in size.

Abstract: Homogeneity and stability of electric characteristics of a thin film transistor included in a circuit are critical for the performance of a display device including said circuit. An object of the invention is to provide an oxide semiconductor film with low hydrogen content and which is used in an inverted staggered thin film transistor having well defined electric characteristics. In order to achieve the object, a gate insulating film, an oxide semiconductor layer, and a channel protective film are successively formed with a sputtering method without being exposed to air. The oxide semiconductor layer is formed so as to limit hydrogen contamination, in an atmosphere including a proportion of oxygen. In addition, layers provided over and under a channel formation region of the oxide semiconductor layer are formed using compounds of silicon, oxygen and/or nitrogen.

Abstract: A photovoltaic device includes a first heterojunction layer having a first donor type organic material and a first acceptor type organic material, in which a concentration of at least one of the first donor type organic material and the first acceptor type organic material is graded continuously from a first side of the first heterojunction layer to a second side of the first heterojunction layer.

Abstract: A technique for creating high quality Schottky barrier devices in doped (e.g., Li+) crystalline metal oxide (e.g., ZnO) comprises field-controlled diffusion of mobile dopant atoms within the metal oxide crystal lattice. When heated (e.g., above 550 K) in the presence of an electric field (e.g., bias to ground of +/?50 V) the dopant atoms are caused to collect to form an ohmic contact, leaving a depletion region. The size of the depletion region controls the thickness of the Schottky barrier. Metal-semiconductor junction devices such as diodes, photo-diodes, photo-detectors, MESFETs, etc. may thereby be fabricated.

Abstract: A method for producing a spatially patterned structure includes forming a layer of a material on at least a portion of a substructure of the spatially patterned structure, forming a barrier layer of a fluorinated material on the layer of material to provide an intermediate structure, and exposing the intermediate structure to at least one of a second material or radiation to cause at least one of a chemical change or a structural change to at least a portion of the intermediate structure. The barrier layer substantially protects the layer of the material from chemical and structural changes during the exposing. Substructures are produced according to this method.

Abstract: A phase change memory device comprises a photolithographically formed phase change memory cell having first and second electrodes and a phase change element positioned between and electrically coupling the opposed contact elements of the electrodes to one another. The phase change element has a width, a length and a thickness. The length, the thickness and the width are less than a minimum photolithographic feature size of the process used to form the phase change memory cell. The size of the photoresist masks used in forming the memory cell may be reduced so that the length and the width of the phase change element are each less than the minimum photolithographic feature size.

Abstract: Embodiments of an apparatus and methods for improving multi-gate device performance including methods to fabricate a plurality of multi-gate fins from a diffused body of a substantially planar structure that is substantially electrically isolated using a shallow trench region are generally described herein. Other embodiments may be described and claimed.

Abstract: Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more p-type wells in the semiconductor substrate, multiple p-channel transistors disposed at least partially in one or more n-type wells in the semiconductor substrate, and a backgate control circuit. The backgate control circuit is electrically coupled to the p-type well(s) and to the n-type well(s) to facilitate transitioning of the multiple n-channel transistors and the multiple p-channel transistors from backgate biased standby mode to active mode by automatically shunting charge from the n-type well(s) to the p-type well(s) until a well voltage threshold is reached indicative of a completed transition of the transistors from backgate biased standby mode to active mode.

Abstract: A liquid crystal display apparatus (10) includes a first substrate (20) including a base layer (71) and a display element layer formed on the base layer (71). The base layer (71) of the first substrate (20) is constituted by a transparent and colorless resin film formed by vapor deposition at room temperature.

Abstract: A phase change device includes a native oxide grown on the surface of a first phase change alloy layer. The native oxide is punched through during the first electrical pulse applied between the device electrodes. An aperture created in the native oxide limit a region of localized heating during the device programming. A method for the phase change device fabrication includes a native oxide formation.

Abstract: A lateral passive device is disclosed including a dual annular electrode. The annular electrodes form an anode and a cathode. The annular electrodes allow anode and cathode series resistances to be optimized to the lowest values at a fixed device area. In addition, the parasitic capacitance to a bottom plate (substrate) is greatly reduced. In one embodiment, a device includes a first annular electrode surrounding a second annular electrode formed on a substrate, and the second annular electrode surrounds an insulator region. A related method is also disclosed.

Abstract: A bulk heterojunction comprising an intermixed blend of fully inorganic n- and p-type particles and its method of manufacture are described. The particles are preferably nanometer-scale, spherical-shaped particles known as nanocrystals which are assembled into a densely packed three-dimensional array. The nanocrystals are preferably fabricated from a photo-active material which, in combination with the nanocrystal shape and size, can be engineered to produce a bulk heterojunction with a specific absorption spectrum. The bulk heterojunction is preferably formed by dispersing a predetermined ratio of the desired n- and p-type nanocrystals in an organic solvent and employing low-cost solution processing techniques to deposit a film having the desired thickness, relative concentration of nanocrystal types, and degree of intermixing onto a substrate.

Abstract: The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The substrate is etched to form a plurality of trenches and cross-trenches which define a plurality of pillars. After the etching, dopant is implanted within the trenches to form a source/drain region that extends less than an entirety of the trench width. The invention includes a semiconductor construction having a bit line disposed within a semiconductor substrate below a first elevation. A wordline extends elevationally upward from the first elevation and substantially orthogonal relative to the bit line. A vertical transistor structure is associated with the wordline. The transistor structure has a channel region laterally surrounded by a gate layer and is horizontally offset relative to the bit line.

Abstract: In a process of fabricating a nitride nitride semi-conductor layer of AlaGabIn(1-a-b)N (0<a<1, 0<b<1, 1?a?b>0), the AlGaInN layer is grown at a growth rate less than 0.09 ?m/h according to the metal organic vapor phase epitaxy (MOPVE) method. The AlGaInN layer fabricated by the process in the present invention exhibits a high quality with low defect, and increases internal quantum yield.

Abstract: A power semiconductor component and a method for producing such a component. The component comprises a semiconductor base body having a first doping. A pn junction is formed in the base body by a contact region having a second doping with a first doping profile. A field ring structure has a second doping with a second doping profile. The contact region and the field ring structure are arranged at respectively assigned first and second partial areas of a first surface of the base body. Both extend into the base body, wherein the base body has, for the field ring structure, a trench-type cutout assigned to each respective field ring, the surface of said cutout following the contour of the assigned doping profile.

Abstract: A detector for electromagnetic radiation such as millimeter wave and infrared employs a ring-shaped ferroelectric element having a temperature affected by an absorber for the radiation. The dielectric constant of the ferroelectric material is a strong function of the temperature near its Curie temperature. The resonant frequency of the ferroelectric element is detected by applying a swept-frequency signal to the circuit and detecting the frequency which enhances the energy of the pulse. A two-dimensional camera for the radiation employs a two-dimensional array of these ferroelectric resonant circuits and a system for rapidly interrogating their resonant frequencies on a sequential basis.

Abstract: Disclosed embodiments provide a solution-based process for producing useful materials, such as semiconductor materials. One disclosed embodiment comprises providing at least a first reactant and a second reactant in solution and applying the solution to a substrate. The as-deposited material is thermally annealed to form desired compounds. Thermal annealing may be conducted under vacuum; under an inert atmosphere; or under a reducing environment. The method may involve using metal and chalcogen precursor compounds. One example of a metal precursor compound is a metal halide. Examples of suitable chalcogen precursor compounds include a chalcogen powder, a chalcogen halide, a chalcogen oxide, a chalcogen urea, a chalcogen or dichalcogen comprising organic ligands, or combinations thereof. Certain disclosed embodiments concern a method for making a solar cell from I-III-VI semiconductors.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming a channel region on a substrate, wherein the channel region comprises at least one CNT, forming at least one source/drain region adjacent the channel region, and then forming a gate electrode on the channel region, wherein a width of the gate electrode comprises about 50 percent to about 90 percent of a width of the contact region.

Abstract: A semiconductor includes an N-type impurity region provided in a substrate. A P-type RESURF layer is provided at a top face of the substrate in the N-type impurity region. A P-well has an impurity concentration higher than that of the P-type RESURF layer, and makes contact with the P-type RESURF layer at the top face of the substrate in the N-type impurity region. A first high-voltage-side plate is electrically connected to the N-type impurity region, and a low-voltage-side plate is electrically connected to a P-type impurity region. A lower field plate is capable of generating a lower capacitive coupling with the substrate. An upper field plate is located at a position farther from the substrate than the lower field plate, and is capable of generating an upper capacitive coupling with the lower field plate whose capacitance is greater than the capacitance of the lower capacitive coupling.

Abstract: Materials, methods, structures and device including the same can provide a semiconductor device such as an LED using an active region corresponding to a non-polar face or surface of III-V semiconductor crystalline material. In some embodiments, an active diode region contains more non-polar III-V material oriented to a non-polar plane than III-V material oriented to a polar plane. In other embodiments, a bottom region contains more non-polar m-plane or a-plane surface area GaN than polar c-plane surface area GaN facing an active region.

Abstract: A board on which a wiring having an electrode pad is formed is prepared. A resist film is formed on the board in order to cover the wiring and then the resist film is left on the electrode pad through patterning. An inorganic insulating film is formed on the board in order to cover the wiring and then the resist film is removed, thereby removing the inorganic insulating film provided on the resist film to leave the inorganic insulating film between the wirings. A solder resist layer is formed on the board in order to cover the wiring and then the electrode pad is exposed.

Abstract: The present application provides a semiconductor Fabry-Perot dual mode lasing device having terahertz characteristics resulting in significant advantages over the prior art including for example operation at room temperatures and the absence of re-growth processing requirements.

Abstract: A method for forming a MTJ in a STT-MRAM is disclosed in which the easy-axis CD is determined independently of the hard-axis CD. One approach involves two photolithography steps each followed by two plasma etch steps to form a post in a hard mask which is transferred through a MTJ stack of layers. The hard mask has an upper Ta layer with a thickness of 300 to 400 Angstroms and a lower NiCr layer less than 50 Angstroms thick. The upper Ta layer is etched with a fluorocarbon etch while lower NiCr layer and underlying MTJ layers are etched with a CH3OH. Preferably, a photoresist mask layer is removed by oxygen plasma between the fluorocarbon and CH3OH plasma etches. A lower hard mask layer made of NiCr or the like is inserted to prevent formation and buildup of Ta etch residues that can cause device shunting.

Abstract: A method for fabricating a semiconductor memory device. An interlayer dielectric layer is formed over a semiconductor substrate including a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) as a cell transistor and a plurality of contact plugs in contact with source and drain regions of the cell transistor. A plurality of openings exposing one of the contact plugs is formed by removing a portion of the interlayer dielectric layer. A fixed magnetization layer, a tunnel barrier layer, and a free magnetization layer are sequentially stacked over the interlayer dielectric layer including the openings. A magnetic tunnel junction element is formed by planarizing the interlayer dielectric layer until a surface of the interlayer dielectric layer is exposed. The magnetic tunnel junction element includes the fixed magnetization layer, the tunnel barrier layer, and the free magnetization layer that fill each of the openings.

Abstract: An electrochemical transistor device is provided, comprising a source contact, a drain contact, at least one gate electrode, an electrochemically active element arranged between, and in direct electrical contact with, the source and drain contacts, which electrochemically active element comprises a transistor channel and is of a material comprising an organic material having the ability of electrochemically altering its conductivity through change of redox state thereof, and a solidified electrolyte in direct electrical contact with the electrochemically active element and said at least one gate electrode and interposed between them in such a way that electron flow between the electrochemically active element and said gate electrode(s) is prevented. In the device, flow of electrons between source contact and drain contact is controllable by means of a voltage applied to said gate electrode(s).

Abstract: A superjunction device that includes a termination region having a transition region adjacent the active region thereof, the transition region including a plurality of spaced columns.

Abstract: The present invention provides a liquid crystal display device having a large holding capacitance in the inside of a pixel. A liquid crystal display device includes a first substrate, a second substrate arranged to face the first substrate in an opposed manner, and liquid crystal sandwiched between the first substrate and the second substrate. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode thereof connected to the video signal line and a second electrode thereof connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film formed above the first silicon nitride film, a capacitance electrode formed above the organic insulation film, and a second silicon nitride film formed above the capacitance electrode and below the pixel electrode. The second silicon nitride film is a film which is formed at a temperature lower than a forming temperature of the first silicon nitride film.