Abstract: A liquid crystal display (LCD) array substrate and its manufacturing method are provided. Scan lines and data lines of the LCD array substrate are composed of two conductive layers to decrease their RC delay. Moreover, the dielectric layer and even the planarization layer are removed from pixel areas defined by the scan lines and the data lines to increase the light penetration percentage.

Abstract: A method for fabricating a thin film transistor (TFT) is provided. A substrate having a gate, a dielectric layer, a channel layer and an ohmic contact layer formed thereon is provided. Next, a metal layer is formed over the substrate covering the ohmic contact layer. Next, the metal layer and the ohmic contact layer are simultaneously etched by a wet etching process to form a source/drain and expose the channel layer. Because the wet etching process can be used to selectively etch the ohmic contact layer, damage to the underlying channel layer may be negligible. Thus, the reliability of the device may be promoted. Furthermore, the process may be simplified, the production yield and the throughput of TFT may be increased.

Abstract: A solar cell includes a substrate, a protective layer located over a first surface of the substrate, a first electrode located over a second surface of the substrate, at least one p-type semiconductor absorber layer located over the first electrode, an n-type semiconductor layer located over the p-type semiconductor absorber layer, and a second electrode over the n-type semiconductor layer. The p-type semiconductor absorber layer includes a copper indium selenide (CIS) based alloy material, and the second electrode is transparent and electrically conductive. The protective layer has an emissivity greater than 0.25 at a wavelength of 2 ?m, has a reactivity with a selenium-containing gas lower than that of the substrate, and may differ from the first electrode in at least one of composition, thickness, density, emissivity, conductivity or stress state. The emissivity profile of the protective layer may be uniform or non-uniform.

Abstract: A method for producing a metal oxide structure, including: forming a layer containing metal acetate hydrate on a sapphire substrate; subjecting the layer containing the metal acetate hydrate to an insolubilization treatment; and immersing the sapphire substrate having the insolubilized layer in a reaction solution containing a metal ion and an NH4+ ion, so as to grow rod-shaped crystals each containing metal oxide as a main substance thereof.

Abstract: A solar cell includes a substrate, a protective layer located over a first surface of the substrate, a first electrode located over a second surface of the substrate, at least one p-type semiconductor absorber layer located over the first electrode, an n-type semiconductor layer located over the p-type semiconductor absorber layer, and a second electrode over the n-type semiconductor layer. The p-type semiconductor absorber layer includes a copper indium selenide (CIS) based alloy material, and the second electrode is transparent and electrically conductive. The protective layer has an emissivity greater than 0.25 at a wavelength of 2 ?m, has a reactivity with a selenium-containing gas lower than that of the substrate, and may differ from the first electrode in at least one of composition, thickness, density, emissivity, conductivity or stress state. The emissivity profile of the protective layer may be uniform or non-uniform.

Abstract: The invention provides a quantum well active region for an optoelectronic device. The quantum well active region includes barrier layers of high bandgap material. A quantum well of low bandgap material is between the barrier layers. Three-dimensional high bandgap barriers are in the quantum well. A preferred semiconductor laser of the invention includes a quantum well active region of the invention. Cladding layers are around the quantum well active region, as well as a waveguide structure.

Abstract: A graphene layer is formed on a surface of a silicon carbide substrate. A dummy gate structure is formed over the fin, in the trench, or on a portion of the planar graphene layer to implant dopants into source and drain regions. The dummy gate structure is thereafter removed to provide an opening over the channel of the transistor. Threshold voltage adjustment implantation may be performed to form a threshold voltage implant region directly beneath the channel, which comprises the graphene layer. A gate dielectric is deposited over a channel portion of the graphene layer. After an optional spacer formation, a gate conductor is formed by deposition and planarization. The resulting graphene-based field effect transistor has a high carrier mobility due to the graphene layer in the channel, low contact resistance to the source and drain region, and optimized threshold voltage and leakage due to the threshold voltage implant region.

Abstract: Method of producing a partly or completely semi-insulating or p-type doped ZnO substrate from an n-type doped ZnO substrate, in which the n-type doped ZnO substrate is brought into contact with an anhydrous molten salt chosen from anhydrous molten sodium nitrate, lithium nitrate, potassium nitrate and rubidium nitrate. Partly or completely semi-insulating or p-type doped ZnO substrate, said substrate being in particular in the form of a thin layer, film or in the form of nanowires ; and said substrate being doped at the same time by an element chosen from Na, Li, K and Rb; by N; and by O; it being furthermore possible for ZnO or GaN to be epitaxially grown on this substrate. Electronic, optoelectronic or electro-optic device such as a light-emitting diode (LED) comprising this substrate.

Abstract: There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point.

Abstract: It is an object to reduce characteristic variation among transistors and reduce contact resistance between an oxide semiconductor layer and a source electrode layer and a drain electrode layer, in a transistor where the oxide semiconductor layer is used as a channel layer. In a transistor where an oxide semiconductor is used as a channel layer, at least an amorphous structure is included in a region of an oxide semiconductor layer between a source electrode layer and a drain electrode layer, where a channel is to be formed, and a crystal structure is included in a region of the oxide semiconductor layer which is electrically connected to an external portion such as the source electrode layer and the drain electrode layer.

Abstract: A method for producing a semiconductor device includes forming an aluminum layer on a core substrate, anodizing the aluminum layer into an alumina layer having a plurality of nanoholes, forming an n-type GaN layer by growing crystals of a compound semiconductor such as an n-type GaN on the alumina layer and inside the nanoholes, and dissolving the alumina layer with an acid. As a result, gaps are formed and a structure in which the core substrate is joined to the n-type GaN layer through portions, other than the gaps, having a very small area is generated. Then a laser beam is applied to the n-type GaN layer through the core substrate to separate the n-type GaN layer from the core substrate by a laser lift-off technique.

Abstract: A method of manufacturing a memory device and a phase-change memory device is presented. The method of manufacturing the memory device includes performing Ge ion implantation on a top surface of a first layer. The method also includes performing a fast heat treatment on the ion-implanted first layer. The method also includes forming a second layer on a top of the fast heat-treated first layer.

Abstract: Methods of making a light emitter are disclosed herein. An embodiment of a method comprises fabricating a line of first leads, the line of first leads comprising a plurality connected individual first leads; fabricating a line of second leads, the line of second leads comprising a plurality of connected individual second leads; physically connecting the line of first leads to the line of second leads, wherein a first individual first lead is adjacent a first individual second lead; attaching a light emitting device to the first individual first lead; electrically connecting the light emitting device to the first individual second lead; encapsulating a portion of the individual first lead and a portion of the individual second lead as a single unit; and separating the encapsulated first individual lead and the second individual lead from the first line of leads and the second line of leads.

Abstract: Mask sets, layout design, and methods for forming contacts in devices are described. In one embodiment, a semiconductor device includes a plurality of contacts disposed over a substrate, the plurality of contacts being disposed as rows and columns on an orthogonal grid, each row of the plurality of contacts is spaced from an neighboring row of the plurality of contacts by a first distance, and each column of the plurality of contacts is spaced from an neighboring column of the plurality of contacts by a second distance.

Abstract: An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost.

Abstract: Method and system for forming one or more predetermined patterns on a substrate for making a photovoltaic device. The method includes aligning at least a first droplet source with a substrate, dispensing one or more first droplets associated with one or more first materials from the first droplet source, and forming at least a first pattern of one or more second materials on the substrate by at least the first droplet source. Additionally, the method includes providing a first light beam incident on at least the first pattern, obtaining a first signal associated with the first pattern in response to the first light beam, processing information associated with the first signal, and determining one or more first characteristics of the first pattern based on at least information associated with the first signal.

Abstract: In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.

Abstract: The present invention provides a production method of a semiconductor device, involving formation of a flattening layer and easy process for layers formed on a semiconductor layer, and also provides a semiconductor device preferably produced by such a production method. The present invention further provides an exposure apparatus preferably used in such a production method.

Abstract: According to one embodiment, a method for the production of a stop zone in a doped zone of a semiconductor body comprises irradiating the semiconductor body with particle radiation in order to produce defects in a crystal lattice of the semiconductor body. The semiconductor body is exposed to an environment containing dopant atoms, during which dopant atoms are indiffused into the semiconductor body at an elevated temperature.

Abstract: In a thin film transistor including an oxide semiconductor, an oxide cluster having higher electrical conductance than the oxide semiconductor layer is formed between the oxide semiconductor layer and a gate insulating layer, whereby field effect mobility of the thin film transistor can be increased and increase of off current can be suppressed.

Abstract: A semiconductor device is described having an integrated high-k dielectric layer and metal control gate. A method of fabricating the same is described. Embodiments of the semiconductor device include a high-k dielectric layer disposed on a floating gate. The high-k dielectric layer defines a recess. A metal control gate is formed in the recess.

Abstract: An electrical structure and method of forming. The method includes providing a semiconductor structure comprising a semiconductor substrate, a buried oxide layer (BOX) formed over the semiconductor substrate, and a silicon on insulator layer (SOI) formed over and in contact with the BOX layer. The SOI layer comprises shallow trench isolation (STI) structures formed between electrical devices. A first photoresist layer is formed over the STI structures and the electrical devices. Portions of said first photoresist layer, portions of the STI structures, and portions of the BOX layer are removed resulting in formed trenches. Ion implants are formed within portions of the semiconductor substrate. Remaining portions of the first photoresist layer are removed. A dielectric layer is formed over the electrical devices and within the trenches. A second photoresist layer is formed over the dielectric layer. Portions of the second photoresist layer are removed.

Abstract: A memory device with band gap control is described. A memory cell can include a conductive oxide layer in contact with and electrically in series with an electronically insulating layer. A thickness of the electronically insulating layer is configured to increase from an initial thickness to a target thickness. The increased thickness of the electronically insulating layer can improve resistive memory effect, increase a magnitude of a read current during read operations, and lower barrier height with a concomitant reduction in band gap of the electronically insulating layer. The memory cell can include a memory element that comprises the conductive oxide layer and the electronically insulating layer and can optionally include a non-ohmic device (NOD). The memory cell can be positioned in a two-terminal cross-point array between a pair of conductive array lines across which voltages for data operations are applied. The memory cell and array can be fabricated BEOL.

Abstract: A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator.

Abstract: Provided is a method of manufacturing an oxide semiconductor thin film transistor using a transparent oxide semiconductor as a material for a channel. The method of manufacturing the oxide semiconductor thin film transistor includes forming a passivation layer on a channel layer and performing an annealing process for one hour or more at a temperature of about 100° C. or above.

Abstract: A population of nanowires can be prepared by a method involving electric field catalyzed growth and alteration based on surface charge density.

Abstract: A semiconductor device includes an insulated-gate field-effect transistor which is disposed on a semiconductor substrate having an element formation plane in a (110) plane direction, and which has a channel length direction in a <?110> direction, and a first element isolation insulation film which is buried in a trench in an element isolation region of the semiconductor substrate and has a positive expansion coefficient, the first element isolation insulation film applying a compressive stress by operation heat to the insulated-gate field-effect transistor in the channel length direction.

Abstract: An electronic device includes a transistor, wherein the electronic device can include a semiconductor layer having a primary surface, a channel region, a gate electrode, a source region, a conductive electrode, and an insulating layer lying between the primary surface of the semiconductor layer and the conductive electrode. The insulating layer has a first region and a second region, wherein the first region is thinner than the second region. The channel region, gate electrode, source region, or any combination thereof can lie closer to the first region than the second region. The thinner portion can allow for faster switch of the transistor, and the thicker portion can allow a relatively large voltage difference to be placed across the insulating layer. Alternative shapes for the transitions between the different regions of the insulating layer and exemplary methods to achieve such shapes are also described.

Abstract: A field-effect transistor provided with at least a semiconductor layer and a gate electrode disposed over the above-described semiconductor layer with a gate insulating film therebetween, wherein the above-described semiconductor layer includes a first amorphous oxide semiconductor layer having at least one element selected from the group of Zn and In, and a second amorphous oxide semiconductor layer having at least one element selected from the group of Ge and Si and at least one element selected from the group of Zn and In. The composition of the above-described first amorphous oxide semiconductor layer is different from the composition of the above-described second amorphous oxide semiconductor layer.

Abstract: An inorganic two-phase nanowire structure including an inorganic semiconducting nanoporous charge conducting phase, and, an inorganic semiconductor nanowire array disposed within at least one of the pores of the nanoporous charge conducting phase.

Abstract: Laser device comprising: a laser source (10) including a light emitting structure (1); a guide structure (40) to deliver light generated by the emitting structure, this guide structure (40) comprising at least a first portion (40.1) and a second portion (40.2), the first portion housing a diffraction grating (3) that forms a reflector of the laser source and cooperates with the emitting structure (1), the second portion (40.2) being a waveguide that delivers light generated by the emitting structure (1) and propagated in the first portion (40.1). The emitting structure (1) is made using the III-V technology or II-VI technology, and the guide structure (40) is made using the silicon technology.

Abstract: A compound semiconductor workpiece with reduced defects and greater strength that uses Group II-VI semiconductor nanoislands on a substrate. Additional layers of Group II-VI semiconductor are grown on the nanoislands using MBE until the newly formed layers coalesce to form a uniform layer of a desired thickness. In an alternate embodiment, nanoholes are patterned into a silicon nitride layer to expose an elemental silicon surface of a substrate. Group II-VI semiconductor material is grown in the holes until the layers fill the holes and coalesce to form a uniform layer of a desired thickness. Suitable materials for the substrate include silicon and silicon on insulator materials and cadmium telluride may be used as the Group II-VI semiconductor.

Abstract: A Periodic Table Group 13 metal nitride crystal is grown by causing a reaction of a Periodic Table Group 13 metal phase with a nitride-containing molten salt phase to proceed while removing a by-product containing a metal element except for Periodic Table Group 13 metals, from the reaction field. According to this process, a high-quality Periodic Table Group 13 metal nitride bulk crystal can be produced under low pressure or atmospheric pressure.

Abstract: A method for fabricating a semiconductor nanowire that has first and second regions is provided. A catalyst particle is put on a substrate. A first source gas is introduced, thereby growing the first region from the catalyst particle via a vapor-liquid-solid phase growth. A protective coating is formed on a sidewall of the first region, and a second source gas is introduced to grow the second region extending from the first region via the liquid-solid-phase growth.

Abstract: Composite of layers which comprises a dielectric layer and a layer which comprises pyrogenic zinc oxide and is bonded to the dielectric layer. Process for producing the composite of layers, in which the pyrogenic zinc oxide is applied to the dielectric layer in the form of a dispersion in which the zinc oxide particles are present with a mean aggregate diameter of less than 200 nm, and the zinc oxide layer is dried and then treated at temperatures of less than 200° C. Process for producing the composite of layers, in which the pyrogenic zinc oxide is applied to a substrate layer or a composite of substrate layers in the form of a dispersion in which the zinc oxide particles are present with a mean aggregate diameter of less than 200 nm to form a zinc oxide layer, and then the zinc oxide layer and the substrate layer are treated at temperatures of less than 200° C., and then a dielectric layer is applied to the zinc oxide layer. Field-effect transistor which has the composite of layers.

Abstract: A light-emitting device, such as a light-emitting diode (LED), is grown on a substrate including a ZnO-based material. The structure includes a plurality of semiconductor layers and an active layer disposed between the plurality of semiconductor layers. The device is removed from the substrate or the substrate is substantially thinned to improve light emission efficiency of the device.

Abstract: According to some embodiments, the present invention provides a nanoelectronic device based on a nanostructure that may include a nanotube with first and second ends, a metallic nanoparticle attached to the first end, and an insulating nanoparticle attached to the second end. The nanoelectronic device may include additional nanostructures so a to form a plurality of nanostructures comprising the first nanostructure and the additional nanostructures. The plurality of nanostructures may arranged in a network comprising a plurality of edges and a plurality of vertices, wherein each edge comprises a nanotube and each vertex comprises at least one insulating nanoparticle and at least one metallic nanoparticle adjacent the insulating nanoparticle. The combination of at least one edge and at least one vertex comprises a diode. The device may be an optical rectenna.

Abstract: A device including semiconductor nanocrystals and a layer comprising a doped organic material disposed over the substrate and in electrical connection with at least one semiconductor nanocrystals is disclosed. Methods for making the device and for improving the efficiency of a device are also disclosed.

Abstract: An LED device including a support structure with at least one LED die mounted thereon, a recess formed in a part of the support structure from a side of the LED die, and a lens formed over the support structure to encapsulate the LED die and the recess, thereby forming a protrusion in the support structure is disclosed.

Abstract: This disclosure provides methods to integrate heat generating nanoparticles to microelectromechanical (MEMs) and photonic devices such as microbolometers and thermopiles for better photodetection and electrical energy generation. Nanoparticles include noble metal and semiconductor nanocrystals of different shapes, as light sensing and heat generating materials.

Abstract: It is an object to provide an oxide semiconductor which is suitable for use in a semiconductor device. Alternatively, it is another object to provide a semiconductor device using the oxide semiconductor. Provided is a semiconductor device including an In—Ga—Zn—O based oxide semiconductor layer in a channel formation region of a transistor. In the semiconductor device, the In—Ga—Zn—O based oxide semiconductor layer has a structure in which crystal grains represented by InGaO3(ZnO)m (m=1) are included in an amorphous structure represented by InGaO3(ZnO)m (m>0).

Abstract: An electrical generator includes a substrate, a semiconductor piezoelectric structure having a first end and an opposite second end disposed adjacent to the substrate, a first conductive contact and a second conductive contact. The structure bends when a force is applied adjacent to the first end, thereby causing an electrical potential difference to exist between a first side and a second side of the structure. The first conductive contact is in electrical communication with the first end and includes a material that creates a Schottky barrier between a portion of the first end of the structure and the first conductive contact. The first conductive contact is also disposed relative to the structure in a position so that the Schottky barrier is forward biased when the structure is deformed, thereby allowing current to flow from the first conductive contact into the first end.

Abstract: Methods, devices, and compositions of matter related to high efficiency InGaN-based photovoltaic devices. The disclosed synthesis of semiconductor heterostructures may be exploited to produce higher efficiency, longer lasting, photovoltaic cells.

Abstract: An integrated circuit arrangement includes a Shockley diode or a thyristor. An inner region of the diode or of the thyristor is completely or partially shielded during the implantation of a p-type well. This gives rise to a Shockley diode or a thyristor having improved electrical properties, in particular with regard to the use as an ESD protection element.

Abstract: A thin film transistor formed by using a metal induced lateral crystallization process and a method for fabricating the same. The thin film transistor comprises an insulating substrate, an active layer formed of polycrystalline silicon and having source/drain regions and a channel region, and a gate electrode formed on a gate insulating layer. The active layer has at least two metal induced lateral crystallization (MILC) regions.

Abstract: A method of making a nonvolatile memory device includes fabricating a diode in a low resistivity, programmed state without an electrical programming step. The memory device includes at least one memory cell. The memory cell is constituted by the diode and electrically conductive electrodes contacting the diode.

Abstract: A method for producing quantum dots embedded in a matrix on a substrate includes the steps of: depositing a precursor on the substrate, the precursor including at least one first metal or a metal compound; contacting the deposited precursor and uncovered areas of the substrate with a gas-phase reagent including at least one second metal and/or a chalcogen; and initiating a chemical reaction between the precursor and the reagent by raising a temperature thereof simultaneously with or subsequent to the contacting so that the matrix consists exclusively of elements of the reagent.

Abstract: A semiconductor laser device includes a first cavity facet formed on an end of the semiconductor element layer on a light-emitting side of a region including the light emitting layer, a first insulating film, made of AlN, formed on a surface of the first cavity facet and a second insulating film, made of AlOXNY (0?X<1.5, 0<Y?1), formed on a surface on an opposite side of the first insulating film to the first cavity facet. A first interface between the first insulating film and the second insulating film has a first recess portion and a first projection portion.

Abstract: A solar cell includes an electron conductor, a plurality of quantum dots on a surface of the electron conductor forming a quantum dot layer, and a supplemental light-absorbing material in one or more gaps in the quantum dot layer. The supplemental light-absorbing material is capable of absorbing light that passes through the one or more gaps in the quantum dot layer and converting the absorbed light into holes and electrons. The supplemental light-absorbing material may also inhibit a hole conductor from coming into contact with the electron conductor. The supplemental light-absorbing material could include one or more polymers, semiconductors, fluorophores, metal particles, nanowires, nanotubes, and nanoparticles.

Abstract: Methods of growing Group-III nitride thin-film structures having reduced dislocation density are provided. Methods in accordance with the present invention comprise growing a Group-III nitride thin-film material while applying an ion flux and preferably while the substrate is stationary or non-rotating substrate. The ion flux is preferably applied as an ion beam at a glancing angle of incidence. Growth under these conditions creates a nanoscale surface corrugation having a characteristic features size, such as can be measured as a wavelength or surface roughness. After the surface corrugation is created, and preferably in the same growth reactor, the substrate is rotated in an ion flux which cause the surface corrugation to be reduced. The result of forming a surface corrugation and then subsequently reducing or removing the surface corrugation is the formation of a nanosculpted region and polished transition region that effectively filter dislocations.